KR101099782B1 - Establishing method for network synchronization and time synchronization in Ethernet system - Google Patents

Abstract

Disclosed is a method for setting network synchronization and time synchronization in an Ethernet system, wherein a pi device of an upper gateway is set as a master, and a pi device of a lower gateway connected to a pi device of an upper gateway set as a master is set as a slave. In the clock divider of the lower gateway, the slave clock used by the lower gateway is transferred to the receiving clock that is synchronized with the reference clock used by the upper gateway, and distributed based on the reference clock used by the upper gateway set as the master. After the clock network synchronization is set, the real time packet is generated by using the message that is the target of traffic delay measurement in the upper gateway and the reference clock used in the upper gateway. And determining and comparing the delay time of each gateway while transmitting and receiving the generated real-time packet to and from each gateway constituting Ethernet, and setting time synchronization of each gateway located on the Ethernet. Accordingly, the present invention does not lose or modify information between the exchange, the gateway, and the terminal in Ethernet, and can guarantee accurate processing of the information and better service quality.

Ethernet, Network Sync, Time Sync, Switch, Gateway, IEEE 802.3, 1588v2

Description

Establishing method for network synchronization and time synchronization in Ethernet system

The present invention relates to a network synchronization and time synchronization setting method in an Ethernet system.

Generally, asynchronous Ethernet is the most widely installed local area network technology, defined as a standard in the Institute of Electrical and Electronics Engineers (IEEE) 802.3, developed by Xerox, and developed by DEC, Intel, etc. in addition to Xerox. .

The most commonly installed Ethernet system is called 10BASE-T and provides a transmission rate of 10 Mbps. All devices are connected by cable and competitively accessed using the Carrier Sense Multiple Access / Collision Detect (CSMA / CD) protocol specified in IEEE 802.3. Fast Ethernet and 100BASE-T provide up to 100 Mbps and are commonly used as the backbone of local area networks to support workstations with 10BASE-T cards. Gigabit Ethernet supports higher backbone speeds as high as 1,000 Mbps.

Since the conventional Ethernet is competitively accessed using the CSMA / CD protocol defined in IEEE 802.3, an upper layer service frame is generated and transmitted as an Ethernet frame while maintaining an Inter Frame Gap (IFG) interval. At this time, regardless of the type of higher service frame, transmission is performed in the order of occurrence. In other words, Ethernet is one of the most commonly used technologies to transfer data between different terminals or between different users.

Ethernet is known as a technology that is not suitable for video or voice transmission that is sensitive to transmission time delay because the same priority is given to all Ethernet frames and CSMA / CD transmission is transmitted through competition.

Recently, however, as video and voice transmissions sensitive to transmission time delays increase and the proportion of data transmission increases, methods for eliminating the problems caused by such transmission delays have been proposed while maintaining the Ethernet method.

In the conventional Ethernet, the information transmitted and received between the gateways is lost, and in media and real-time communications where the amount of information transmitted / received, such as voice communication or video communication, fluctuates every time, the information is not lost or modified, so that time and clocks are guaranteed. Network motivation is needed.

However, in the existing Ethernet boards forming the Ethernet, only 1588v2 and 802.1AS standards use only the clock phase value of each Ethernet gateway to form mutual time and network synchronization. Processing and time could not be guaranteed. Therefore, a device that simultaneously performs clock network synchronization and time synchronization is needed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a network synchronization and time synchronization setting method in an Ethernet system to synchronize network synchronization and time synchronization between each gateway having a link in asynchronous Ethernet.

Another object of the present invention is to further configure a clock divider including a network synchronization and time synchronization function in the gateway, so that the master according to the IEEE 802.3 standard at the gateway without having to configure the network synchronization device in the middle of the switch device as in the conventional method. In addition, the present invention provides a method for configuring network synchronization and time synchronization in an Ethernet system that can synchronize network synchronization and time synchronization using slave interface characteristics and 1588v2 standard packet communication.

In order to achieve the above object, a network synchronization and time synchronization setting method in an Ethernet system according to the present invention is a method for setting synchronization between each gateway constituting an asynchronous Ethernet system, which includes: (1) a gateway constituting Ethernet; Set the PHY device of the upper gateway as the master, set the slave device's pi device connected to the pi device of the upper gateway set as the master as slave, and the slave clock used by the lower gateway in the clock divider of the lower gateway. (B) switching and distributing the signal to a reception clock synchronized with a reference clock used in the upper gateway to form a clock network synchronization between the upper gateway and the lower gateway based on the reference clock used in the upper gateway configured as the master; Stage 1 After setting the clock network synchronization through the network, the real time packet is generated by using the message targeted for the traffic delay measurement in the upper gateway and the reference clock used in the upper gateway, and the generated real time packet is generated in each gateway configuring the Ethernet. Determining and comparing the delay time of each gateway while transmitting and receiving, and setting the time synchronization of each gateway located on the Ethernet.

In this case, step (1) described above includes (1-1) setting a state of the pi device connected to the lower gateway in the upper gateway among the gateways constituting the Ethernet as a master, and (1-2) lower level connected to the upper gateway. Setting the status of the pi device connected to the pi device of the upper gateway set as the master at the gateway as a slave, and (1-3) whether a link is formed between the upper gateway set as the master at the lower gateway and the lower gateway set as the slave. (1-4) When a link is established between the upper gateway and the lower gateway, the clock divider of the lower gateway checks the status of the pi device set as the slave, and sets the slave clock used in the lower gateway as the master. Receive Clock Accepted from Gateway To the switch device and the pi device to distribute the received clock from the upper gateway transferred through the step (1-4) in the clock divider of the lower gateway (1-5) and use it in the upper gateway set as the master. And forming a clock network synchronization between the upper gateway and the lower gateway based on the reference clock.

In the above-described step (2), after setting the clock network synchronization through the steps (2-1) and (1), the central processing unit of the upper gateway uses a message that is the target of traffic delay measurement and the reference clock used in the upper gateway. Generating and outputting a real time packet, and a packet transmitted from a clock divider or an upper gateway of an upper gateway, which receives the real time packet generated in (2-2) and (2-1) from the central processing unit. Storing a Rx time stamp at a start frame delimiter (SFD) time point in a format of a packet in a clock divider of a lower gateway received through the storage unit; and (2-3) SFD in a format of a packet. After storing the time at the time of reception, the clock divider checks the length / type information of the packet format and inputs the packet according to the 1588v2, 802.1AS standard. Determining whether it is a sync packet, a follow-up packet, a packet delay request / response packet, and (2-4) the inputted packet according to the 1588v2 or 802.1AS standard. If it is not a sync packet, follow-up packet, or packet delay request / response packet, the clock divider outputs the packet to the switch device to perform basic packet processing performed by the gateway, and (2-5) (2-3) If the inputted packet is the 1588v2, the sync packet according to the 802.1AS standard, the follow-up packet, and the packet delay request / response packet, the clock divider transmits a transmission time point (Tx time stamp) at the SFD time point of the output packet. Is stored in the storage, or the reception time point and the transmission time point previously stored in the storage part are inserted into the User Datagram Protocol (UDP) field, or the packet delay value is calculated and calculated by the central processing unit. After inserting the delay value into the UDP field, outputting the packet to the upper gateway or lower gateway through the pi device, and the upper gateway or lower gateway receiving the packet through the steps (2-6) and (2-5). And setting the time synchronization by performing a correction to change the time of the lower gateway to the time of the upper gateway based on the corresponding packet including the time message in the clock divider.

As described above, according to the network synchronization and time synchronization setting method of the Ethernet system of the present invention, the network synchronization and time synchronization functions are not required in the asynchronous Ethernet as in the conventional method, without having to configure the network synchronization device in the middle of the switch device. Based on the pi characteristics according to the IEEE 802.3 standard, each gateway that has a link is configured as a master or slave to synchronize the clock network in the gateway that additionally configured the clock divider including the clock divider, and is used in the 1588v2 message and the top gateway that are the targets of the traffic delay measurement. Time synchronization is performed using a timer made using a reference clock that does not lose or change information (video, data, etc.) between exchanges, gateways, and terminals, thereby ensuring accurate processing and better quality of service. Filial piety There is.

Hereinafter, a method of setting network synchronization and time synchronization in an Ethernet system of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram schematically showing the configuration of an Ethernet system to which the method of the present invention is applied, and FIG. 2 is a diagram schematically showing the configuration of an upper gateway and a lower gateway for network synchronization setting according to the method of the present invention. Is a diagram schematically illustrating a configuration of a gateway for setting time synchronization according to the method of the present invention.

As shown in FIG. 1, the present invention provides a plurality of processes for transmitting / receiving large-capacity, real-time media data including voice and video transmitted from the network server 100 in accordance with network synchronization and time synchronization without loss or modification of information. Includes a gateway 200.

The gateway 200 is hierarchical to the upper gateway 210 that sets the state of the pie device as the master and the upper gateway 210 set as the master by using a PHY characteristic (MII management configuration) according to the IEEE 802.3 standard. The sub gateway 220 is connected to the sub gateway 220 to set the state of the pi device as a slave using a pi characteristic according to the IEEE 802.3 standard. In this case, the reason why the gateway 200 is divided into a master and a slave and designated as the upper gateway 210 and the lower gateway 220 is because the clock phases used in each gateway 200 are different from each other. This is to use the reference clock used in 210 as a common clock in the lower gateway 220.

The configuration for setting network synchronization between the respective gateways 200 will be described in detail with reference to FIG. 2. The upper gateway 210 includes a switch device 211 that performs an input packet processing using a reference clock 'a'. And a master pie device 212 that transmits and receives data to and from the lower gateway 220 in which the link is formed using the reference clock 'a'. The lower gateway 220 may include a slave pie device 221 and a slave pie device for applying a received clock 'b' received from the master pie device 212 of the upper gateway 210 having the link to the clock divider 222. When the reception clock 'b' is applied from the 221, the clock which transfers the slave clock used before the link with the upper gateway 210 to the reception clock 'b' is distributed to each component of the lower gateway 220 and supplied. When the splitter 222, the switch device 223 which handles the transmission and reception of data with the upper gateway 210, and the lower gateway 220 and another lower gateway are hierarchically connected, the pi characteristics according to the IEEE 802.3 standard are used. And a master pie device 224 that sets the state to the master.

At this time, the reference clock 'a' of the upper gateway 210 and the reception clock 'b' received by the lower gateway 220 having a link are synchronized. In addition, the role of the clock divider 222 of the lower gateway 220 is required for transmission and reception synchronization between the upper gateway 210 set as the master and the lower gateway 220 set as the slave in a hierarchical synchronization state. That is, the clock divider 222 distributes the slave clock to the pie device 221 and the switch device 223 when the link with the upper gateway 2210 is not formed, and provides the upper gateway 210 and the lower gateway 220. When a link is established between the slave pi devices 221, the slave clock is read to switch to a reception clock 'b' that is synchronized with the reference clock 'a' of the upper gateway 210 to serve as a slave clock. will be. Accordingly, since the data transmitted from the switch device 223 of the lower gateway 220 to the upper gateway 210 also becomes a clock value that is synchronized, the clock synchronization between the upper gateway 210 and the lower gateway 220 is matched.

On the other hand, even if the clock phase value is adjusted between the upper gateway 210 and the lower gateway 220 hierarchically as in the above-described configuration, in the media communication in which the amount of information to be transmitted / received, such as voice and video communication, varies with time, it is necessary to synchronize time synchronization. do.

In order to achieve time synchronization, a clock divider 214 capable of processing a message according to the 1588v2, 802.1AS standard between the upper gateway 210 and the lower gateway 220 is required. That is, since the switch device configured in the existing gateway cannot perform such a function, the clock divider 214 configures a function capable of processing a real time packet, thereby switching clocks and real time for the network synchronization setting described above. Perform packet processing.

The configuration for setting the time synchronization between the respective gateways 200 will be described in detail with reference to FIG. 3 (in this case, based on the time synchronization setting in the upper gateway 210). A switch device 211 that performs data transmission / reception, a master pie device 212 that transmits / receives data to / from a lower gateway 220 having a link, a sync, a follow-up, and a packet delay response. A central processing unit 213 for generating and outputting a Pdeley req / resp packet, a MAC (Media Access Control) processing unit 214a for classifying a format of a packet input from the central processing unit 213, and time information in the gateway In the slave state, a timer 214b and a lookup table (LUT) 214c are used to update the time information in the gateway (that is, the lower gateway) using the master information. If a packet input from the central processing unit 213 is a 1588v2, a sync packet according to the 802.1AS standard, a follow-up packet, or a packet delay request / response packet, a transmission time point (Tx time stamp) at the SFD time point of the output packet is stored. The reception time point and the transmission time point stored in the storage unit 215 or previously stored in the storage unit 215 are inserted into a UDP field or the packet delay value is transmitted through the central processing unit 213. After calculating and inserting the calculated packet delay value into the UDP field, the clock divider 214 outputs the packet to the lower gateway 220 through the pi device 212, the time point at which the packet is input, and the time output. The storage unit 215 stores a viewpoint.

At this time, the clock divider 214 outputs the packet to the switch device 211 if the packet input from the central processing unit 213 is not a 1588v2, a sync packet, a follow-up packet, or a packet delay request / response packet according to the 802.1AS standard. To perform the basic packet processing performed by the gateway. In addition, unlike the above description, the lower gateway 220 uses the pi device 221 instead of the central processing unit 213 to synchronize the sync packet, the follow-up packet, and the packet delay request / response packet according to the 1588v2 and 802.1AS standards. It may be received from the gateway 210 or another lower gateway. In this case, the same operation as described above may be performed. That is, the lower gateway 220 as well as the upper gateway 210 may receive and process packet information for time synchronization between the gateways.

As such, the clock divider 214 exchanges time messages with the lower gateway 220 and changes the time value of the upper gateway 210 from the lower gateway 220 which is hierarchically connected to each other. Motivated.

Next, an embodiment of a network synchronization and time synchronization setting method in the Ethernet system according to the present invention configured as described above will be described in detail with reference to FIGS. 4 to 7.

4 to 6 are flowcharts showing in detail the operation of the network synchronization and time synchronization setting method in the Ethernet system according to the present invention, and FIG. 7 is a view showing a part of a format of a packet used for the time synchronization setting of FIG. to be.

First, the lower gateway 220 connected to the pi device 212 of the upper gateway 210 of the gateway 200 configuring the Ethernet as the master and connected to the pie device 212 of the upper gateway 210 set as the master. The pi device 221 of the slave is set as a slave, and the clock divider 222 of the lower gateway 220 receives the slave clock used by the lower gateway 220 in synchronization with the reference clock used by the upper gateway 210. A clock network synchronization is formed between the upper gateway 210 and the lower gateway 220 based on the reference clock used in the upper gateway 210 set as the master by switching to and distributing the clock (S100).

The above-described step S100 will be described in more detail with reference to FIG. 5. Among the gateways 200 constituting Ethernet, the upper gateway 210 is connected to the lower gateway 220 based on a pi characteristic according to the IEEE 802.3 standard. The state of 212 is set to the master (S110).

The lower gateway 220 connected to the upper gateway 210 sets the state of the pie device 221 connected to the pie device 212 of the upper gateway 210 set as the master as a slave (S120).

In this case, when the state of the pi device 212 of the upper gateway 210 is set as a master in step S110, the reference clock supplied to the switch device 211 or the pi device 212 of the upper gateway 210 is one same clock. When used, the transmit clock generated at pi device 212 is synchronous with the reference clock.

In addition, setting the state of the pi device 221 to the slave in the lower gateway 220 in step S120 is because the clock phase value of the upper gateway 210 and the lower gateway 220 is different, the upper gateway 210 set as the master. This is to use only one reference clock which is used in one common clock.

After setting the upper gateway 210 and the lower gateway 220 as a master and a slave through the steps S110 and S120, the lower gateway 220 is the lower gateway 220 set as the upper gateway 210 and the slave as the master. It is determined whether the link is formed between (S130).

If the link between the upper gateway 210 and the lower gateway 220 is not formed, the clock divider 222 of the lower gateway 220 may convert the slave clock used by the lower gateway 220 into the switch device 223 and the pi. To the device 224 for distribution.

However, if a link between the upper gateway 210 and the lower gateway 220 is formed as a result of step S130, the clock divider 222 of the lower gateway 220 checks the state of the pi device 221 set as the slave, The slave clock used in the gateway 220 is transferred to the received clock applied from the upper gateway 210 set as the master (S150).

In this case, when a link between the upper gateway 210 and the lower gateway 220 is formed, the reference clock used in the upper gateway 210 set as the master and the pie device of the lower gateway 220 set as the slave may be determined. The receive clock applied to 221 is synchronized.

The clock divider 222 of the lower gateway 220 that switches the internal slave clock to the received clock applied from the upper gateway 210 through step S150 switches the received clock applied from the upper gateway 210 to the switch device 223. ) And the pie device 224, and supplies (S160).

Then, based on the reference clock used in the upper gateway 210 set as the master, the upper gateway 210 and the lower gateway 220 form a clock network synchronization (S170). That is, since the data value outputted from the switch device 223 to the upper gateway 210 through the step S170 is a clock value for synchronizing, the synchronization between the upper gateway 210 and the lower gate 220 is matched.

Meanwhile, in the above-described network synchronization setting in step S100, another lower gateway may be connected hierarchically to the lower gateway. In this case, as shown in FIG. 2, the lower gateway 220 set as a slave to another lower gateway. Set the pi device 224 to be connected as the master, and set the pi device of another sub gateway connected with the pi device 224 of the sub gateway 220 set as the master to the slave, and in the clock divider of another sub gateway. The slave clock used by another lower gateway is transferred to a receiving clock which is synchronized with a reference clock (that is, a receiving clock applied from the upper gateway 210 set as a master) used by the lower gateway 220, and is set as a master. Based on the reference clock used in the lower gateway 220 A clock network synchronization is formed between the lower gateway 220 and another lower gateway.

Now, after setting the network synchronization between the gateway through the step S100, even if the clock phase value is matched between the upper gateway 210 and the lower gateway 220 hierarchically connected, the amount of information transmitted / received such as voice and video communication fluctuates every moment. In media communication, it is necessary to synchronize time.

That is, after the clock network synchronization is set through the step S100, the upper gateway 210 generates a real time packet using a message that is a target of traffic delay measurement and a reference clock used by the upper gateway 210, and generates the generated real time packet. The packet is transmitted and received between each gateway 200 constituting the Ethernet, and the delay time of each gateway 200 is determined and compared to set the time synchronization of each gateway 200 located on the Ethernet (S200).

The above-described step S200 will be described in more detail with reference to FIG. 6. After setting the clock network synchronization through the step S100, the central processing unit 213 of the upper gateway 210 may transmit a message and an upper gateway (a target of traffic delay measurement). A real time packet (see FIG. 7) is generated using the reference clock used in 210, and the generated real time packet is output to the clock divider 214 (S205).

In step S205, the clock divider 214 of the upper gateway 210 receiving the real time packet from the central processing unit 213 classifies the format of the packet input through the built-in MAC processing unit 214a to check SFD information. In operation S210, the reception time point at the SFD time point is stored in the storage unit 215.

After storing the reception time point at the SFD time point in the format of the packet in the storage unit 215, the clock divider 214 checks the length / type information of the packet format and inputs the packet according to the 1588v2, 802.1AS standard. It is determined whether it is a sync packet, follow-up packet, or packet delay request / response packet (S215).

If it is determined that the input packet is not a 1588v2, a sync packet according to the 802.1AS standard, a follow-up packet, or a packet delay request / response packet, the clock divider 214 outputs the packet to the switch device 211 to be performed by the gateway. Basic packet processing is performed (S220).

In operation S215, if the input packet is a sync packet, a follow-up packet, or a packet delay request / response packet according to the 1588v2 or 802.1AS standard, the clock divider 214 may sink the input packet to the 1588v2 or 802.1AS standard. It is determined whether the packet (S225).

If the determination result is a sync packet, the clock divider 214 stores the transmission time point at the SFD time point of the output packet in the storage unit 215 (S230), and stores the packet in another gateway 200 through the pi device 212. Step S250 outputs the same).

However, if the determination result of step S225 is not the sync packet, the clock distributor 214 determines whether the input packet is a follow-up packet or a packet delay request / response packet (S235).

If the inputted packet is the follow-up packet, the clock divider 214 inserts a reception time point and a transmission time point previously stored in the storage unit 215 into the UDP field through steps S210 and S230 (S240). In operation S250, the packet is output to the other gateway 200 through the pi device 212.

However, if the inputted packet is a packet delay request / response packet as a result of the determination in step S235, the clock divider 214 calculates a packet delay value for correcting latency between the gateways 200 through the central processing unit 213. After that, the packet delay value calculated by the central processing unit 213 is inserted into the UDP field (S245), and the S250 step of outputting the packet to the other gateway 200 through the pie device 212 is performed.

Then, the clock divider of the upper gateway 210 or the lower gateway 220 receiving the packet through step S250 performs a correction to change the time of the lower gateway to the time of the upper gateway based on the corresponding packet including the time message. This will set up the synchronization. That is, each gateway 200 repeatedly transmits / receives the sync packet, follow-up packet, and packet delay request / response packet as described above to give time information (x year x month x day) necessary for each gateway 200. On receiving, it calculates the packet delay to make time synchronization.

At this time, the above-described processing of the sync packet of step S225 and the follow-up packet of step S235 are immediately processed without passing through the central processing unit 213 in the clock divider 214, and the processing of the packet delay request / response packet of step S245 is performed by the clock divider. Since it is not directly performed at 214, the calculation is performed through the central processing unit 213. That is, the present invention can process all data transmitted and received through the pi device 212 in the clock divider 214 itself without the switch device 211 or the central processing unit 213 within the clock divider 214. This reduces the load on the gateway, which allows for faster and more accurate time synchronization settings.

On the other hand, unlike the above description, each of the lower gateway 220 in the time synchronization setting process, the sync packet, follow-up packet, and packet delay request / response packet according to the 1588v2 and 802.1AS standards are higher through the pi device 221. It may be received from the gateway 210 or another lower gateway connected in a hierarchical manner. In this case, the same operation may be performed as described above to set time synchronization between the gateways. That is, the lower gateway 220 as well as the upper gateway 210 may receive and process packet information for time synchronization between the gateways.

Herein, while the present invention has been described with reference to the preferred embodiments, those skilled in the art will variously modify the present invention without departing from the spirit and scope of the invention as set forth in the claims below. And can be changed.

1 is a view schematically showing the configuration of an Ethernet system to which the method of the present invention is applied;

2 is a diagram schematically showing the configuration of an upper gateway and a lower gateway for network synchronization setting according to the method of the present invention;

3 is a diagram schematically illustrating a configuration of a gateway for setting time synchronization according to the method of the present invention;

4 is a flowchart illustrating an operation process of a network synchronization and time synchronization setting method in an Ethernet system according to the present invention;

5 is a flowchart illustrating a process for setting network synchronization of FIG. 4 in detail;

6 is a flowchart illustrating a process for setting time synchronization of FIG. 4 in detail;

FIG. 7 is a diagram illustrating a part of a format of a packet used for setting time synchronization of FIG. 6.

Explanation of symbols on the main parts of the drawings

100: network server 200: gateway

210: upper gateway 211: switch device

212: master pie device 213: central processing unit

214: clock divider 214a: MAC processor

214b: Timer 214c: Lookup Table (LUT)

215: storage 220: lower gateway

221: slave pi device 222: clock divider

223: switch device 224: master pi device

Claims (7)

In a method for establishing synchronization between each gateway constituting an asynchronous Ethernet system, (1) Set the PHY device of the upper gateway among the gateways constituting Ethernet as the master, and set the pi device of the lower gateway connected to the pi device of the upper gateway set as the master as the slave, and the clock divider of the lower gateway. The slave clock used in the lower gateway is transferred and distributed to the receiving clock which is synchronized with the reference clock used in the upper gateway to form a clock network synchronization between the upper gateway and the lower gateway based on the reference clock used in the upper gateway set as the master. To do, and (2) After the clock network synchronization is set through step (1), a real time packet is generated by using a message that is a target of traffic delay measurement in the upper gateway and a reference clock used in the upper gateway, and the generated real time packet Determining and comparing the delay time of each gateway while transmitting and receiving at each gateway constituting Ethernet to set the time synchronization of each gateway located on the Ethernet. Method of setting network synchronization and time synchronization in an Ethernet system that includes. The method of claim 1, Step (1), (1-1) setting the status of the pi device connected to the lower gateway in the upper gateway among the gateways configuring the Ethernet as a master, (1-2) setting the state of the pi device connected to the pi device of the upper gateway set as the master in the lower gateway connected to the upper gateway as the slave; (1-3) checking whether a link is formed between the upper gateway set as the master in the lower gateway and the lower gateway set as the slave; (1-4) When a link is established between the upper gateway and the lower gateway, the clock divider of the lower gateway checks the status of the pi device set as the slave and receives the slave clock used in the lower gateway from the upper gateway set as the master. Switching to a clock, and (1-5) Based on the reference clock used in the upper gateway set as the master by distributing the received clock applied from the upper gateway transferred through the step (1-4) to the switch device and the pi device in the clock divider of the lower gateway. Forming a clock network synchronization between the upper gateway and the lower gateway. Method of setting network synchronization and time synchronization in an Ethernet system that includes. The method of claim 2, When the link between the upper gateway and the lower gateway is formed in the step (1-3), A method of setting network synchronization and time synchronization in an Ethernet system in which a reference clock used in an upper gateway set as a master and a receive clock applied to a pi device of a lower gateway set as a slave are synchronized. The method of claim 2, If the link between the upper gateway and the lower gateway is not formed in the step (1-3), Network synchronization and time synchronization setting method in Ethernet system that distributes slave clock used in lower gateway in switch gateway of lower gateway to switch device and pi device. The method of claim 1, If another lower gateway is hierarchically connected to the lower gateway in the step (1), In the subgate set as slave, the pi device to be connected to another sub gateway is set as the master, the pie device in another sub gateway connected with the pi device of the sub gateway set as the master, as the slave, and the clock of another sub gateway. The slave clock, which is used by another sub-gateway in the distributor, is transferred to the receiving clock that is synchronized with the reference clock used by the sub-gateway, and distributed to the sub-gateway and another sub-gateway based on the reference clock used by the sub gateway set as the master. A method for setting network synchronization and time synchronization in an Ethernet system that forms clock network synchronization between devices. The method of claim 1, Step (2), (2-1) After the clock network synchronization is set through step (1), the central processing unit of the upper gateway generates and outputs a real time packet using a message to be measured for traffic delay and a reference clock used in the upper gateway. Steps, (2-2) The clock divider of the upper gateway receiving the real time packet generated in step (2-1) from the central processing unit or the packet splitter of the lower gateway receiving the packet transmitted from the upper gateway through the pi device. Storing a reception time point (Rx time stamp) at a start frame delimiter (SFD) time point in a storage unit, (2-3) After storing the reception time point at the SFD point in the format of the packet in the storage unit, the clock divider checks the length / type information of the packet format and inputs the packet according to the 1588v2, 802.1AS standard. determining whether the packet is a (sync) packet, a follow-up packet, a packet delay request / response packet, (2-4) If it is determined that the input packet is not a 1588v2, a sync packet, a follow-up packet, or a packet delay request / response packet according to the 802.1AS standard, the clock divider outputs the packet to the switch device to perform the basic operation at the gateway. To perform packet processing, (2-5) If the inputted packet is the 1588v2, the sync packet, the follow-up packet, or the packet delay request / response packet according to the 802.1AS standard as a result of the determination in the step (2-3), the clock divider determines the SFD time point of the output packet. Stores the Tx time stamp in the storage unit, or inserts the reception time point and the transmission time point previously stored in the storage unit into the User Datagram Protocol (UDP) field, or sends the packet through the central processing unit. Calculating the delay value, inserting the calculated packet delay value into the UDP field, and outputting the packet to the upper gateway or the lower gateway through the pi device, and (2-6) Correction of changing the time of the lower gateway to the time of the upper gateway based on the corresponding packet including the time message in the clock distributor of the upper gateway or lower gateway that received the packet through step (2-5). To set up time synchronization Method of setting network synchronization and time synchronization in an Ethernet system that includes. The method of claim 6, Step (2-5) is, (2-5-1) If the inputted packet is the 1588v2, the sync packet, the follow-up packet, or the packet delay request / response packet according to the 802.1AS standard, the clock divider indicates that the input packet is Determining whether it is a sync packet according to the 1588v2, 802.1AS standard, (2-5-2) If the determination result is a sync packet, the clock divider stores the transmission time point (Tx time stamp) at the SFD time point of the output packet in the storage unit, and stores the packet in the upper gateway or lower level through the pi device. Outputting to the gateway, (2-5-3) if the determination result of step (2-5-1) is not a sync packet, determining whether the clock divider is a follow-up packet or a packet delay request / response packet; (2-5-4) If the determination result of the step (2-5-3) is the follow-up packet, the clock divider is pre-stored in the storage through the steps (2-2) and (2-5-2). Inserting the received reception time point and the transmission time point into the UDP field, and outputting the packet to the upper gateway or the lower gateway through the pi device, and (2-5-5) If the determination result of step (2-5-3) is a packet delay request / response packet, the clock divider calculates the packet delay value through the central processing unit, and then calculates the packet delay value calculated by the central processing unit. In the UDP field and output the packet to the upper gateway or lower gateway through the pi device. Method of setting network synchronization and time synchronization in an Ethernet system that includes.

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