KR101097864B1 - Phase change memory device and method of manufacturing the same - Google Patents

Abstract

The present invention discloses a phase change memory device and a manufacturing method thereof in which the amount of current to the set transistor and the reset transistor is different from each other without forming a separate resistor. The disclosed phase conversion memory device includes a set transistor and a reset transistor each having a gate and a source region of the first conductivity type and sharing a drain region of the first conductivity type, wherein the phase conversion memory device comprises: In the source region of the reset transistor, LDD ion implantation of a first conductivity type impurity having a first concentration and a first conductivity type impurity ion implantation having a second concentration higher than the first concentration are performed, while a source of the set transistor is performed. In the region, only LDD ion implantation of the first conductivity type impurity having a first concentration is performed, so that the source region of the set transistor has a higher resistance than the source region of the reset transistor.

Description

Phase change memory device and method of manufacturing the same

1A is a graph for explaining a phase change of a phase change film in a conventional phase change memory element.

Fig. 1B is a circuit diagram showing a conventional phase change memory element.

2A to 2F are cross-sectional views of steps for explaining a method of manufacturing a phase change memory device according to the present invention.

Explanation of symbols on the main parts of the drawings

21 semiconductor substrate 22 device isolation film

23a, 23b: gate 24: LDD region

25 halo area 26 spacer

27: photoresist pattern 28a: first source region

28b: second source region 29: drain region

30: interlayer insulating film 31: contact hole

32: metal wiring C: set transistor

D: reset transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase conversion memory element and a method for manufacturing the same, and more particularly, to a method for manufacturing a set transistor and a reset transistor.

Generally, a memory device is a volatile random access memory (RAM) device that loses input information when the power supply is turned off, and a nonvolatile ROM (Read Only Memory) that maintains the storage state of the input information even when the power supply is turned off. : It is divided into ROM) device. The volatile RAM devices may include DRAM and SRAM, and the nonvolatile ROM devices may include flash memory such as EEPROM (Elecrtically Erasable and Programmable ROM). .

However, although the DRAM has a very good memory device as is well known, high charge storage capability is required, and for this purpose, it is difficult to achieve high integration since the electrode surface area must be increased. In addition, the flash memory requires a higher operating voltage than a power supply voltage in connection with a structure in which two gates are stacked, and thus requires a separate boost circuit to form a voltage required for write and erase operations. Therefore, there is a difficulty in high integration.

Accordingly, many studies have been conducted to develop new memory devices having characteristics of the nonvolatile memory device and having a simple structure. For example, a phase change memory device has recently been developed. ) Has been proposed.

The phase change memory device has a crystalline state having a low resistance of several kW and an amorphous state having a high resistance of a few kW between the electrodes through the current flow between the lower electrode and the upper electrode. From the phase change occurring in two states (amorphous state), the information stored in the cell is determined using the difference in resistance between the crystalline state and the amorphous state.

In other words, the phase conversion memory element uses a chalcogenide film as a phase conversion film. The chalcogenide film is a compound film composed of germanium (Ge), stevidium (Sb) and tellurium (Te). From reversible phase change between the crystalline state of low resistance, that is, the SET state, and the amorphous state of high resistance, that is, RESET, caused by the current, that is, Joule Heat. In the write and read modes, the current flowing through the phase change film is sensed to determine whether the information stored in the phase change memory cell is data '0' in the set state or data '1' in the reset state.

1A is a graph for explaining a phase change of a phase change film in a conventional phase change memory element.

As shown, the phase change film is changed to an amorphous state by heating at a temperature higher than the melting temperature (Tm) for a short time (first operating period; t1) and then cooling at a high speed (curve "A"). Reference). On the other hand, the phase change film is heated after cooling for a longer time than the first operating section t1 (second operating section; t2) at a temperature lower than the melting temperature Tm and higher than the crystallization temperature Tc. Change to the crystalline state (see curve "B").

Therefore, in the writing current required for the phase change of the phase conversion film, a high current and a short pulse are required to make an amorphous state, and a low current to make a crystalline state. It can be seen that a low current and a long pulse are required.

On the other hand, in the phase conversion memory element, because of the above-described driving characteristics, as shown in FIG. 1B, input data is inputted from the node ⓐ to the node ⓑ through the set transistor C or the reset transistor D, or A current path is formed from node ⓐ to node ⓒ. At this time, resistors are formed in the nodes ⓑ and ⓒ to control the amount of current.

Here, each resistor is formed to have a different resistance value, for example, in the case of the set transistor (C) requires a low current, a resistor having a high resistance should be formed, in the case of the reset transistor (D) On the contrary, since a high current is required, a resistor having a low resistance must be formed.

However, in the case of the conventional phase change memory device, a resistor having a different resistance value must be formed in each of the set transistor and the reset transistor, which is not only complicated in terms of processing but also thermal stress and subsequent processing. It is difficult to stably form the resistor, such as deformation of the resistor that has already been formed due to the like.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and provides a phase change memory device and a manufacturing method thereof in which the amount of current to the set transistor and the reset transistor is different from each other without forming a separate resistor. The purpose is to provide.

Another object of the present invention is to provide a phase change memory device and a method of manufacturing the same, which can simplify the process by omitting the formation of resistors having different resistance values in the set transistor and the reset transistor.

In addition, another object of the present invention is to provide a phase change memory device and a method of manufacturing the same, which allow different amounts of current to be applied to the set transistor and the reset transistor stably.

The phase change memory device of the present invention for achieving the above object comprises a set transistor and a reset transistor each having a gate and a first conductive type source region and sharing a drain region. The source region of the reset transistor includes LDD ion implantation of a first conductivity type impurity having a first concentration and a first conductivity type impurity ion implantation having a second concentration higher than the first concentration is performed. In the source region of the set transistor, only LDD ion implantation of the first conductive impurity having a first concentration is performed, so that the source region of the set transistor has a higher resistance than the source region of the reset transistor.

Here, the first conductive type is characterized in that the n-type.

In addition, a phase change memory device of the present invention for achieving the above object, the semiconductor substrate having an element isolation film defining an active region; A set transistor and a reset transistor formed on the substrate active region, each having a gate and a source region of a first conductivity type and sharing a drain region of the first conductivity type; An interlayer insulating film formed on an entire surface of the substrate to cover the set transistor and the reset transistor; And a metal wiring formed in the interlayer insulating layer to contact the source and drain regions of the set transistor and the reset transistor, wherein the source and drain regions of the reset transistor have a first concentration. LDD ion implantation and a first conductivity type impurity ion implantation having a second concentration higher than the first concentration are performed, whereas the source region of the set transistor is only LDD ion implantation of a first conductivity type impurity having a first concentration And the source region of the set transistor has a higher resistance than the source region of the reset transistor.

Here, the set transistor and the reset transistor are each characterized in that a halo region is formed outside the LDD ion implantation region under the gate.

In addition, a method of manufacturing a phase change memory device of the present invention for achieving the above object comprises the steps of: forming a device isolation film defining an active region in a semiconductor substrate; Forming a first gate and a second gate on the active region; A source region of the set transistor is implanted into an active region of one side of the first gate that is not adjacent to the second gate by implanting a first conductive type LDD ion having a first concentration into the active regions of both the first gate and the second gate. Forming; Forming spacers on both sidewalls of the first and second gates, respectively; The first conductive type impurity ion implantation having a second concentration higher than the first concentration is performed in the active region between the first gate and the second gate and the active region on one side of the second gate that is not adjacent to the first gate. Forming a drain region shared by the set transistor and the reset transistor and a source region of the reset transistor; Forming an interlayer insulating film on an entire surface including a source region and a drain region of the first and second gates, the set transistors, and the reset transistors; And forming metal wires in the interlayer insulating layer, the metal wires being in contact with the source and drain regions of the source region reset transistor of the set transistor, respectively.

Here, the method of the present invention, after the step of forming the LDD region, and before the step of forming a spacer, halo ion implantation is performed to the outside of the LDD region below the first gate and the second gate, respectively It further comprises a step.

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(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the technical principle of the present invention will be briefly described. In the present invention, LDD and halo ion implantation are performed in all the source and drain regions of the set transistor and the reset transistor, and then n + ion implantation is performed in the source region of the reset transistor. In contrast, n + ion implantation is not performed in the source region of the set transistor, so that a low amount of current flows due to relatively low doping of the set transistor.

This eliminates the need for further processing to form different resistors in the set transistors and the reset transistors, which can be advantageous in terms of processing, and is particularly stable by being free from significant effects of thermal stress and subsequent processing. Forming a resistor can be achieved, and consequently, the present invention can implement a phase change memory device that is reliably driven.

In detail, FIGS. 2A to 2F are cross-sectional views illustrating processes of manufacturing a phase change memory device according to the present invention.

Referring to FIG. 2A, a trench type isolation layer 22 is formed in the semiconductor substrate 21 to define an active region according to a known process. Thereafter, a gate insulating film, a gate conductive film, and a hard mask film are sequentially formed on the entire surface of the substrate 21 including the device isolation film 22, and then the films are patterned according to a known process to form a first gate on the active region. 23a and the second gate 23b are formed.

Here, as will be described later, the first gate 23a corresponds to the gate of the set transistor, and the second gate 23b corresponds to the gate of the reset transistor. In each of the gates 23a and 23b, the gate insulating film is formed of an oxide film or a nitride film, preferably an oxide film, and the gate conductive film is formed of a laminated film of a polysilicon film and a metal film or a metal silicide film. The hard mask film is made of a nitride film.

Referring to FIG. 2B, LDD (Lightly Doped Drain) ion implantation is performed on n-type impurities such as P or As using the gates 23a and 23b as ion implantation masks to the substrate resultant. N-, that is, low concentration LDD regions 24 are formed in the substrate surface on both the first gate 23a and the second gate 23b.

Referring to FIG. 2C, halo ion implantation is performed on a substrate resultant with a p-type impurity such as B, in order to reduce an electric field, and thereby, an LDD region 24 under gates 23a and 23b. Halo region 25 is formed outside.

Referring to FIG. 2D, after the insulating film for the spacer is deposited on the substrate resultant, the spacer 26 is formed on both sidewalls of the first gate 23a and the second gate 23b by blanket etching the spacer.

Referring to FIG. 2E, after the photoresist is coated on the resultant, the photoresist is exposed and developed to cover the source predetermined region including the first gate 23a in the set transistor formation region while the second gate in the reset transistor formation region. A drain predetermined region which is mutually shared with the source predetermined region including (23b) forms an exposed photoresist pattern 27.

Subsequently, source / drain ion implantation, that is, high concentration ion implantation of n-type impurities, is performed on the substrate resultant using the photoresist pattern 27 as an ion implantation mask, whereby the second gate 23b and the LDD are performed. A reset transistor (D) including a second source region (28a) ion-implanted with a high concentration of n-type impurities including the region (24) and a drain region (29) shared with each other is formed, and the drain region (29) ) And a first transistor 23a and a set transistor C including a low concentration first source region 28a formed only of LDD ion implantation.

Referring to FIG. 2F, the photoresist pattern used as the ion implantation mask is removed according to a known process. Then, the interlayer insulating film 30 is formed on the substrate resultant up to the step, and then the surface is etched back or CMP to planarize.

Subsequently, the interlayer insulating layer 30 is etched to expose contact holes 31 that expose drain regions 29 that are mutually shared with the source regions 28a and 28b of the set transistor C and the reset transistor D, respectively. ). Then, the source regions 28a and 28b of the set transistor C and the reset transistor D and the drain region 29 mutually shared with each other through the contact holes 31 on the interlayer insulating layer 30. Metal wires 32 are formed to contact each other.

Subsequently, although not shown, a series of well-known subsequent processes including a formation of a phase change cell including a stacked structure of a lower electrode, a phase change film, and an upper electrode are sequentially performed to complete the manufacture of the phase change memory device according to the present invention. .

According to the phase change memory device of the present invention as described above, high concentration ion implantation of n-type impurities is performed in the second source region of the reset transistor, while high concentration ion implantation of n-type impurities is performed in the source region of the set transistor. Therefore, the source region of the set transistor may have a resistance higher than that of the second source region of the reset transistor.

Therefore, the phase change memory device according to the present invention can have different resistances between quantum transistors without separately forming resistors having different resistance values in each of the set transistors and the reset transistors. Of course, the source / drain regions are not significantly affected by subsequent processes, and therefore have advantages in terms of properties.

Hereinbefore, the present invention has been described with reference to some examples, but the present invention is not limited thereto, and those skilled in the art to which the present invention pertains have many modifications and variations without departing from the spirit of the present invention. It will be appreciated that it can be added.

As described above, the present invention allows the resistance of the set transistor to be greater than that of the reset transistor through selective performance of source / drain ion implantation, thereby providing a difference in resistance between quantum transistors without any additional process. The process can be simplified.

In addition, since the phase change memory device of the present invention uses the doping difference to give a resistance difference between transistors, the influence of the subsequent process is not large, and thus, the phase change memory device can be reliably driven.

Claims (9)

A phase conversion memory device comprising a set transistor and a reset transistor each having a gate and a source region of the first conductivity type and sharing a drain region of the first conductivity type, In the source region of the reset transistor, LDD ion implantation of a first conductivity type impurity having a first concentration and a first conductivity type impurity ion implantation having a second concentration higher than the first concentration are performed. And source source of the first conductive impurity having a first concentration, so that the source region of the set transistor has a higher resistance than the source region of the reset transistor. Claim 2 has been abandoned due to the setting registration fee. The phase change memory device as claimed in claim 1, wherein the first conductivity type is n-type. A semiconductor substrate having an isolation layer defining an active region; A set transistor and a reset transistor formed on the substrate active region, each having a gate and a source region of a first conductivity type, and sharing a drain region of the first conductivity type; An interlayer insulating film formed on an entire surface of the substrate to cover the set transistor and the reset transistor; And And a metal wiring formed in the interlayer insulating layer to contact the source and drain regions of the set transistor and the reset transistor. While the source region and the drain region of the reset transistor are LDD ion implantation of a first conductive impurity having a first concentration and a first conductive impurity ion implantation having a second concentration higher than the first concentration, The source region of the set transistor is LDD ion implantation of the first conductive impurity having a first concentration only, so that the source region of the set transistor has a higher resistance than the source region of the reset transistor. device. Claim 4 was abandoned when the registration fee was paid. The phase change memory device according to claim 3, wherein the first conductivity type is n-type. Claim 5 was abandoned upon payment of a set-up fee. 4. The phase change memory device as claimed in claim 3, wherein the set transistor and the reset transistor each have a halo region formed outside the LDD ion implantation region under the gate. Forming an isolation layer defining an active region in the semiconductor substrate; Forming a first gate and a second gate on the active region; The source region of the set transistor is implanted into an active region of one side of the first gate that is not adjacent to the second gate by implanting a first conductive LDD ion having a first concentration into the active regions of both the first and second gates. Forming; Forming spacers on both sidewalls of the first and second gates, respectively; The first conductive type impurity ion implantation having a second concentration higher than the first concentration is performed in the active region between the first gate and the second gate and the active region on one side of the second gate that is not adjacent to the first gate. Forming a drain region shared by the set transistor and the reset transistor and a source region of the reset transistor; Forming an interlayer insulating film on an entire surface including a source region and a drain region of the first, second gate, set transistor, and reset transistor; And And forming metal wirings on the interlayer insulating layer, the metal wires being in contact with the source region of the set transistor, the source region of the reset transistor, and the drain region, respectively. Claim 7 was abandoned upon payment of a set-up fee. 7. The method of claim 6, further comprising performing halo ion implantation outside the LDD regions below the first and second gates after forming the LDD region and before forming the spacer. The method of manufacturing a phase change memory device, characterized in that it further comprises. Claim 8 was abandoned when the registration fee was paid. 7. The method of claim 6, wherein the first conductivity type is n-type. delete

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