KR101093625B1 - Non-volatile memory and virtual negative read operatin method of the same - Google Patents

Abstract

PURPOSE: A non-volatile memory and a virtual negative read operation method of the same are provided to prevent a malfunction due to noise by determining whether a sensing node discharge unit is operated or not according to the voltage level of a sensing node. CONSTITUTION: In a non-volatile memory and a virtual negative read operation method of the same, a plurality of memory cells are serially connected to a cell string(200). A bit line(BL) is connected to the cell string. A connection part(210) electrically interlinks the bit line and the sensing node. A page buffer(220) senses the voltage of the sensing node. A discharge unit(230) discharges the voltage of the sensing node before sensing the voltage of the sensing node in a pager buffer. The discharge unit discharges the voltage of the sensing node.

Description

Non-Volatile Memory and Virtual Negative Read Operation {NON-VOLATILE MEMORY AND VIRTUAL NEGATIVE READ OPERATIN METHOD OF THE SAME}

The present invention relates to a nonvolatile memory and its virtual negative read operation method.

The memory device is divided into a volatile memory device and a nonvolatile memory device according to whether data is maintained when the power supply is cut off. Volatile memory devices are memory devices in which data is destroyed when a power supply is cut off, and DRAM and SRAM are examples thereof. A nonvolatile memory device is a memory device in which stored data is retained even when a power supply is cut off, and a flash belongs to the nonvolatile memory device.

The nonvolatile memory determines a data value according to a threshold voltage of a memory cell composed of a transistor including a floating gate. If the voltage used to determine the data of a memory cell is a negative voltage (ie, the memory cell is programmed with a negative voltage), read and verify operations should be performed using the negative voltage as a reference, but the negative voltage is non- The use of negative voltages generates a great deal of current because they must be made and used in-house in volatile memory chips. Therefore, a virtual negative read operation is used, which makes it possible to read data of a memory cell programmed with a negative voltage without using a negative voltage.

FIG. 1 is a block diagram of a conventional nonvolatile memory. Referring to FIG. 1, a conventional virtual negative read operation will be described.

As shown in FIG. 1, the nonvolatile memory includes a cell string 100, a precharge unit 101, a bit line BL, a connection unit 110, a page buffer 120, and a discharge unit 130. Include.

In the virtual negative read operation, the bit line BL is first precharged. In the precharge operation, the precharge unit 101 is turned on to make the voltage of the sensing node SO at a high level, and the connection unit 110 is turned on. The voltage of the sensing node SO is transferred to the bit line BL. The precharge level of the bit line BL in the virtual negative read operation is (the precharge voltage in the normal read operation) + VNR (absolute value of the virtual negative read bias). As described above, the application of the precharge voltage higher than the normal read operation may be performed by controlling the voltage PBSENSE applied to the connection unit 110 to V1 + VNR. Here, V1 is the level of the voltage applied to the connection unit 110 to precharge the bit line BL during the normal read operation.

After the precharge of the bit line BL, a VCC + VNR voltage is applied to the drain select line DSL and the source select line SSL of the cell string 100, and unselected word lines UNSEL WL are read. VPASS + VNR is applied to word lines that are not targets. VNR is applied to the source line SL, and 0V is applied to the selected word line SEL WL. That is, in the virtual negative read operation, a voltage higher than VNR is applied to all lines other than the selected word line SEL WL, so that a voltage of -VNR is applied to the relatively selected word line SEL WL. Cause the same effect as After the voltages are applied to the cell string 100, the voltage level of the bit line is maintained or decreased according to data stored in the memory cell corresponding to the selected word line SEL_WL.

Afterwards, the connection unit 110 is turned on so that charge sharing occurs between the bit line BL and the sensing node SO. When the connection unit 110 is turned on, the voltage PBSENSE level applied to the connection unit is controlled by V2 + VNR. Here, V2 is a voltage level applied to the connection unit 110 to transfer the voltage level of the bit line BL to the sensing node SO during the normal read operation.

Now, the voltage level of the sensing node SO should be sensed through the page buffer 120. In the virtual negative read operation, the sensing node SO may be used regardless of the data of the memory cell corresponding to the selected bit line BL. Has a high voltage level. This is because, in the virtual negative read operation, all voltages other than the voltage applied to the selected word line SEL WL have the level of the existing voltage + VNR. Therefore, before the page buffer 120 senses the voltage level of the sensing node SO, an operation of lowering the voltage level of the sensing node SO is required. The operation of lowering the voltage level of the sensing node SO is performed by the discharge unit 130. The discharge unit 130 is composed of a capacitor (capacitor using the gate cap of the transistor), the power supply voltage (VCC) is applied to the KICK terminal of the discharge unit 130, the ground voltage is applied, as a result The voltage level of the node SO drops.

When the voltage level of the sensing node SO drops to the same level as in the normal read operation, the power supply voltage VCC is applied to the SET terminal of the page buffer 120, and as a result, the page according to the voltage level of the sensing node SO is applied. Data is stored in the latch 121 of the buffer 120.

According to the above-described prior art, the capacitor 130 is used to drop the voltage of the sensing node SO before the sensing operation of the page buffer 120 in the virtual negative read operation. However, when the voltage of the sensing node SO is dropped by using the capacitor 130, the coupling ratio is changed according to the voltage level of the sensing node SO, thereby causing a difference in the amount of voltage drop. As a result, there is a problem of causing a large amount of sensing noise.

The present invention has been proposed to solve the above-mentioned problems of the prior art, and is intended to remove sensing noise generated in a process of dropping a voltage of a sensing node during a virtual negative read operation.

In order to achieve the above object, a nonvolatile memory according to an embodiment of the present invention, the cell string is a plurality of memory cells connected in series; A bit line coupled to the cell string; A connection unit for electrically connecting the bit line and the sensing node; A page buffer for sensing the voltage of the sensing node; And a discharge unit configured to discharge the voltage of the sensing node in response to a voltage level of the sensing node before the sensing node voltage sensing operation of the page buffer.

The discharge unit may be activated during a virtual negative operation.

The discharge unit discharges the sensing node to a logic 'low' level when the voltage of the sensing node is high, and maintains the sensing node at a logic 'high' level when the voltage of the sensing node is low. Can be.

In addition, the virtual negative read operation method of the nonvolatile memory according to an embodiment of the present invention, the bit line connected to the cell string is precharged with a virtual negative read precharge voltage; Applying a virtual negative bias to the cellstring; Charge sharing of the cell string and the sensing node; Discharging the sensing node in response to the voltage of the sensing node; And sensing the voltage of the sensing node.

The discharging may include discharging the sensing node to a logic 'low' level when the voltage of the sensing node is high, and maintaining the sensing node at a logic 'high' level when the voltage of the sensing node is low. have.

According to the present invention, whether the discharge operation of the sensing node discharge unit is determined according to the voltage level of the sensing node.

Therefore, a malfunction due to noise or the like is prevented in the process of dropping the voltage of the sensing node before sensing the voltage of the sensing node.

1 is a block diagram of a conventional nonvolatile memory.
2 is a block diagram of an embodiment of a nonvolatile memory according to the present invention;

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

2 is a configuration diagram of an embodiment of a nonvolatile memory according to the present invention.

As shown in FIG. 2, the nonvolatile memory includes: a cell string 200 in which a plurality of memory cells are connected in series; A bit line BL connected to the cell string 200; A connection unit 210 for electrically connecting the bit line BL and the sensing node SO; A precharge unit 201 for increasing the voltage of the sensing node during the precharge operation; A page buffer 220 for sensing a voltage of the sensing node SO; And a discharge unit 230 for discharging the voltage of the sensing node SO in response to the voltage level of the sensing node SO before the sensing operation of the sensing voltage of the page buffer 220.

The latch 221 of the page buffer 220 is configured to store data sensed by the sensing node SO, and a transistor to which the MTRAN_N signal is applied and a transistor to which the MTRAN signal is applied sense the data stored in the latch 221. It is a transistor for transferring to a node SO or another page buffer (not shown). In addition, the transistor receiving the RST signal and the transistor receiving the SET signal are configured to transfer data to the latch 221 according to the voltage of the sensing node SO.

The discharge unit 230 is activated before the sensing operation of the page buffer 220 in the virtual negative read operation, and discharges the voltage of the sensing node SO in response to the voltage of the sensing node SO. The discharge unit 230 may include a first transistor 231 transferring a voltage of the sensing node SO to the first node A in response to the discharge activation signal SOTRAN; A second transistor 232 that pulls up the second node B in response to a voltage of the first node A; A third transistor 234 that pulls down the sensing node SO in response to the voltage of the second node B; A capacitor 233 connected to the second node B; A fourth transistor 235 for adjusting an amount of current transferred from the sensing node SO to the third transistor 234 in response to the bias voltage TTRAN; And a fifth transistor 236 for initializing the voltage level of the second node B in response to the TSET signal.

Now, each step will be divided into a virtual negative read operation according to the present invention.

(1) Bit line BL precharge operation

First, the precharge signal PRE is activated and the precharge unit 201 is turned on to precharge the bit line BL. Then, the voltage level of the sensing node SO becomes the level of the power supply voltage VCC. Thereafter, a voltage of V1 + VNR is applied to the gate PBSENSE of the transistor constituting the connection unit 210 to transfer the voltage of the sensing node SO to the bit line BL, and as a result, the bit line BL is closed. Precharged. Here, V1 is a level of a voltage applied to the connection unit 210 to precharge the bit line BL during the normal read operation, and VNR is an absolute value of the virtual negative read bias. Since the voltage of V1 + VNR is applied to the gate PBSENSE of the transistor constituting the connection unit 210, the bit line BL is precharged to (precharge level during normal read operation) + VNR. In general, the bit line BL is precharged to a level of about 1.3 V during the normal read operation. If VNR is 1 V, the bit line BL is precharged to a level of 2.3 V during the virtual negative read operation. .

(2) Apply Virtual Negative Bias to Cellstring 200

After the bit line BL is precharged, various virtual negative biases are applied to the transistors of the cell string 200. A voltage of VCC + VNR is applied to the drain select line DSL and the source select line SSL, and a voltage of VPASS + VNR is applied to unselected word lines UNSEL WL. . VNR is applied to the source line SL, and 0V is applied to the selected word line SEL WL. That is, a voltage higher than VNR is applied to all lines other than the selected word line SEL WL during the virtual negative read operation, and a voltage of −VNR is applied to the relatively selected word line SEL WL. Cause the same effect. Where VPASS is the pass voltage and typically has a level of about 6.5V. When the above voltages are applied to the cell string 200, the voltage level of the bit line BL is maintained at the precharge level or the precharge level according to the data stored in the memory cell corresponding to the selected word line SEL WL. It cannot be maintained and descends.

(3) Charge sharing between the bit line BL and the sensing node SO

After the operation of (2), a voltage of V2 + VNR is applied to the PBSENSE terminal of the connection unit 210, and as a result, the bit line BL and the sensing node SO are electrically connected by the connection unit 210. Charge sharing is performed between the bit line BL and the sensing node SO. Here, V2 represents the level of the voltage applied to the PBSENSE terminal to transfer the voltage of the bit line BL to the sensing node SO during the normal read operation.

The sensing node SO when the memory cell corresponding to the selected word line SEL WL is turned on on the assumption that the precharge voltage level of the bit line BL is 2.3V and the VNR is 1V during the virtual negative read operation. Is approximately 1V, and when the memory cell corresponding to the selected word line SEL WL is not turned on, the voltage of the sensing node SO is approximately 2.3V.

(4) The sensing node SO discharged by the discharge unit 230

After the operation of (3), the sensing node SO has a level of about 1V or about 2.3V, all of which are logical 'high' values, and the voltage level of the sensing node SO distinguishes data. impossible. Therefore, the discharge operation of the sensing node SO by the discharge unit 230 is performed.

Operation of the discharge unit 230 is initiated by activation of the discharge activation signal SOTRAN. When the discharge activation signal SOTRAN is activated at the 'high' level (which is enough to transfer the voltage level of the sensing node to the first node A), the first transistor 231 is turned on to sense the sensing node SO. Voltage level is transferred to the first node (A). Then, the second transistor 232 is turned on in response to the voltage level of the first node A. As a result, the voltage level of the second node B is (voltage level of the SO node)-Vth (threshold of the second transistor). Voltage), and the voltage level of the second node B is maintained by the capacitor 233 for a predetermined time. In response to the voltage level of the second node B, the third transistor 234 is turned on or off and eventually charges are discharged from the sensing node SO.

When the voltage level of the sensing node SO is about 1 V (when the cell transistor corresponding to the selected word line SEL WL is turned on), the third transistor 234 is not turned on and thus the sensing node SO is turned on. Although the voltage level of the signal is maintained as it is, when the voltage level of the sensing node (SO) is a level of about 2.3V (when the cell transistor corresponding to the selected word line (SEL WL) is turned off), the third transistor 234 is When turned on, the voltage level of the sensing node SO drops to a low level. The fourth transistor 234 to which the bias voltage TTRAN is applied serves to adjust the amount of current discharged from the sensing node SO by the third transistor 234 in response to the bias voltage TTRAN.

As a result, when the cell transistor corresponding to the selected word line SEL WL is turned on (when the voltage level of the sensing node is relatively low), the discharge unit 230 does not operate and thus the logic level of the sensing node SO. Is kept high, but when the cell transistor corresponding to the selected word line SEL WL is turned off (when the voltage level of the sensing node is relatively high), the discharge unit 230 operates to sense the sensing node SO. ) 'S level is reduced to' low '. That is, the discharge unit 230 may be regarded as an amplifier for amplifying the voltage level of the sensing node SO in reverse.

(5) Sensing the sensing node (SO) voltage of the page buffer 220

After operation (4), the page buffer 220 detects the voltage level of the sensing node SO. The power supply voltage VCC is applied to the RST terminal of the page buffer 220 to turn on the transistor connected to the RST terminal, and the transistor 222 is turned on / off according to the voltage level of the sensing node SO. Therefore, data loaded on the latch 221 is determined according to the logic level of the sensing node SO. Conventionally (see FIG. 1), when the page buffer 120 senses the voltage of the sensing node SO, the power supply voltage VCC is applied to the SET terminal. However, in the present invention, the page buffer 220 is the sensing node SO. The power supply voltage VCC is applied to the RST terminal when the voltage level is detected, because the voltage level of the sensing node SO is amplified by the operation of the discharge unit 230.

As described above, the present invention does not discharge the voltage level of the sensing node SO using a capacitor, and determines whether or not to discharge the voltage level of the sensing node SO according to the voltage level of the sensing node SO. do. Therefore, it is possible to prevent the sensing noise and the malfunction caused by the conventional process of discharging the voltage level of the sensing node SO.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

In particular, it should be understood that the read operation in the present invention should be interpreted to include not only a read operation by a read command but also a verify operation (which is the same operation as a read) performed during the program process.

200: cell string 201: precharge part
210: connection portion 220: page buffer
230: discharge unit

Claims (10)

A cell string in which a plurality of memory cells are connected in series;
A bit line coupled to the cell string;
A connection unit for electrically connecting the bit line and the sensing node;
A page buffer for sensing the voltage of the sensing node; And
The discharge unit discharges the voltage of the sensing node in response to the voltage level of the sensing node before the voltage sensing operation of the sensing node of the page buffer.
Non-volatile memory comprising a.
Claim 2 has been abandoned due to the setting registration fee. The method of claim 1,
The discharge unit
Is activated during virtual negative lead operation.
Nonvolatile Memory.
Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1,
The discharge unit
When the voltage of the sensing node is high, the sensing node is discharged to a logic 'low' level,
If the voltage of the sensing node is low to maintain the sensing node at a logic 'high' level
Nonvolatile Memory.
Claim 4 was abandoned when the registration fee was paid. The method of claim 1,
The discharge unit
A first transistor transferring a voltage of the sensing node to a first node in response to a discharge activation signal;
A second transistor configured to pull-up a second node in response to the voltage of the first node; And
A third transistor configured to pull-down the sensing node in response to the voltage of the second node;
Nonvolatile Memory.
Claim 5 was abandoned upon payment of a set-up fee. The method of claim 4, wherein
The discharge unit
Further comprising a capacitor connected to the second node
Nonvolatile Memory.
Claim 6 was abandoned when the registration fee was paid. 6. The method of claim 5,
The discharge unit
And a fourth transistor for adjusting an amount of current transferred from the sensing node to the third transistor in response to a bias voltage.
Nonvolatile Memory.
A bit line connected to the cell string is precharged with a virtual negative lead precharge voltage;
Applying a virtual negative bias to the cellstring;
Charge sharing of the cell string and the sensing node;
Discharging the sensing node in response to the voltage of the sensing node; And
Sensing the voltage of the sensing node
Virtual negative read operation method of the nonvolatile memory comprising a.
Claim 8 was abandoned when the registration fee was paid. The method of claim 7, wherein
The discharged step
When the voltage of the sensing node is high, the sensing node is discharged to a logic 'low' level,
If the voltage of the sensing node is low to maintain the sensing node at a logic 'high' level
Virtual negative read operation of nonvolatile memory.
Claim 9 was abandoned upon payment of a set-up fee. The method of claim 7, wherein
The virtual negative lead precharge voltage is
Normal precharge voltage + (absolute value of negative voltage)
Virtual negative read operation of nonvolatile memory.
Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 9,
In the step of applying a virtual negative bias to the cell string
Supply voltage + (absolute value of negative voltage) is applied to the drain select line and the source select line,
Normal pass voltage + (absolute value of negative voltage) is applied to unselected word lines.
Ground voltage is applied to the selected word line.
Virtual negative read operation of nonvolatile memory.

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