KR101093280B1 - Audio processing circuit, audio processing apparatus, and audio processing method - Google Patents

Abstract

The voice processing circuit includes a frequency division circuit for dividing an input signal into a plurality of frequency bands to generate a plurality of first voice signals, and performing a non-linear process on the plurality of first voice signals to generate a plurality of second voice signals. And a plurality of compression circuits, and an addition circuit which adds a plurality of second audio signals to generate an output signal. Each compression circuit multiplies a gain, which is determined based on a predetermined coefficient, with the first audio signal to generate a second audio signal. Thereby, the frequency characteristic of the speaker which converts an output signal into an audio | voice can be correct | amended. In addition, it is possible to suppress distortion without deteriorating the S / N ratio without using a high performance circuit, thereby generating an audio signal excellent in auditory sound.

Audio processing unit, audio processing circuit, speaker, level detector, gain calculator

Description

AUDIO PROCESSING CIRCUIT, AUDIO PROCESSING APPARATUS, AND AUDIO PROCESSING METHOD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a speech processing circuit, a speech processing apparatus, and a speech processing method in which auditory sound is improved by gain adjustment in an audio frequency band of a speech signal.

This invention claims priority based on Japanese Patent Application No. 2008-278923 (application date: October 29, 2008), and uses the content here.

In recent years, with the development of mobile communication devices such as mobile phones, various voice processing technologies have been developed and disclosed in various documents such as Patent Document 1.

Patent Document 1: Japanese Patent No. 375156

In the cellular phone disclosed in Patent Document 1, in order to reproduce an incoming melody composed of a plurality of parts with an optimum volume balance, the frequency characteristics of the sound signal are adjusted by an equalizer to flatten the frequency characteristics of the speaker (or receiver). Doing.

Generally, the frequency characteristics are planarized by increasing the gain with respect to the level reduction portion in the frequency characteristics of the speaker. When a high level audio signal is input to the equalizer, the equalizer or a subsequent circuit needs to employ a high performance circuit to process the high level input audio signal. On the other hand, when the low level audio signal is input to the equalizer, the S / N ratio of the audio reproduction is lowered. For this reason, it was difficult to apply the voice processing technology of patent document 1 to a mobile telephone.

An object of the present invention is to provide a speech processing circuit, a speech processing apparatus, and a speech processing method in which auditory speech is improved without employing a high performance circuit.

The speech processing circuit according to the present invention includes a frequency division circuit for dividing an input signal into a plurality of frequency bands to generate a plurality of first audio signals, and performing a nonlinear process on the plurality of first audio signals to perform a plurality of second audio signals. A plurality of compression circuits for generating an audio signal and an addition circuit for adding an output of a plurality of second audio signals are provided. Each compression circuit multiplies a gain, which is determined based on a predetermined coefficient, with the first audio signal to generate a second audio signal.

In the audio processing circuit described above, nonlinear processing is performed to increase the gain for the low level input signal and to reduce the gain for the high level input signal. In addition, since it is possible to specify predetermined coefficients from the outside so as to correct frequency characteristics of a speaker or the like which converts an output signal into speech, it is possible to generate speech output excellent in auditory sound. In addition, since the second audio signal is generated by multiplying the first audio signal by a gain determined based on the first audio signal level and a predetermined coefficient, a gain multiplication is performed to correct the frequency characteristic of the audio signal after the nonlinear processing. Compared with the comparative example (refer FIG. 4) performed, in this invention, distortion can be suppressed without degrading the S / N ratio of an output signal.

Each compression circuit includes a level detector that detects a level of the first audio signal, a coefficient unit that multiplies a predetermined coefficient by the detection level, a gain determiner that determines a gain based on the multiplication result, and a first audio signal. And a multiplier configured to multiply the gain determined by the signal to generate a second voice signal. Each compression circuit further includes a storage unit for rewriting the predetermined coefficients rewritably.

The speech processing apparatus according to the present invention includes the above-described speech processing circuit and a speaker for converting the output signal into speech, and predetermined coefficients are set to correct frequency characteristics of the speaker.

In the voice processing method according to the present invention, a plurality of first voice signals are generated by dividing an input signal into a plurality of frequency bands, and non-linear processing is performed on the plurality of first voice signals to generate a plurality of second voice signals. The second audio signal is added to generate an output signal. In the nonlinear processing, a second audio signal is generated by multiplying the first audio signal by a gain determined based on the level of the first audio signal and a predetermined coefficient.

According to the present invention, it is possible to provide a speech processing circuit, a speech processing apparatus, and a speech processing method in which auditory speech is improved without employing a high performance circuit.

The present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing the configuration of the speech processing apparatus 100 according to the present embodiment. The speech processing apparatus 100 is composed of a speech processing circuit 1 and a speaker 2. The speech processing circuit 1 performs a predetermined speech processing on the input signal IN which is a speech signal to generate an output signal OUT. The speaker 2 converts the output signal OUT into audio and outputs it (soundproof). The voice processing apparatus 100 is incorporated in, for example, a mobile phone, and the input signal IN is a voice signal of a user of the other mobile phone with which communication is being performed. By the audio processing of the audio processing circuit 1, the speaker 2 outputs the audio with the improved audio.

The audio processing circuit 1 includes a frequency division circuit 10, a compression circuit unit 20, and an addition circuit 30. The frequency division circuit 10 divides the input signal IN into a plurality of frequency bands to generate a plurality of first audio signals. The compression circuit unit 20 performs a dynamic range compression on each of the plurality of first speech signals to generate a plurality of second speech signals. The addition circuit 30 adds a plurality of second audio signals to generate an output signal OUT.

The frequency division circuit 10 includes a plurality of band pass filters BPF1 to BPF6. In the present embodiment, six BPP1 to BPF6 are provided in the frequency division circuit 10. However, the present invention is not limited thereto, and an arbitrary number of band pass filters may be provided. Input signals IN are supplied to BPF1 to BPF6, respectively, and pass signals of a predetermined frequency band based on the center frequency set in each bandpass filter to generate a first audio signal. The frequency band of each band pass filter is narrower than the frequency band of the input signal IN. BPF1 to BPF6 have different center frequencies and are preferably set at logarithmic intervals from the viewpoint of outputting voices having improved auditory sound over the speaker 2. In this embodiment, BPF1: 125 Hz, BPF2: 250 Hz, BPF3: 500 Hz, BPF4: 1 kHz, BPF5: 2 kHz, and BPF6: 4 kHz are set as the center frequency.

The compression circuit unit 20 includes the first compression circuit U1 to the sixth compression circuit U6. The first compression circuit U1 to the sixth compression circuit U6 are connected corresponding to the BPF1 to BPF6, respectively. In the present embodiment, six compression circuits are provided in the compression circuit unit 20 corresponding to six band pass filters, but the present invention is not limited thereto, and any number of compression circuits may be applied to any number of band pass filters. You may provide it correspondingly. Each compression circuit performs the nonlinear processing and the correction processing described later on the first audio signal to generate a second audio signal. In addition, you may refer to these compression circuits generically as a nonlinear processing circuit.

The speaker 2 has the frequency characteristic peculiar to the speaker. In this embodiment, in order to improve the audible sound of speech reproduction by the speaker 2, a predetermined frequency characteristic is given to the output signal OUT in consideration of the frequency characteristic inherent to the speaker 2. For this reason, each compression circuit performs a correction process using the control signal CTL supplied from the outside of the audio processing circuit 1. The control signal CTL is appropriately determined according to the frequency characteristic to be given to the output signal OUT. In this embodiment, the control signal CTL designates a coefficient corresponding to the natural frequency characteristic of the speaker 2, and adjusts the signal level supplied to the gain calculator 52 in each compression circuit (see Fig. 2). . The gain calculator 52 calculates gain in accordance with the supplied signal level, so that the frequency characteristic according to the coefficient is given to the output signal OUT. That is, in this embodiment, the coefficient is set to correct the frequency characteristic of the speaker 2 in accordance with the output signal OUT. The coefficients used for this correction process are specified outside of the audio processing circuit 1, but the supply source of the control signal CTL may be provided outside or inside the audio processing apparatus 100.

Next, the structure of each compression circuit is demonstrated with reference to FIG. Since the first compression circuit U1 to the sixth compression circuit U6 each have the same configuration, the configuration of the first compression circuit U1 will be described here.

As shown in FIG. 2, the first compression circuit U1 includes a level detector 50, a counter 51, a gain calculator (or a gain determiner) 52, and a multiplier 53. do. The level detector 50 detects the level of the first voice signal generated by the BPF1. The counting unit 51 multiplies the level of the detected first audio signal by the coefficient designated by the control signal CTL. This multiplication is performed to correct the frequency characteristic of the speaker 2. A counter may be provided in the counter 51 to rewritable the counter. When the counter 51 is not provided with a storage, a storage is provided at the supply source of the control signal CTL so that the coefficient can be rewritable. The gain calculator 52 has a gain table for determining gain in accordance with the input signal. That is, the gain calculator 52 calculates a gain based on the output signal of the counter 51 and the gain table. This gain table is designed so that the relationship between an input level and an output level becomes a nonlinear characteristic as mentioned later, and is responsible for the nonlinear process in a compression circuit. The multiplier 53 multiplies the gain calculated by the gain calculator 52 with respect to the first audio signal generated by BPF1 to generate a second audio signal. In addition, since the gain is calculated to correct the frequency characteristic of the speaker 2, the correction process is completed by multiplication of the multiplier 53. FIG. In other words, the first compression circuit U1 is also responsible for the function of the correction processing circuit.

Each compression circuit has the input / output level characteristic as shown by the solid line of FIG. The gain table described above is set to obtain this input / output level characteristic. In Fig. 3, the horizontal axis represents the input level (dB), and the vertical axis represents the output level (dB). The symbol "UCL" represents an auditory discomfort level, which corresponds to an upper limit of a sound pressure range that does not give an auditory discomfort to a human being. The UCL value can be set arbitrarily, but it is preferable to set it by a statistical method. As shown in the input / output level characteristic of Fig. 3, each compression circuit restricts the output level and fixes it to the UCL value when the input level is equal to or greater than the UCL value. Thereby, the second voice signal is limited to sound pressure which does not give an auditory discomfort to a human.

In FIG. 3, the code | symbol "HTL" represents an auditory threshold value, and this corresponds to the lower limit of the sound pressure range which a human can hear. Although the HTL value can be set arbitrarily, it is preferable to set it by a statistical method. Further, the sign "HTL_high" represents a level higher by a predetermined difference (dB) than the HTL value, and is set in the range of HTL_high <UCL. In FIG. 3, the broken line is a straight line connecting the input level / output level (UCL, UCL) point and the origin, and shows linear input / output level characteristics. As apparent from comparison with the linear input / output level characteristic shown by the broken line in FIG. 3, the input / output level characteristic of each compression circuit represented by the solid line is nonlinear.

According to the input / output level characteristic of each compression circuit, the first audio signal level (i.e., input level) from the HTL value to the UCL value is compressed to the second audio signal level from the HTL_high value to the UCL value. Even the listener having the HTL_high value can sufficiently hear the first audio signal from the HTL value or more to the HTL_high value.

In the process of correcting the frequency characteristic of the speaker 2, it is necessary to increase the gain in the low level region of the frequency characteristic or decrease the gain in the high level region. The gain is determined by the gain calculator 52 at the rear end of the counter 51 shown in FIG. The gain calculating unit 52 performs compression amplification to increase gain as the input level is lower, and the counting unit 51 multiplies the coefficient by the first audio signal level detected by the level detecting unit 50, whereby The level which increased or decreased one audio signal level by the increment in the speaker 2 is calculated. That is, when the level is attenuated in the speaker 2, the input level of the gain calculating part 52 shifts to the left direction in FIG. 3 by the coefficient multiplication of the counting part 51. On the other hand, when amplifying the level in the speaker 2, the input level of the gain calculator 52 is shifted in the right direction in FIG.

As described above, each compression circuit has a nonlinear input / output level characteristic, but here, the nonlinear process and the correction process are performed simultaneously. Thereby, the overflow in the addition circuit 30 can be prevented and the S / N ratio of the output signal OUT can be improved. 4 shows a configuration of an audio processing apparatus 200 that performs correction processing after nonlinear processing. The feature and advantages of the speech processing apparatus 100 according to the present embodiment will be described using this speech processing apparatus 200 as a comparative example.

The speech processing apparatus 200 shown in FIG. 4 is constituted by the speech processing circuit 3 and the speaker 2. The audio processing circuit 3 includes a frequency division circuit 10, a compression circuit unit 40, gain multipliers G1 to G6, and an addition circuit 30. The compression circuit unit 40 includes a plurality of compression circuits (that is, eleventh compression circuits U11 to 16th compression circuits U16), which are respectively included in the BPF1 to BPF6 included in the frequency division circuit 10. It is connected correspondingly. Each of the eleventh compression circuits U11 to 16th compression circuits U16 has a configuration in which the counter 51 is removed from the configuration shown in FIG. 2, and is generated by the corresponding band pass filter BPF. Nonlinear processing is performed on the audio signal to generate a third audio signal.

The gain multiplier G1 to the gain multiplier G6 are configured by, for example, an equalizer, and are connected to correspond to the eleventh compression circuits U11 to 16th compression circuit U16. The above-mentioned control signal CTL is supplied to the gain multiplier G1 to the gain multiplier G6. Each gain multiplier generates a second voice signal by multiplying a third voice signal generated by a corresponding compression circuit by a coefficient designated by the control signal CTL. The coefficient multiplication by the gain multiplier G1 to the gain multiplier G6 is performed to correct the frequency characteristic of the speaker 2, specifically, to cancel the level increment in the speaker 2. In this way, the audio processing device 200 executes the correction process using the gain multiplier G1 to the gain multiplier G6. The addition circuit 30 adds the plurality of second audio signals generated by the gain multiplier G1 to the gain multiplier G6 to generate an output signal OUT.

Frequency [Hz] Frequency characteristic [dB] 125 -10 250 -5 500 0 1000 -5 2000 -7 4000 -10

Table 1 shows an example of the frequency characteristics of the speaker 2, and when performing the correction process, the gain multiplier G1 is + 10dB, the gain multiplier G2 is + 5dB, the gain multiplier G3 is 0dB, the gain multiplication. The part G4 amplifies the third voice signal by +5 dB, the gain multiplier G5 is +7 dB, and the gain multiplier G6 is +10 dB. In this way, the audio processing circuit 3 amplifies the audio signal in each frequency band by the level attenuation of the speaker 2. This suppresses (removes) the influence of the frequency characteristic peculiar to the speaker 2 in the sound actually soundproofed from the speaker 2.

However, depending on the frequency characteristics of the speaker 2 of the audio processing device 200, there is a fear that the output level of the gain multiplier G1 to the gain multiplier G6 becomes too high. In addition, when the addition circuit 30 is comprised with an analog circuit, when the output level of a gain multiplication part becomes high too much, the output signal OUT will be clipped. When the adder circuit 30 is constituted by a digital circuit, if the output level of the gain multiplier becomes too high, it overflows and the output signal OUT is clipped like the analog circuit. As a result, distortion occurs in the output signal OUT, and sound quality deteriorates. Moreover, even if the output level of the gain multiplication part is in the dynamic range of the adder circuit 30, the distortion resulting from the frequency characteristic of the speaker 2 of a rear stage may generate | occur | produce.

The above problem can be solved by lowering the third audio signal level input to each gain multiplier, but lowering the third audio signal level lowers the S / N ratio of the output signal OUT. This phenomenon becomes a problem when the input signal IN has a small amplitude. This problem also occurs similarly regardless of whether the compression circuit is an analog circuit or a digital circuit. When the compression circuit is composed of an analog circuit, the noise level compared to the input signal level (for example, the thermal noise of the transistor or the level of the noise drawn from the power supply) becomes a problem. When the compression circuit is composed of a digital circuit, a slight rounding error of the digital voice data becomes a problem.

In comparison with the speech processing apparatus 200 as a comparative example, the speech processing apparatus 100 according to the present embodiment performs the nonlinear processing and the correction processing in the compression circuit. Specifically, the gain calculator 52 corrects the first audio signal level detected by the level detector 50 by the counting unit 51, and gives gain to the first audio signal based on the corrected level. The multiplication unit 53 multiplies the gain calculated by the first audio signal to generate a second audio signal. The gain calculator 52 determines the gain in accordance with the nonlinear input and output level characteristics shown in FIG. 3. That is, the dynamic range is compressed by reducing the gain for the portion having the high first audio signal level. Thereby, even if the correction process is performed in the compression circuit, it is possible to suppress the overflow in the addition circuit 30. In particular, since the second audio signal level is suppressed so as not to exceed the UCL value in the input / output characteristics shown in FIG. 3, the maximum level of the second audio signal output from the first compression circuit U1 to the sixth compression circuit U6. Will be confirmed. For this reason, by setting the dynamic range of the addition circuit 30 in consideration of the maximum level, generation | occurrence | production of the distortion by the clipping of the output signal OUT can be reliably prevented. In addition, even if the input signal IN has a small amplitude, the present embodiment does not need to attenuate the level further, so that the S / N ratio is not lowered.

Next, the difference between the effects of the speech processing apparatus 100 and the speech processing apparatus 200 will be described with attention to the signal path corresponding to the BPF6. Here, the input / output level characteristics regarding the nonlinear processing of the sixth compression circuit U6, the input / output level characteristics of the sixteenth compression circuit U16, and the input level-gain characteristics of the gain multiplier 52 are shown in Figs. . In Fig. 5, the unit "dBSPL" is used as the decibel notation of the sound pressure level. The difference between the HTL value and the HTL_high value is 40 dB, the HTL value is -5 dB, and the UCL value is 100 dB.

Input level [dBSPL] Gain [dB] Output level [dBSPL] -10 40 30 -5 40 35 0 38.1 38.1 10 34.3 44.3 20 30.5 50.5 30 26.7 56.7 40 22.9 62.9 50 19 69 60 15.2 75.2 70 11.4 81.4 80 7.6 87.6 90 3.8 93.8 100 0 100

First, the case where the level detected by the level detection unit 50 is 60 dBSPL will be described. In the speech processing circuit 3 of the speech processing device 200 according to the comparative example, the gain calculated by the gain calculating unit 52 of the sixteenth compression circuit U16 is 15.2 dB. Therefore, the sound pressure output from the audio processing circuit 3 becomes 60 + 15.2 = 75.2 dBSPL when the frequency characteristic of the speaker 2 is flat. According to Table 1, since the gain multiplier G6 increases the gain by the attenuation fraction (10 dB) of the frequency characteristic at 4 kHz in the speaker 2, the output sound pressure of the speech processing circuit 3 is 75.2 + 10-10 = 75.2dBSLP. This indicates that the audio processing circuit 3 corrects the frequency characteristic of the speaker 2 with high accuracy.

On the other hand, the sound pressure output from the audio processing circuit 1 of the audio processing device 100 according to the present embodiment is a gain calculating unit of the sixth compression circuit U6 if the frequency characteristic of the speaker 2 is flat. The input level of 52) is 60 dBSPL, and the gain calculated by this gain calculating section 52 is 15.2 dB, which is 60 + 15.2 = 75.2 dBSPL. According to Table 1, since the counter 51 lowers the gain detected by the level detector 50 by the attenuation fraction (10 dB) of the frequency characteristic at 4 kHz in the speaker 2, the gain calculator 52 ), The input level is 60-10 = 50dBSPL, and the gain calculated by the gain calculating unit 52 is 19dB. As a result, the output sound pressure of the audio processing circuit 1 becomes 60 + 19-10 = 69dBSPL. . This indicates that the speech processing circuit 1 corrects the frequency characteristic of the speaker 2 with a certain degree of accuracy, although lower than that of the speech processing circuit 3.

Next, the case where the detection level of the level detection unit 50 is 100 dBSPL will be described. In the speech processing circuit 3 of the speech processing device 200 according to the comparative example, the gain calculated by the gain calculating unit 52 of the sixteenth compression circuit U16 is 0 dB. If the frequency characteristic of the speaker 2 is flat, the output sound pressure of the audio processing circuit 3 becomes 100 + 0 = 100dBSLP. According to Table 1, the gain multiplier G6 increases the gain by the attenuation fraction (10 dB) of the frequency characteristic at 4 kHz in the speaker 2, so that the output sound pressure of the speech processing circuit 3 is 100 + 10-10 = 100dBSLP. This indicates that the audio processing circuit 3 corrects the frequency characteristic of the speaker 2 with high accuracy, but on the other hand, the gain multiplier, the adder circuit 30, and the speaker 2 correspond to 110dBSLP. This suggests that a high performance circuit capable of handling high level signals needs to be used.

On the other hand, the output sound pressure of the audio processing circuit 1 of the audio processing device 100 according to the present embodiment is the gain calculating unit 52 of the sixth compression circuit U6 if the frequency characteristic of the speaker 2 is flat. ), The input level is 100dBSLP, and the gain of the gain calculating unit 52 is 0dB, so that 100 + 0 = 100dBSLP. According to Table 1, since the counter 51 reduces the detection level of the level detector 50 by attenuation (10 dB) of the frequency characteristic at 4 kHz in the speaker 2, the input of the gain calculator 52 Since the level becomes 100-10 = 90 dBSLP and the gain of the gain calculation unit 52 becomes 3.8 dB, the output sound pressure of the audio processing circuit 1 becomes 100 + 3.8-10 = 93.8 dBSLP. This indicates that the speech processing circuit 1 corrects the frequency characteristic of the speaker 2 with a certain degree of accuracy, although lower than that of the speech processing circuit 3. In addition, it suggests that the multiplication unit 53 and the speaker 2 can be configured using a circuit that handles a signal having a level equivalent to 103.8 dBSLP.

In addition, although the nonlinear processing performed by each compression circuit in this embodiment includes level limitation, compression amplification, and linear amplification, it is not necessary to limit this. In addition, in the present embodiment, the speaker 2 is illustrated as a means for converting the output signal OUT into voice, but the present invention is not limited to this. That is, the present invention is not limited to this embodiment, but includes various design examples that can be grasped based on the definitions of the invention according to the claims and the problem to be solved. Hereinafter, a modification of the present embodiment will be described with reference to FIG. 7.

7 is a block diagram showing the configuration of the audio processing circuit 4 according to the modification of the present embodiment. Similar to the speech processing circuit 1 according to the present embodiment, the speech processing circuit 4 according to the modification performs speech processing on the input signal IN to generate the output signal OUT. The speech processing circuit 4 executes the speech processing in the frequency domain, while the speech processing circuit 1 executes the speech processing in the time domain.

The speech processing circuit 4 includes a Fourier transform unit 60, a band selector 1 to a band selector 6, a level detector 61 to 66, a counter 71 to 76, a gain calculator 81 to 86, and a gain. An interpolation section 70, a multiplication section 80, and an inverse Fourier transform section 90 are provided. The audio processing circuit 4 includes six circuit configurations, and the band selector 1, the level detector 61, the counter 71 and the gain calculator 81 are connected in series, and the band selector 2, the level detector 62, the counter 72 and the gain calculator 82 are connected in series. The band selector 6, the level detector 66, the counter 76 and the gain calculator 86 are connected in series.

The Fourier transform unit 60 converts the input signal IN into a frequency domain signal from a time domain signal by Fourier transform (for example, fast Fourier transform). Each band selector selects and outputs a signal of a predetermined frequency band from the input signal IN after Fourier transform. In other words, each band selector calculates an input spectrum of a predetermined frequency band. That is, the Fourier transform unit 60 and the band selector 1 to the band selector 6 realize a function corresponding to the frequency division circuit 10 shown in FIG.

The level detectors 61 to 66 correspond to the level detector 50 shown in Fig. 2, respectively, and detect (calculate) the average level of the output signal of the predetermined band selection circuit. The control signals CTL1 to CTL6 are supplied to the counters 71 to 76, and multiply the detection level of the level detectors 61 to 66 by the coefficients specified by the control signals CTL1 to CTL6. Here, the counters 71 to 76 perform coefficient multiplication to correct the frequency characteristic of the speaker 2. That is, the counters 71-76 correspond to the counter 51 shown in FIG.

The gain calculators 81 to 86 correspond to the gain calculator 52 shown in Fig. 2, respectively, and calculate a gain based on the output signal of the counters 71 to 76 and a gain table (not shown). . Here, the gain calculators 81 to 86 may refer to a common gain table or a separate gain table. In this modification, the gain calculators 81 to 86 refer to separate gain tables from the viewpoint of improving the accuracy.

The gain interpolator 70 interpolates the gains calculated by the gain calculators 81 to 86 to calculate the gain for the signal in the entire frequency domain (that is, the input signal IN in the frequency domain). This "interpolation" is described below.

The gain calculators 81 to 86 calculate the gains for the specific frequency bands, respectively, and calculate only the gains for the six specific frequency components in the entire frequency range. However, the input signal IN contains frequency components other than six specific frequency components. Therefore, in the present modification, the gain for the input signal IN in the entire frequency domain is calculated by linearly interpolating the gain for the six frequency components in the input signal IN in the frequency domain.

The multiplier 80 corresponds to the multiplier 53 shown in FIG. 2, and multiplies the gain calculated by the gain interpolator 70 to the input signal IN in the frequency domain. The inverse Fourier transform unit 90 performs inverse Fourier transform on the output signal of the multiplier 80 to convert the output signal in the frequency domain into the output signal OUT in the time domain.

That is, the level detectors 61 to 66, the counters 71 to 76, the gain multipliers 81 to 86, the gain interpolator 70, the multiplier 80 in the speech processing circuit 4, and The inverse Fourier transform unit 90 corresponds to the compression circuit unit 20 of the speech processing circuit 1. In addition, in the audio processing device provided with the audio processing circuit 4 according to the present modification, the addition circuit 30 becomes unnecessary.

Finally, the present invention is not limited to the present embodiment, modifications, and the like, and includes various design examples for implementing the voice processing technique as shown in the appended claims.

1 is a block diagram showing the configuration of a speech processing apparatus according to the present embodiment.

2 is a block diagram showing the configuration of a compression circuit included in the audio processing device.

3 is a graph showing input / output level characteristics of a compression circuit.

4 is a block diagram showing the configuration of a voice processing device as a comparative example of the voice processing device shown in FIG. 1;

Fig. 5 is a graph showing the input / output level characteristics of the speech processing circuit and explaining the effectiveness of the present embodiment compared with the comparative example with respect to Tables 1 and 2;

6 is a block diagram showing a configuration of a speech processing circuit according to a modification of the present embodiment.

<Explanation of symbols for the main parts of the drawings>

1: voice processing circuit

2: speaker

10: frequency division circuit

20: compression circuit unit

30: addition circuit

Claims (8)

A frequency division circuit for dividing an input signal into a plurality of frequency bands to generate a plurality of first audio signals; A plurality of compression circuits for performing a nonlinear process on the plurality of first speech signals to generate a plurality of second speech signals; An adding circuit for adding the plurality of second voice signals to generate an output signal,  Each of the plurality of compression circuits determines a gain based on a level detector that detects a level of the first audio signal, a counter that multiplies a predetermined coefficient with the detected level, and a multiplication result of the counter. And a multiplier for multiplying the determined gain with respect to the first audio signal to generate the second audio signal. The speech processing circuit according to claim 1, wherein said coefficient is specified from the outside. delete The audio processing circuit according to claim 1, wherein each of the plurality of compression circuits includes a storage unit for rewriting the predetermined coefficients rewritably. A frequency division circuit for dividing an input signal into a plurality of frequency bands to generate a plurality of first speech signals, and a plurality of compressions for performing a non-linear process on the plurality of first speech signals to generate a plurality of second speech signals Circuitry, and an adder circuit for adding an output signal by adding the plurality of second audio signals, wherein each of the plurality of compression circuits comprises: a level detector for detecting a level of the first audio signal; A second audio signal is generated by multiplying a coefficient unit for multiplying a predetermined coefficient with respect to a level, a gain determination unit for determining a gain based on a multiplication result of the coefficient unit, and the determined gain with respect to the first audio signal A speech processing circuit having a multiplier to perform, A speaker for converting the output signal into voice; And a predetermined coefficient is set to correct frequency characteristics of the speaker. Generating a plurality of first audio signals by dividing an input signal into a plurality of frequency bands; Generating a plurality of second speech signals by performing nonlinear processing on the plurality of first speech signals; Generating an output signal by adding the plurality of second voice signals; In the nonlinear processing, a level of a first audio signal is detected for each of the plurality of first audio signals, a predetermined coefficient is multiplied with the detected level, and a gain is determined based on the multiplication result. And a process for generating a second speech signal by multiplying the determined gain with respect to the first speech signal. The speech processing circuit according to claim 1, wherein said gain determining section has a gain table designed such that a relationship between an input level and an output level is a nonlinear characteristic. The speech processing device according to claim 5, wherein the gain determining unit has a gain table designed such that a relationship between an input level and an output level is a nonlinear characteristic.

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