KR101090509B1 - Inverter and controlling method thereof - Google Patents

Abstract

An inverter and an inverter control method are disclosed. The inverter includes a plurality of switch elements, and includes a switch unit for generating a three-phase output power according to the switching operation of the plurality of switch elements, and a plurality of capacitors connected in series to have a neutral node. A capacitor unit for supplying a voltage generated by the discharge to the plurality of switch elements, and a voltage vector of the neutral node, and a space vector control unit performing space vector control on the switch unit using the estimated voltage value of the neutral node. It includes. Accordingly, a control for compensating for the unbalance of the three-phase output voltage can be easily performed by estimating this without using a separate voltage measuring device for measuring a voltage value for the neutral node.

Inverter, Space Vector, Estimated, Unbalanced, FSTPI, SVPWM

Description

Inverter and control method {INVERTER AND CONTROLLING METHOD THEREOF}

The present invention relates to an inverter and a control method of the inverter, and does not use a separate voltage measuring device for measuring a voltage value for a neutral node (sequence link voltage), and estimates this to compensate for the unbalance of the three-phase output voltage. The present invention relates to an inverter and a control method of the inverter.

Recently, the demand for high-voltage high-capacity inverter system is increasing according to the trend of large-capacity and high-pressure industrial facilities, and researches on inverters that can overcome the limited rating of power semiconductor devices have been continuously conducted.

Four-Switch Three-Phase Inverter (FSTPI) is an inverter that can output three-phase power using four switch elements. Since four-switch three-phase inverters output three-phase power using only four switching elements, they are not only economical compared to six-switch three-phase inverters (SSTPI). There is an advantage to reduce.

However, in a four-switch three-phase inverter, pulsation of the capacitor voltage occurs as current flows through the neutral node (DC link or neutral point), which causes the output voltage vector to change. When the output voltage vector changes, the output voltage is unbalanced, and there is a problem in that harmonic components of the output voltage increase. In particular, when the motor is connected to the load of the inverter, the harmonic components cause torque pulsation, and therefore, it is required to improve the output voltage waveform for precise control of the fluctuation.

Accordingly, conventionally, the output voltage waveform is improved by using a space vector plus width modulation (SVWWM) method. The space vector PWM uses four basic voltage vectors obtained from a four-switch three-phase inverter to create a switching pattern to compensate for the unbalance of the three-phase output voltage, or to control the rectifier at the input stage to control the unbalance of the DC link voltage. How to improve.

However, since the space vector PWM method uses the voltage value of the neutral node (direct link) to identify the distorted reference voltage vector, the DC link voltage value in the four-switch three-phase inverter needs to be measured. That is, conventionally provided with a separate voltage measuring device, and directly measured the voltage value of the neutral node, there was a problem that the size and manufacturing cost of the inverter increases. In addition, it does not meet the intention of using a four-switch three-phase inverter that is important to reduce costs, and a method for improving the unbalance of the three-phase output voltage is required without directly measuring the voltage of the neutral node.

Accordingly, an object of the present invention is to provide an inverter and an inverter capable of compensating for an unbalance of a three-phase output voltage without estimating a separate voltage measuring device for measuring a voltage value for a neutral node (serial link voltage). To provide a control method.

Inverter according to the present invention for achieving the above object includes a plurality of switch elements, a plurality of switch units for generating a three-phase output power in accordance with the switching operation of the plurality of switch elements, a plurality of serially connected to have a neutral node A capacitor unit for supplying a voltage generated by charging and discharging an input DC power to the plurality of switch elements, and a voltage value of the neutral node, and estimating a voltage value of the neutral node. It includes a space vector control unit for performing a space vector control for the switch unit using.

In this case, it is preferable that the space vector controller estimates the voltage value of the neutral node by integrating the real axis voltage value of the output power of one phase of the three-phase output power to before and after the voltage pulsation.

The switch unit may include a first switch group including a first switch element and a third switch element connected in series, and a second switch group including a second switch element and a fourth switch element connected in series. Preferably, a neutral node, a second node to which the first switch element and a third switch element are connected, and a third node to which the second switch element and the fourth switch element are connected, output the three-phase output power.

On the other hand, the capacitor unit, one side and one side of the input DC power is connected, the first capacitor is connected to the neutral node and the other side, and the other side and one side of the input DC power is connected It may include a second capacitor connected to the neutral node and the other side.

In this case, the space vector controller preferably estimates node voltages of the first capacitor and the second capacitor through the following equation.

는 제2 커패시터의 노드 전압값,

는 제1 커패시터의 노드 전압값, V_dc 는 직류 전압값, K는 적분기의 이득값, V_α ^* 는 전압 맥동이 없는 경우 지령 전압 벡터에 의해 얻을 수 있는 출력 전압의 실수축 전압값, V_α는 전압 맥동이 있는 경우 출력된 실제 전압의 실수축 전압값이다. here,

Is the node voltage value of the second capacitor,

Is the node voltage value of the first capacitor, V _dc is the DC voltage value, K is the gain value of the integrator, V _α ^* is the real axis voltage value of the output voltage obtained by the command voltage vector when there is no voltage pulsation, V _α Is the real axis voltage value of the actual voltage output in the case of voltage pulsation.

On the other hand, the control method of the inverter in the present embodiment, the step of calculating the switching period for each of the plurality of switch elements, the control of each of the plurality of switch elements in accordance with the calculated switching period to supply a three-phase output power supply Generating, estimating a voltage value of a neutral node to which the plurality of capacitors are interconnected; and recalculating a switching period of the plurality of switch elements by using the estimated voltage value of the neutral node. Controlling the device.

In this case, estimating the voltage of the neutral node, the voltage of the neutral node is estimated by integrating the real axis voltage value of the output power of one phase of the three-phase output power to before and after pulsation according to the current flow. It is desirable to.

On the other hand, the plurality of capacitors, one side and one side of the DC power is connected, the first capacitor is connected to the neutral node and the other side, and the other side and one side of the DC power is connected, The neutral node may include a second capacitor connected to the other side.

In this case, estimating the voltage of the neutral node, it is preferable to estimate the voltage value of the first capacitor and the second capacitor through the following equation.

는 제2 커패시터의 노드 전압,

는 제1 커패시터의 노드 저전압, V_dc 는 입력되는 직류 전압, K는 적분기의 이득값, V_α ^* 는 전압 맥동이 없는 경우 지령 전압 벡터에 의해 얻을 수 있는 출력 전압의 실수축 전압값, V_α는 전압 맥동이 있는 경우 출력된 실제 전압의 실수축 전압값이다. here,

Is the node voltage of the second capacitor,

Is the node low voltage of the first capacitor, V _dc is the input DC voltage, K is the gain value of the integrator, V _α ^* is the real axis voltage value of the output voltage obtained by the command voltage vector when there is no voltage pulsation, V _α Is the real axis voltage value of the actual voltage output in the case of voltage pulsation.

Hereinafter, exemplary embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

1 is a block diagram showing the configuration of an inverter according to an embodiment of the present invention. Referring to FIG. 1, the inverter includes a capacitor unit 110, a switch unit 120, an output unit 130, and a space vector control unit 140.

The capacitor unit 110 includes a plurality of capacitors connected in series to have a neutral node (neutral point or DC link voltage), and provides the switch unit 120 with a voltage generated by charging and discharging a DC voltage input from the outside. In detail, the capacitor unit 110 receives DC power from the outside, and the plurality of capacitors may alternately perform charging and discharging. The charging and discharging operation is changed according to the switching state of the switch unit 120. A detailed configuration and operation of the capacitor unit 110 will be described later with reference to FIGS. 2 to 5.

The switch unit 120 includes a plurality of switch elements, and generates a three-phase voltage according to a switching operation of the plurality of switch elements. Specifically, the switch unit 120 includes a first switch group including a first switch element 121 and a third switch element 123 connected in series, a second switch element 122 and a fourth switch element 124 connected in series. It may be implemented as a second switch group consisting of. The detailed configuration and operation of the switch unit 120 will be described later with reference to FIGS. 2 to 5.

The output unit 130 outputs the three-phase power generated by the switch unit 120. Specifically, the output unit 130 is the output power Va for the neutral node of the capacitor unit 110 as phase a, and the phase where the node where the first switch element 121 and the third switch element 123 meet is b-phase. The three-phase power can be output by using the node where the second switch element 122 and the fourth switch element 124 meet as the output power supply Vc for the c-phase.

FIG. 2 is a circuit block diagram specifically illustrating the configuration of the capacitor unit 110 and the switch unit 120 of FIG. 1.

Referring to FIG. 2, the capacitor unit 110 includes two capacitors 111 and 112, and the two capacitors 111 and 112 are connected in series. Specifically, one side of the first capacitor 111 is connected to one side of the DC power supply, the other side is connected to the second capacitor 112. In addition, one side of the second capacitor 112 is connected to the other side (not connected to the first capacitor) of the DC power supply, and the other side is connected to the first capacitor 111. The node (neutral node or neutral point) where the first capacitor 111 and the second capacitor 112 meet is a node that outputs the output power Va for the A phase. In the present embodiment, the capacitor unit 110 is implemented using two capacitors, but the capacitor unit 110 may be implemented using three or more capacitors. For example, the capacitor unit 110 may be implemented by connecting four capacitors having the same capacitance in parallel, and connecting the capacitors connected in series.

The switch unit 120 includes four switch elements, the first switch element 121 connected in series, the third switch element 123 forming a first switch group, the second switch element 122 connected in series, and the first switch element. Four switch elements 124 form a second switch group. Here, the intermediate node of the first switch group and the second switch group has an output terminal, and the intermediate node of the first switch group, that is, the node where the first switch element 121 and the third switch element 123 meet is B A node for outputting the output power Vb for the phase, and an intermediate node of the second switch group, that is, a node where the second switch element 122 and the fourth switch element 124 meet is an output power source for the C phase ( This node outputs Vc). In the implementation, the role of the intermediate node of the first switch group and the intermediate node of the second switch group may be implemented in a form that is mutually changed.

On the other hand, the two switch elements in each switch group operate alternately. For example, when the first switch element 121 is turned on, the third switch element 123 has an off state, and when the first switch element 121 is turned off, the third switch element 123 is turned on. Has a status.

Accordingly, the output power of the inverter 100 is determined according to the states of the first switch element 121 and the second switch element 122. Specifically, the number of four cases occurs according to the operating states of the two switch elements 121 and 122. For example, when the first switch element 121 and the second switch element 122 are turned off, and the third switch element 123 and the fourth switch element 124 are turned on, the second capacitor 112 may be used. The voltage V _C2 charged to is outputted, and the voltage V _C1 charged to the first capacitor 111 is not outputted.

Then, when the first switch element 121 and the second switch element 122 are turned on and the third switch element 123 and the fourth switch element 124 are turned off, the first capacitor 111 is charged. The voltage V _{C1 that} has been set is output, and the voltage V _C2 that is charged in the second capacitor 112 is not output. The first capacitor 111 and the first switch element 121 and the fourth switch element 124 are turned on and the second switch element 122 and the third switch element 123 are turned off. The voltages V _C1 and V _C2 charged in the two capacitors 112 are all output, the second switch element 121 and the third switch element 124 are turned on, and the first switch element 122 and Even when the fourth switch element 123 is turned off, all of the voltages V _C1 and V _C2 charged in the first capacitor 111 and the second capacitor 112 are output.

The output voltage for each phase according to such a switch state is as follows.

Here, S ₁ represents a switch state of the first switch element 121, and S ₂ represents a switching state of the second switch element 122. For example, when S ₁ has a value of '1', the first switch element 121 is in an on state, and when S ₁ has a value of '0', the first switch element 121 is in an off state. to be.

In addition, since two switches in one switch group operate alternately with each other, when S ₁ has a value of '1', the third switch element 123 is in an off state, and S ₁ is '0'. When the value is, the third switch element 123 is in an on state.

If the value of the output voltage according to the state of S ₁ and S ₂ is converted into a fixed coordinate system, it is shown in Table 1.

S ₁ S ₂ vector Vα Vβ 0 0 V1 '

0 One 0 V2 '

One One V3 '

0 0 One V4 '

V _α is a voltage value corresponding to the real component Re in the fixed coordinate system value, and V _β is a voltage value corresponding to the imaginary component Im in the fixed coordinate system.

FIG. 3 illustrates the voltage vectors of Table 1 according to the voltage V _C1 of the first capacitor 111 and the voltage V _C2 of the second capacitor 112.

Referring to FIG. 3A, when the voltage V _C1 of the first capacitor 111 and the voltage V _C2 of the second capacitor 122 have the same magnitude, it can be seen that each voltage vector is orthogonal to each other. have. By combining the four reference voltage vectors thus obtained, the inverter 110 can obtain a three-phase balanced voltage having a phase of 120 degrees.

However, referring to FIG. 3B, when the voltage V _C1 of the first capacitor 111 is smaller than the voltage V _C2 of the second capacitor 112 (V _C1 <V _C2 ), the right side Will have a sloped voltage vector. 3 (c), when the voltage V _C1 of the first capacitor 111 is greater than the voltage V _C1 of the second capacitor 112 (V _C1 > V _C2 ), the left side Will have a sloped voltage vector. As such, when the voltage values of the first capacitor 111 and the second capacitor 112 are not the same, the resulting voltage vectors are not perpendicular to each other, and the inverter can generate a three-phase balanced voltage having a phase of 120 degrees. There will be no.

Therefore, in order to compensate for such distortion, space vector control is performed to compensate for the DC link voltage pulsation. A detailed operation description of the space vector control according to the present embodiment will be described below with reference to the configuration of the space vector controller 140 of FIG. 1.

The space vector controller 140 estimates a voltage value of the neutral node and performs space vector control on the switch unit 120 using the estimated voltage value of the node. Specifically, the space vector control unit 140 integrates the real axis voltage value of the one-phase output voltage of the three-phase output voltage of the output unit 130 to the time point before and after the voltage pulsation (the second capacitor). And a command vector V _O ^* for compensating for the DC link voltage pulsation using the estimated voltage value of the neutral node. The space vector controller 140 may perform PWM control on the plurality of switching elements by using the generated command vector V _O ^* . In the implementation, the operation of estimating the voltage value of the neutral node, generating the command vector, and performing the PWM control may be implemented through a separate configuration.

A method of estimating the voltage value of the neutral node in the space vector controller 140 will be described with reference to FIGS. 4 to 7.

Since a zero switch does not exist in the four-switch 3 inverter, a zero vector can be made by using a combination of vectors ν ₁ 'and ν ₃ ' that are relatively small in size and have low harmonics. The zero vector and the vectors ν ₂ ′ and ν ₄ ′ produced by this combination can be used to create a reference voltage vector (or command vector V _O ^* ) as shown in FIG. 3, depending on the position of the reference vector. The switching time for each switch element is shown in equations (2) and (3).

구역에 있어서,

In the zone,

구역에 있어서,

In the zone,

)이고, V_O ^*는 4 스위치 3상 인버터의 지령 전압 벡터(V_O ^*)의 크기이고, α는 벡터 V_O ^*와 실수축 사이의 각이고, T는 샘플 주기이다. 이와 같은 각각의 스위칭 소자에서의 스위칭 패턴을 도시화하면 도 4와 같다. Where Tx is the conduction time of the vector (

), And, V _O ^* is an angle between the switch 4 and the three-phase command magnitude of the voltage vector (V _O ^*) of the inverter, α is a vector V _O ^* and the real axis, T is the sample period. 4 shows the switching pattern of each switching device.

As can be seen from equations (2) and (3), the DC link voltage value must be known to improve the unbalance of the output voltage due to the DC link voltage pulsation.

FIG. 5 is a diagram showing a vector diagram of (a) and (b) of FIG. 3 simultaneously for analyzing a DC link voltage pulsation. FIG.

Referring to FIG. 5, V _α ^* and V _β ^* are output voltage components obtained by the command value when there is no pulsation of the DC link voltage, and V _α and V _β are actual voltage components output when there is a voltage pulsation. it means.

Meanwhile, in FIG. 2, even when _a current i _a flows from the neutral node and a pulsation of the DC link voltage occurs, the entire DC link voltage V _dc in the inverter may be considered to be constant. In this case, looking at the amount of change of ν _C1 and ν _C2 , since the magnitude is different and only the sign is different, the relation shown in Equation (4) can be obtained.

△ ν _C1 =-△ ν _C2

ν _C1 = V _dc / 2-Δν _C2

ν _C2 = V _dc / 2 + Δν _C2

Here, Δν _C1 is the voltage change of ν _C1 , and Δν _C2 is the voltage change of ν _C2 .

Using the equation (4) to obtain the voltage vectors shown in Figure 5 are shown in Table 2.

vector ν _α ν _β ν ₁

0 ν ₁ ''

0 ν ₂ 0

ν ₂ ''

ν ₂

0 ν ₂ ''

0 ν ₄ 0

ν ₄ ''

Referring to Table 2, it can be seen that even if the voltage of the neutral node of the capacitor unit 110 varies, the output voltage component ν _{β in the} β direction has no effect. That is, when analyzing or compensating the effect of the pulsation of the DC link voltage, it is not necessary to consider the values of ν _β ^* and ν _β , and use only the values of ν _α ^* and ν _α or their relationship to the capacitor unit 110. It can be seen that the effect on the pulsation of the neutral node can be compensated for.

On the other hand, when the relationship of ν _o ^* and ν _o is expressed by an equation, it is as shown in equation (5).

ν_o = ν_o ^* + △ν_o = ν_α ^* + △ν_o + ν_β ^*= ν_α + ν_β

ν _o = ν _o ^* + Δν _o = ν _α ^* + Δν _o + ν _β ^* = ν _α + ν _β

는

이다. Where Δν _o is the error of the voltage vector,

Is

to be.

만큼 이동한 것을 알 수 있다. ν₁,ν₁',ν₃,ν₃' 의 경우에도 마찬가지로 직류 링크 중성점의 맥동과 관계 없이 표 2에서 β방향 성분이 '0'으로 일정하다. 하지만, ν₁',ν₃'의 방향 α성분이 양의 방향으로

만큼 각각 이동하였음을 알 수 있다. That is, the error Δν _o of the output voltage vector is an α direction (real) component of ν _o ^* changed due to the DC link voltage pulsation. Observing each axis, the β direction (imaginary) component of ν ₂ , ν ₂ ', ν ₄ , ν ₄ ' is always constant in Table 2, while the α direction component is

You can see that you moved by. Similarly, in the case of ν ₁ , ν ₁ ', ν ₃ , ν ₃ ', the β direction component is constant as '0' in Table 2 regardless of the pulsation of the DC link neutral point. However, the direction α component of ν ₁ ', ν ₃ ' is positive

As can be seen that each has moved.

Further, Δν _o , which is the magnitude of the voltage in the α direction of the output voltage vector changed due to the voltage pulsation of the neutral node (direct link neutral point) of the capacitor unit 120 in the space vector control (or space vector PWM) scheme, is determined by ν ₂ . Derivation using the angle θ of ν ₂ 'is as follows.

Δν _o = ν _α -ν ^* _α = (ν ^* _α '-ν ^* _α ) + (ν _α -ν ^* _α ')

By arranging equations (6), (7), and (8), the magnitude of the error (Δν _o ) of the output voltage vector as shown in equation (9) can be obtained.

가 됨을 알 수 있다. As a result, an error occurring between the command vector ν ^* _o of the vector controller input terminal and the actual applied output voltage vector ν _{o due} to the voltage pulsation of the neutral node (direct link) of the capacitor unit 120 is represented by the β direction (imaginary) component. There is no change and only the α-direction component changes, which is equal to the amount of change in the reference vector.

It can be seen that.

In addition, using Equation (9), the instantaneous voltage ν _C2 of the second capacitor 112 may be expressed as in Equation 10 and Equation 11.

Therefore, when there is a voltage pulsation of the neutral node of the capacitor unit 120, the output voltage can be balanced if ν ^* _o can be generated such that the command vector ν ^* _o can be equal to the output voltage vector ν _o . This is also a vector of _{ν 1, ν 2, ν 3} , ν 4 ν 1 eseo _{^{5 ', ν 2', ν}} 3 command of the vector controller input terminal to match ^', ν _^4' vector ν ^* _o and a terminal voltage output vector If it means Manda the ν _o error △ ν _o takes place between "0" and _α ν is adjusted to a value △ ν _c2 to allow the ν ^* _α in equation (10) becomes possible.

In this embodiment, an integral controller such as Equation (12) was used to find the value of Δν _c2 where ν _α can be ν ^* _α . 6 shows the following characteristics according to the constant K value. If the K value is small, the following performance is deteriorated and the larger the instability is.

,

는 식 (13)과 같다. 7 is a block diagram for estimating the DC link voltages Δν _c2 , ν _c1 , ν _c2 , and an estimated value

,

Is as shown in equation (13).

,

,

,

를 앞서 설명한 식 (2), (3)를 이용하여, 직류 링크 전압 맥동을 보상한 지령 벡터를 생성함으로써, 출력 전압 불평형을 보상할 수 있게 된다. Estimated by equations (12) and (13)

,

By using Equation (2), (3) described above, by generating a command vector that compensates for the DC link voltage pulsation, it is possible to compensate for the output voltage unbalance.

Therefore, the space vector controller 140 may estimate the voltage value of the first capacitor 111 and the voltage value of the second capacitor 112 by using the above-described equations (2) and (3). By applying the voltage values of the capacitors 111 and 112 to equations (2) and (3), an output voltage waveform may be improved by generating a command vector that compensates for the neutral node pulsation of the capacitor unit 120.

Accordingly, the inverter 100 according to the present embodiment can compensate the output voltage unbalance of the inverter by estimating the DC link voltage value without using a separate device for measuring the DC link voltage (voltage of the neutral node). Will be.

8 is a flowchart illustrating a control method of an inverter according to an embodiment of the present invention.

Referring to FIG. 8, a switching period for each of a plurality of switch elements in a four-switch three-phase inverter is calculated (S810). An operation of calculating a switching period of each of the plurality of switch elements has been described above with reference to FIG. 4, and thus a detailed description thereof will be omitted.

Then, each of the plurality of switch elements in the inverter is controlled in accordance with the calculated switching cycle to generate a three-phase output power (S820). Specifically, switching control (PWM control) for each of the plurality of switch elements is performed according to the calculated switching period, and capacitors connected to the switching element are alternately charged and discharged in correspondence to the switching state of each switch element.

In operation S830, a voltage value of the neutral node to which the plurality of capacitors are connected to each other is estimated. Specifically, the voltage value of the neutral node may be estimated by integrating the real axis voltage value of the output power of one phase of the three-phase output power to the time before and after the pulsation according to the current flow of the neutral node. Specific formulas and methods for estimating the voltage value of the neutral node have been described above, and thus the detailed description thereof will be omitted.

Finally, the switching elements are controlled by recalculating the switching periods of the plurality of switch elements by using the estimated voltage value of the neutral node (S840). Accordingly, the control method according to the present exemplary embodiment may compensate for the output voltage unbalance of the inverter by estimating the voltage value of the neutral node without using a separate measuring device.

9 to 17 are diagrams showing experimental results of the inverter according to the present embodiment.

9 to 17 show that the motor is connected to the load end of the inverter, the main constant of the motor is as shown in Table 3.

Main constant Constant value Constant / pole 3 [upper] / 8 [pole] Rated output 3.0 [kW] Rated speed 1,000 [rpm] Moment of inertia

]67.8 [

] Torque constant 12.8 [

] Upper resistance 0.056 [ohm] Upper inductance 1.391 [mH] Counter voltage constant 78.7 [V / krpm]

9 is a waveform diagram of various voltages when the output voltage waveform is not compensated. Referring to FIG. 9D, it can be seen that the voltages of the first and second capacitors are not constant and change. In other words, there is a DC link voltage pulsation. Accordingly, since an error exists between the command voltage vector ν ^* _o and the output voltage vector ν _o , the linearity between ν ^* _o and ν _o is not maintained, so that the current value does not follow the command value properly, and as a result, the phase current i _a , you can see that i _b and i _c are unbalanced.

10 are various waveform diagrams when the voltage value of the capacitor is estimated and the output voltage waveform is compensated using the estimated voltage value. Referring to FIG. 10 (d), it can be seen that voltage values V _C1 and V _C2 of the first capacitor and the second capacitor are well estimated without using a separate voltage measuring device. In addition, when compared with FIG. 9, it can be seen that a markedly improved output voltage and current waveform is formed.

FIG. 11 and FIG. 12 are diagrams showing experimental results according to starting characteristics and torque fluctuations at a normal speed to investigate dynamic characteristics of a permanent magnet synchronous motor (PMSM) controller using a four-switch three-phase inverter. Specifically, in order to investigate the dynamic characteristics of a permanent magnet synchronous motor (PMSM) controller using a four-switch three-phase inverter, the motor is started at a speed command value of 500 rpm at 5 [N · m] at a stop state, and torque is 0.25 sec after starting. Is increased to 8 [N · m] and then reduced to 5 [N · m] again after 0.15 seconds.

FIG. 11 is a diagram illustrating an experimental result when the compensation for the output voltage is not performed, and FIG. 12 is a diagram illustrating an experimental result when the compensation for the output voltage is performed. Referring to FIGS. 11 and 12, when the inverter according to the present embodiment is used, the steady state error of the rotational speed is significantly reduced, and there is almost no unbalance between voltage and current.

13 is a waveform diagram comparing the voltage value of the second capacitor and the voltage value of the second capacitor estimated in the inverter according to the present embodiment. Referring to FIG. 13, it can be seen that the voltage value of the second capacitor estimated in the inverter according to the present embodiment coincides with the voltage value of the second capacitor.

14 is a waveform diagram comparing the estimated second capacitor voltage with the measured voltage of the second capacitor according to the speed change of the PMSM. Referring to FIG. 14, the current value increases with increasing torque command value of the motor in the starting phase of the motor, so that the second capacitor value may be well estimated even in a poor situation in which the second capacitor value drops sharply.

15 is a waveform diagram showing dynamic characteristics when the torque is changed. Referring to FIG. 15, it can be seen that the inverter according to the present embodiment well follows the speed command value even if the load varies.

16 is a waveform diagram of phase currents with and without a compensation algorithm. Specifically, (a) of FIG. 16 is a waveform diagram of the phase current when the compensation algorithm is not applied, and it can be confirmed that the three-phase output of the inverter is unbalanced. Referring to FIG. It can be seen that the imbalance of phase current is significantly reduced compared to.

17 is a diagram illustrating a path of a voltage applied to a PMSM. Referring to FIG. 18, it can be seen that the trajectory of the inverter according to the present embodiment becomes a circular shape having a constant distance from the center, and thus, a perfect equilibrium voltage is applied.

Although preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above, and the present invention belongs to the present invention without departing from the gist of the present invention as claimed in the claims. Various modifications can be made by those skilled in the art, and such changes are within the scope of the claims.

1 is a block diagram showing the configuration of an inverter according to an embodiment of the present invention;

FIG. 2 is a circuit block diagram specifically illustrating a configuration of a capacitor unit and a switch unit of FIG. 1;

3 shows the voltage vector of Table 1;

4 is a diagram showing a switching pattern of a 4 switch 3 inverter by space vector PWM;

5 is a vector diagram for a voltage pulsation analysis according to an embodiment of the present application;

6 is a diagram showing convergence characteristics according to a controller gain K value;

7 is a block diagram showing a node voltage estimation algorithm in the space vector PWM according to the present embodiment;

8 is a flowchart illustrating a control method of an inverter according to an embodiment of the present invention, and

9 to 17 are diagrams showing experimental results of the inverter according to the present embodiment.

* Description of the main parts of the drawings

100: inverter 110: capacitor

120: switch unit 130: output unit

140: space vector control

Claims (9)

A switch unit including a plurality of switch elements, the switch unit generating three-phase output power according to a switching operation of the plurality of switch elements; A capacitor unit including a plurality of capacitors connected in series to have a neutral node, and supplying a voltage generated by charging and discharging an input DC power to the plurality of switch elements; And And a space vector controller for estimating a voltage value of the neutral node and performing a space vector control on the switch unit by using the estimated voltage value of the neutral node. The space vector control unit, And a voltage value of the neutral node is estimated by integrating the real-axis voltage value of the one-phase output power of the three-phase output power to before and after voltage pulsation. delete The method of claim 1, The switch unit, A first switch group consisting of a first switch element and a third switch element connected in series; And And a second switch group consisting of a second switch element and a fourth switch element connected in series. The neutral node of the capacitor unit, a second node to which the first switch element and a third switch element are connected, and a third node to which the second switch element and the fourth switch element are connected to output the three-phase output power; inverter. The method of claim 1, The capacitor unit, A first capacitor connected to one side and one side of the input DC power and connected to the neutral node and the other side; And And a second capacitor connected to the other side and one side of the input DC power and connected to the neutral node and the other side. 5. The method of claim 4, The space vector control unit, Inverter, characterized in that for estimating the node voltage of the first capacitor and the second capacitor through the following equation.

here,

Is the node voltage value of the second capacitor,

Is the node voltage value of the first capacitor, V _dc is the DC voltage value, K is the gain value of the integrator, and V _α ^* is the real axis voltage value of the output voltage obtained by the command voltage vector when there is no voltage pulsation, V _α Is the real axis voltage value of the actual voltage output in the case of voltage pulsation. In the control method of the inverter having a plurality of capacitors and a plurality of switch elements connected in series with the DC power supply to output the three-phase output power, Calculating a switching period for each of the plurality of switch elements; Generating a three-phase output power by controlling each of the plurality of switch elements according to the calculated switching period; Estimating a voltage value of a neutral node to which the plurality of capacitors are interconnected; And And recalculating the switching periods of the plurality of switch elements using the estimated voltage value of the neutral node to control the switch elements. Estimating the voltage of the neutral node, And a voltage of the neutral node is estimated by integrating the real axis voltage value of the output power of one phase of the three-phase output power to before and after pulsation according to the current flow. delete The method of claim 6, The plurality of capacitors, A first capacitor connected to one side and one side of the DC power supply and connected to the neutral node and the other side; And And a second capacitor connected to the other side and one side of the DC power source and connected to the neutral node and the other side. The method of claim 8, Estimating the voltage of the neutral node, The control method of the inverter, characterized in that for estimating the voltage value of the first capacitor and the second capacitor through the following equation.

here,

Is the node voltage value of the second capacitor,

Is the node voltage value of the first capacitor, V _dc is the DC voltage value, K is the gain value of the integrator, V _α ^* is the real axis voltage value of the output voltage obtained by the command voltage vector when there is no voltage pulsation, V _α Is the real axis voltage value of the actual voltage output in the case of voltage pulsation.

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