KR101088563B1 - Method Of Controlling Multi-Core Processor, Apparatus For Controlling Multi-Core Processor, Multi-Core Processor, And Record Medium For Performing Method Of Controlling Multi-Core Processor - Google Patents

Abstract

Disclosed are a recording medium in which a multicore processor control method, a multicore processor control device, a multicore processor, and a multicore processor control method are recorded for efficient management of core resources in a multicore processor. The multi-core processor control method is driven by a multi-core processor using information obtained by determining the number of cores required for parallel processing of the program when the parallel program is executed, and determining the number of cores. Controlling the number of cores. Therefore, by efficiently managing core resources, the core resources of a multicore processor required for executing a program may be efficiently used to have a high quality of service (QoS) and to reduce power consumption of the multicore processor.

Multicore Processor, Multicore, Control, On-Demand, Parallel Programming

Description

Recording medium recording multi-core processor control method, multi-core processor control device, multi-core processor and multi-core processor control method (Method Of Controlling Multi-Core Processor, Apparatus For Controlling Multi-Core Processor, Multi-Core Processor, And Record) Medium For Performing Method Of Controlling Multi-Core Processor}

The present invention relates to a multicore processor control method, a multicore processor control device, a multicore processor, and more particularly, to reduce power consumption of a multicore processor and to efficiently manage core resources of the multicore processor. A control method, a multicore processor control apparatus, and a multicore processor.

Multi-core processor is a processor with two or more cores. In the case of the conventional single-core processor, the performance of the processor is improved by increasing the clock speed of the processor, but the power consumption and the processor are disadvantages of the method of increasing the clock speed. To improve heat dissipation, multicore processor technology has been developed that can operate at a relatively low frequency and distribute the power consumption of a single core to multiple cores.

When using a multicore processor, the dynamic power consumption can be reduced compared to that of a single core processor. But multicore processors don't completely solve the power problem. Since battery technology cannot keep up with processor performance, it is still a consideration for designers when designing digital processing devices that still provide reliable user time for digital processing devices by reducing power consumption in portable devices or embedded systems. The element to do.

The conventional method of reducing power consumption is to reduce the static power consumption of the digital processing device by reducing the leakage power just because the processor is not clocked but powered on. Another way to reduce the power consumption of the processor is to analyze the processor's total utilization in percentage units and adjust the number of cores running on the processor.

1 is a diagram illustrating a method of controlling a multicore processor using an on-demand method. The vertical axis of FIG. 1 indicates the use of a multicore processor in percentage and the horizontal axis is the time axis in seconds. If the multicore processor shows less than 80% utilization, stop one core or set it to low performance to reduce power consumption. The multicore processor is controlled by running the set core again or setting the high utilization rate. However, since this control method predicts future utilization based on past CPU utilization, there is a problem that the performance of the program cannot be guaranteed if the prediction fails. Assuming that the number of cores required for the parallel programming program is 4, in case of using the On-Demand method, one core is deactivated in the On-Demand method in 9 seconds to 12 seconds (section 1) in FIG. The utilization rate is below the 80% threshold. At this time, when the on-demand control method is applied, a situation arises in which one core is deactivated and only three cores are activated. However, due to the structure of the program, four processes are created, so the number of cores actually required is four. Therefore, in such a situation, the on-demand method does not guarantee the quality of service (QoS) of the program.

Accordingly, an object of the present invention is to provide a multicore processor control method for efficiently reducing the power consumption of a processor while maintaining the service quality of a parallel programmed program.

In addition, another object of the present invention is to provide a multi-core processor control device for providing the control method.

Another object of the present invention is to provide a multicore processor providing the control method.

Still another object of the present invention is to provide a recording medium on which the control method is recorded.

According to an aspect of the present invention, there is provided a method for controlling a multicore processor, the method comprising: determining a number of cores required for parallel processing of a program when executing a parallel programmed program; And controlling the number of cores running in the multicore processor using the information obtained through the step of determining the number of. The information obtained from the step of determining the number of cores required for the parallel processing may include information on whether the executed program belongs to a parallel processing section and information on the number of cores required for parallel processing of the executed program. Can be. The determining of the number of cores required for the parallel processing of the program includes executing a code automatically inserted by a compiler that compiles the program when the program is executed and executing the code by executing the code. And information on whether the number of cores required for parallel processing of the executed program is generated. Controlling the number of cores running in a multicore processor by using the information obtained through the determining of the number of cores comprises: information on whether the executed program belongs to a parallel processing section and the information of the executed program. On the basis of the information on the number of cores required for parallel processing, when there is a request for core resources corresponding to the number of cores required for parallel processing, the core currently allocated to the program is released and the cores are allocated as many as the requested number of cores. Reallocation. The method may determine that there is no other process allocated to the released core, and reassign the core when no other process is allocated. The reallocating step may include releasing cores currently allocated to the program by using bits representing the activation state of cores and reallocating cores by the number of requested core resources. Controlling the number of cores running in a multicore processor by using the information obtained through determining the number of cores is necessary for parallel processing of the executed programs when the executed programs belong to a parallel processing section. Requesting to allocate as many core resources as the number of cores, and requesting to allocate as many core resources as one core resource if the executed program does not belong to the parallel processing section. can do.

In accordance with another aspect of the present invention, there is provided a control apparatus for a multicore processor, the parallel processing analysis unit configured to determine the number of cores required for parallel processing of a program when executing a parallel program. And a core controller configured to control the number of cores driven in the multicore processor by using the information obtained through the determining of the number of cores. The information obtained from the step of determining the number of cores required for the parallel processing includes information on whether the executed program belongs to a parallel processing section and information on the number of cores required for parallel processing of the executed program. It may be characterized by. The parallel processing analyzing unit executes the code automatically inserted by a compiler that compiles the program when the program is executed, and executes the code so that information about whether the executed program belongs to a parallel processing section and the executed program is executed. The information on the number of cores required for parallel processing of may be generated. The core control unit is configured to generate as many as the number of cores required for the parallel processing based on information on whether the executed program belongs to a parallel processing section and information on the number of cores required for parallel processing of the executed program. When there is a request for a core resource, it may be characterized by releasing cores currently allocated to the program and reallocating cores by the number of the requested cores. The core controller determines whether there are other processes allocated to the released core in releasing cores currently allocated to the program and reallocating cores by the requested number of cores. It may be characterized by the assignment. In releasing cores currently allocated to the program and reallocating cores by the requested number of cores, the cores currently allocated to the program are released using bits representing the activation status of cores and the number of core resources requested. And reassign cores.

The multi-core processor according to an aspect of the present invention for achieving another object of the present invention is to determine the number of cores required for parallel processing of the program when executing a plurality of cores and a parallel processing programmed program, It may include a control unit for controlling the number of driven cores using the information obtained through the step of determining the number of cores.

In addition, the recording medium in which the multi-core processor control method according to an aspect of the present invention is recorded to achieve another object of the present invention described above is a program of instructions that can be executed by a digital processing device that performs parallel processing And controlling the core by using the information obtained by determining the number of cores required for the program and the number of cores, which can be read by the digital processing apparatus. You can record the program.

As described above, according to the recording medium in which the multi-core processor control method, the multi-core processor control device, the multi-core processor and the multi-core processor control method according to the embodiment of the present invention are recorded, the parallel processing of the processor The number of cores required to execute the program is determined, and the number of cores driven by the multicore processor is controlled based on the determined information.

Therefore, by controlling the number of cores running on a multicore processor, it is possible to guarantee the quality of service (QoS) of the program when executing a parallel-programmed program and to efficiently manage power of the multicore processor. have.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Like reference numerals are used for like elements in describing each drawing.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. Hereinafter, the same reference numerals are used for the same components in the drawings, and redundant description of the same components is omitted.

Hereinafter, embodiments of the present invention assume that a parallel programming model is used for power management of a multi-core processor. Here, the parallel programming model means that information (eg, a library function) indicating a parallel processing section and a serial processing section is included in a program. For example, the compiler compiles the parallel program code and automatically inserts code that can provide the kernel with information about the parallelism interval and the number of processes generated by the compiler when the application is run in real time. Automatically inserted code is executed to control the multicore processor.

FIG. 2 is a diagram illustrating a process or thread generated when executing a parallel programmed program according to an exemplary embodiment of the present invention. Referring to FIG. 2, when a program programmed in parallel processing is executed in a multicore processor, it may be divided into a section 210 in which parallel processing is required and a section 220 in which parallel processing is not required. The quality of service (QoS) can be analyzed by analyzing the section 210 where parallel processing is required and the section 220 where parallel processing is not required and assigning the exact number of cores required when the program is executed to the multicore processor. Quality of Service can be guaranteed and power management of multicore processors can be done efficiently.

3 is a flowchart illustrating a method for controlling a core of a multicore processor according to an embodiment of the present invention. Referring to FIG. 3, a method for controlling cores of a multicore processor according to an exemplary embodiment of the present invention includes a plurality of cores configured through a parallel processing analysis step 310 and a core control step 320. To control the cores.

4 is a block diagram of a multicore processor 400 in accordance with an embodiment of the present invention. Referring to FIG. 4, the multicore processor 400 includes a controller 410 and a plurality of cores 413-1, 413-2, 413-3, and 413-4. The control unit 410 is composed of a parallel processing analysis unit 411 core control unit 412. The parallel processing analysis unit 411 analyzes the parallel processing sections of each parallel processing programmed program and requests the core control unit 412 to allocate as many core resources as the number of processes used in the case of the parallel processing sections. If not in the processing section, the core controller 412 requests one core resource. The core control unit 412 stores and manages core resources used by the programs programmed in parallel processing, and handles the request when there is a new core allocation request.

5 is a flowchart specifically illustrating the parallel processing analysis step 310 of FIG. 3 performed by the parallel processing analysis unit 411 according to an embodiment of the present invention. The parallel processing analysis unit 411 determines whether to terminate the parallel processing programmed program being executed (step 311). The parallel processing analysis unit 411 determines whether the parallel processing section is a parallel processing section and the number of cores required for parallel processing if the program programmed in the parallel processing continues to be executed (step 312). In the case of a program that has been programmed for parallel processing, the code of the program can be analyzed to find out whether it is a parallel processing section and the number of processes required for parallel processing. In the parallel processing analysis unit 411, a core that is driven by a multicore processor provides a compiler for compiling a parallel processing programmed program with information about a parallel processing section of the program and information about the number of cores required for parallel processing of the program. The code transmitted to the core controller 412 that controls the number of times is automatically inserted so that when the program is executed, the inserted code is executed together so that the core controller 412 can request as many core resources as the number of processes of the target application program. (Step 314)

In addition, when the parallel processing analysis unit 411 determines from the information on the parallel processing section of the program, if it is not the parallel processing section, only one core resource is requested to the core control unit 412 (step 313). Power consumption can be reduced.

6 is a block diagram illustrating a core manager 610 managing core resources of a multicore processor according to an exemplary embodiment of the present invention. The core manager 610 data-cores and manages core resources in an ID form 620 of a master process (parent process) -slave process (child process). The numbers in the blocks of the figure are examples of master process ID (parent process) -slave process ID (child process).

FIG. 7 illustrates the core manager 610 of FIG. 6 storing and managing master process ID information and slave process ID information, and storing and managing ON / OFF bit information of a core to drive the core. An example of the core manager table for control.

8 is a flowchart illustrating the core control step 320 of FIG. 3 performed by the core control unit 412 according to an embodiment of the present invention. The core controller 412 issues a command to allocate or release a core to the master process based on the master process ID information displayed in the core manager table (see FIG. 7). The master process, which receives a command to allocate or free cores, dynamically allocates or frees cores allocated to slave processes to dynamically change the number of processes required to run in the program. The process of dynamically changing the number of processes required for a program by allocating or releasing cores changes the ON / OFF bit value of the core manager table in the core controller 412 and the core manager controls ON / OFF of the actual core.

Hereinafter, a core control step performed by the core controller 412 will be described with reference to FIG. 8. First, the core controller 412 determines whether there is a request for a core resource of an application program (step 321). If there is no request of core resources, for example, a parallel programmed program continuously executes the same number of processes and requires the same number of core resources, the core of the current multicore processor is kept running. Step 321). However, if there is a request for a new core resource, the core control unit 412 releases the core assigned to the parallel-programmed program (step 322). Releasing the assigned core releases the associated slave process by referring to the master process of the parallel program being executed (step 322). In step 322 of releasing the assigned core, the core controller 412 modifies the core manager table (see FIG. 7) without turning on or off the actual core to change the ON / OFF bit value of the core manager table. Can be done with. The core controller 412 determines whether there is a process allocated to the released core (step 323). If there is no newly allocated process in the unassigned core, the core controller 412 sets the ON / OFF bit of the corresponding core to OFF (step 324) and as many as the requested number of new core resources. Reallocate the core (step 325). The core controller 412 reallocates the core to the process from the core having the bit indicated as OFF by referring to the ON / OFF bit information of the core in the core manager table, and turns the core ON / OFF bit in the core manager table. Is made by modifying the information to ON (step 325). When there is a process allocated to the core released in step 323, the core controller 412 allocates two programs on the same core, for example, by the scheduler of the operating system responsible for distributing core resources. When the remaining one program which has not been released is being executed, the core is reallocated by the number of the requested new core resources without going through step 324 (step 325). In this case, the core manager 610 also determines the ON / OFF bit of the corresponding core, reallocates the core from the core having the bit indicated as OFF, and sets the ON / OFF bit of the corresponding core to ON. In actuality, the core manager determines the ON / OFF bit information of all cores in the core manager table to activate cores by the number of cores marked as ON (step 326). In order to update the core manager table, the master process ID and the slave process ID, which are process information allocated to the actual core, in the kernel information of the operating system are applied to the core manager table (step 327).

The flowchart of FIG. 8 will be described using an example of an actual application program executed by the core controller 412. In an embodiment, it is assumed that when a video player is run on a quad core processor having four cores, one process is used during execution of the video player program and then three processes are required. . If the example of FIG. 7 is used, the master process of the video player program may be assigned as ID 315. Since one process is required when executing the video playing program for the first time, core 0 is driven by assigning ID 315-315 to the master process ID-slave process. If three processes then change to the required situation, this request is sent to the master process (step 321) and the master process releases slave processes 315-315 (step 322). At this time, the core controller modifies the core manager table. Thereafter, if there is no process assigned to core 0, the ON / OFF bit of core 0 is set to OFF in the core manager table (step 324). Then, based on the ON / OFF bit information of Core 0, Core 1, Core 2, and Core 3 shown in the Core Manager table, if the three processes assumed above are required, the core marked OFF is Core 0, Core 1 And core 3, core 0, core 1 and core 3 are assigned to the video playback program and the ON / OFF bit information of core 0, core 1 and core 3 is changed to ON in the core manager table (step 325). Thereafter, the core manager checks the ON / OFF bit to activate cores as many as the number of ON marks (step 326). 315-316, Core 3: 315-317) are applied to the Core Manager table.

The flowchart of FIG. 8 will be described with another example of an actual application program executed by the core controller 412. Consider a case where a video player and a word processor are executed on a quad core processor having four cores. Currently, 3 processes are required for the video player, 2 processes are required for the word processor, 3 cores are allocated to the video player and 1 core is assigned to the word processor by the scheduler that allocates the core resources of the operating system. Assume that it is allocated. Based on these assumptions, based on the master process ID-slave process ID information illustrated in FIG. 7, the master process-slave process and the assignment state of the cores are illustrated. The video playback program includes core 0: 315-315 and core 1: 315. -316, core 2: 315-317 are assigned, and word processors core 3: 4150-4152, core 0: 4150-4150. In this case, since only 4 cores exist in the multicore processor, it is assumed that 3 cores are allocated to the video player and 1 core is allocated to the word processor by the scheduler that distributes the core resources of the operating system. If the core and master process ID-slave process ID are running on the real core, three video cores are assigned to the video player as core 0: 315-315, core 1: 315-316, and core 2: 315-317. Core 3: 4150-4152 is assigned and executed. Core 0: 4150-4150 of the word processor is currently waiting for execution in core 0 because a video playback program is being executed in core 0. If the state of the core resource distribution continues and changes to the state where two processes are required in the video program, the core 0: 315-315, the core 1: 315-316, and the core 2 are referred to in step 321 with reference to the master process of the video playback program. With 3 cores assigned as: 315-317, the command to release the core assignment to the master process by referring to the master process ID 315 of the video player is modified. (Step 322). At this time, the core manager's table (see Fig. 7) is not modified. To illustrate this situation, the cores assigned to the video program, which are matched core information and master process ID-slave process ID information on the core manager's table (see Fig. 7), are assigned to core 0: 315-315 and core 1: 315. -316, core 2: 315-317 are released on the core manager table. At this time, the word processor processes 4150-4150 allocated to core 0 are executed in the released core 0 and the remaining cores core 1 and core 2 set the ON / OFF bit to OFF in the core manager table through step 324. do. The core controller 412 reallocates cores by two processes requested through step 321 (step 325). In the step of allocating core, the ON / OFF bit of the core manager table is determined and allocated. The program is reallocated. Thereafter, all the ON / OFF bits of the core manager 610 are inspected to actually activate the core (step 326), and among the kernel information of the operating system, process information allocated to the actual core is applied to the core manager table (step 327).

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

1 is a graph illustrating a power management method of a multicore processor using an on-demand method.

2 is a diagram illustrating a process or thread generated when executing a parallel programmed program according to an exemplary embodiment of the present invention.

3 is a flowchart illustrating a method for controlling a core of a multicore processor according to an embodiment of the present invention.

4 is a block diagram of a multicore processor according to an embodiment of the present invention.

5 is a flowchart showing in detail the parallel processing analysis step performed in the parallel processing analysis unit according to an embodiment of the present invention.

6 is a block diagram illustrating a core manager for managing core resources of a multicore processor according to an exemplary embodiment of the present invention.

7 is an example of a core manager table according to an embodiment of the present invention.

8 is a flowchart illustrating a core control step performed in the core control unit according to an embodiment of the present invention.

Claims (15)

Executing a program automatically inserted by a compiler for compiling the program when executing a parallel program; Executing the code to generate information on whether the executed program belongs to a parallel processing section and information on the number of cores required for parallel processing of the executed program; And The number of cores running in a multicore processor is controlled using information on whether the code is executed and the executed program belongs to a parallel processing section, and information on the number of cores required for parallel processing of the executed program. Multi-core processor control method comprising the step of. delete delete The method of claim 1, wherein the controlling of the number of cores running in the multicore processor comprises: There may be requests for as many core resources as the number of cores required for the parallel processing based on information on whether the executed program belongs to a parallel processing section and information on the number of cores required for parallel processing of the executed program. And reallocating cores currently allocated to the program and reallocating cores by the requested number of cores. The method of claim 4, wherein the reassignment step, And determining that there is no other process allocated to the released core, and reassigning the core when no other process is allocated. The method of claim 4, wherein the reassignment step, Releasing a core currently allocated to the program by using a bit representing an activation state of a core and reallocating cores by the number of requested core resources. The method of claim 1, wherein the controlling of the number of cores running in the multicore processor comprises: Requesting to allocate as many core resources as the number of cores required for parallel processing of the executed program if the executed program belongs to a parallel processing section; And And requesting to allocate as many core resources as one core resource if the program to be executed does not belong to the parallel processing period. In the control device of a multicore processor, When executing the programmed program, the code inserted automatically by the compiler compiling the program is executed, the information is executed whether the code is executed and the executed program belongs to the parallel processing section and the parallel of the executed program. A parallel processing analysis unit for generating information on the number of cores required for processing; And The code is executed from the parallel processing analyzer to run on a multicore processor using information on whether the executed program belongs to a parallel processing section and information on the number of cores required for parallel processing of the executed program. Control device of a multi-core processor including a core control unit for controlling the number of cores to be. delete delete The method of claim 8, wherein the core control unit, There may be requests for as many core resources as the number of cores required for the parallel processing based on information on whether the executed program belongs to a parallel processing section and information on the number of cores required for parallel processing of the executed program. And, when releasing cores currently assigned to the program and reallocating as many cores as the requested number of cores. The method of claim 11, wherein the core control unit, In releasing cores currently allocated to the program and reallocating cores by the requested number of cores, And determining that there is no other process allocated to the released core, and reassigning the core when no other process is allocated. The method of claim 11, wherein the core control unit, In releasing cores currently allocated to the program and reallocating cores by the requested number of cores, The controller of the multicore processor, comprising: releasing a core currently allocated to the program by using a bit representing an activation state of a core and reallocating cores by the number of requested core resources. In the recording medium on which a program of instructions that can be executed by a digital processing apparatus that performs parallel processing is tangibly implemented, and which records a program that can be read by the digital processing apparatus, Executing code automatically inserted by a compiler that compiles the program when the program is executed; Executing the code to generate information on whether the executed program belongs to a parallel processing section and information on the number of cores required for parallel processing of the executed program; And A program for performing core control using the information on whether the code is executed and the executed program belongs to a parallel processing section and the number of cores required for parallel processing of the executed program. Record carrier. In a multicore processor, A plurality of cores; And When executing the programmed program, the code inserted automatically by the compiler compiling the program is executed, the information is executed whether the code is executed and the executed program belongs to the parallel processing section and the parallel of the executed program. Information about the number of cores required for processing is generated, and information about whether the code is executed and the executed program belongs to a parallel processing section, and information about the number of cores required for parallel processing of the executed program A multicore processor comprising a control unit for controlling the number of cores to be driven using.

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