KR101087776B1 - Semiconductor device and method for forming using the same - Google Patents

Abstract

The present invention is provided in a semiconductor substrate, and is provided on the barrier metal surrounding the charge flow metal layer and the sidewalls and the lower portion of the charge flow metal layer recessed to have a height lower than the flattened height on the semiconductor substrate, and the barrier metal sidewall. By including a barrier insulating film embedded in the substrate, the parasitic field effect is reduced due to high integration, thereby solving the problem of lowering the threshold voltage, thereby improving the characteristics of the semiconductor device.

Recess gate prevents parasitic field effect

Description

Semiconductor device and method for forming using the same

The present invention relates to a semiconductor device and a method for forming the same, and more particularly, to a semiconductor device and a method for forming the same that can reduce the parasitic field effect caused by high integration.

As the design rule of the semiconductor device, which has recently been developed, is reduced, the channel length is correspondingly reduced. This trend is reducing the channel length of transistors in peripheral circuits as well as cell transistors serving as storage units. As a result, in implementing the threshold voltage (Vt) target of the transistor (transistor) required by a particular device, the conventional planar transistor structure is facing its limitations.

Accordingly, in order to overcome the above problems, a transistor having a gate having a three-dimensional structure, that is, a recess gate is formed by etching a semiconductor substrate, and then a gate is formed on the recess. Research on transistors, such as a fin gate structure, which protrudes an active region in the form of a fin by recessing a structure or an isolation layer and forms a gate thereon, has been actively conducted. Such a three-dimensional gate has the advantage of increasing the effective channel length because the channel length can be secured by using the etched substrate portion as a channel.

Meanwhile, a recess formed in the semiconductor substrate to form a three-dimensional gate is formed in the device isolation film as well as the active region. However, a gate (hereinafter, referred to as a passing gate) formed on the recess formed in the device isolation film affects the gate formed on the recess formed in the active region adjacent to the device isolation film.

Specifically, during the etching process of the semiconductor substrate for forming the recess, the device isolation layer through which the passing gate passes is also etched, so that the passing gate is closer to the recess by the depth of the recess in which the device isolation layer is etched, so that electrons are removed from the source. Differential potentials near the source junction and channel act as barriers to entry into the channel, causing bias in neighboring and passing gates to increase the electrical potential around them. This reduces the difference in electrical potential between the channel and source junction regions, which facilitates the inflow of electrons from the source to the channel, thereby reducing the Passing Gate Effect, which reduces the cell transistor threshold. Causing deterioration of transistor characteristics.

In addition, as the distance between the recess gate and the neighboring recess gate decreases due to high integration of the semiconductor device, the vertical channel potential increases, thereby reducing the threshold voltage of the cell transistor. neighbor gate effect) appears to deteriorate the characteristics of the semiconductor device.

In particular, since the poly is further filled on the device isolation layer of the fin gate by the height of the fin gate, a triple gate effect is induced, and thus the characteristics of the semiconductor device may be further deteriorated.

The present invention aims to solve the problem that parasitic field effects such as a passing gate effect and an adjacent gate effect are caused as the semiconductor device is gradually integrated and the gate and the neighboring gate become closer together.

The present invention includes a charge flow metal layer provided in a semiconductor substrate and recessed to have a height lower than the flattened height of the semiconductor substrate, a barrier metal surrounding sidewalls and lower portions of the charge flow metal layer, and provided on the barrier metal sidewall and And a barrier insulating film embedded in the semiconductor substrate.

In this case, the planarized oxide film may be further formed on the whole including the charge flow metal layer and the barrier insulating film.

And recesses formed in the oxide film and the barrier insulating film.

In this case, the gate electrode may further include a gate electrode formed on the recess.

In addition, the method may further include an ion implantation region provided under the charge flow metal layer.

And, the charge flow metal layer is characterized in that tungsten.

In addition, the barrier metal is characterized in that the TiN.

A method of forming a semiconductor device according to the present invention includes forming a trench in a semiconductor substrate, forming a barrier insulating film on the sidewalls of the trench, forming a barrier metal over the entirety of the barrier metal, and planarizing the semiconductor substrate over the barrier metal. And forming a recessed charge flow metal layer to have a height that is less than the height.

In this case, the method may further include forming a planarized oxide film on the entire upper portion after the forming of the charge flow metal layer and forming a recess in the oxide film and the semiconductor substrate.

The forming of the recess may include forming a hard mask layer on the oxide layer, forming a photoresist pattern defining the recess on the hard mask layer, and using the photoresist pattern as an etch mask. And etching the semiconductor substrate.

After the forming of the recess, the method may further include forming a gate on the recess.

After the forming of the barrier insulating film, the method may further include forming an ion implantation region by performing an ion implantation process on the semiconductor substrate exposed between the barrier insulating films.

In addition, the ion implantation process is characterized in that the implantation of P ions.

After the forming of the ion implantation region, the method may further include performing rapid thermal annealing (RTA) on the entire upper portion.

The charge flow metal layer is formed by chemical vapor deposition (CVD).

The present invention solves the problem of lowering the threshold voltage by reducing the parasitic field effect caused by the high integration of the semiconductor device provides an effect of improving the characteristics of the semiconductor device.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

1 is a plan view of a semiconductor device according to the present invention, Figure 2 is a cross-sectional view of a semiconductor device according to the present invention, Figures 3a to 3k is a cross-sectional view showing a method of forming a semiconductor device according to the present invention, (i) It is sectional drawing which cut y-y1, (ii) is sectional drawing which cut x-x1.

As shown in FIG. 2, the semiconductor device of the present invention includes a charge flow metal layer 122 and a charge flow metal layer recessed to have a height lower than the flattened height of the semiconductor substrate 100 provided in the semiconductor substrate 100. The semiconductor substrate 100 includes a barrier metal 120 surrounding the sidewalls and a lower portion, a barrier insulating layer 114 embedded in the semiconductor substrate 100, and a charge flow metal layer 122 disposed on the sidewalls of the barrier metal 120. ), An oxide film 124 is formed. The barrier 130 further includes a recess 130 in which the barrier insulating layer 114 and the semiconductor substrate 100 are etched to a predetermined distance from the charge flow metal layer 122 having the barrier metal 120 formed on the sidewall thereof. In this case, although not shown, the gate is preferably formed on the recess 130. In addition, it is preferable to further include an ion implantation region 118 provided under the charge flow metal layer 122. Here, the ion implantation region 118 facilitates the transfer of charges to the surface of the barrier metal 120 to the semiconductor substrate rich in electrons and holes. In this case, the charge flow metal layer 122 is preferably tungsten, and the barrier metal 120 is preferably TiN.

As described above, the semiconductor device according to the present invention can improve the problem that the threshold voltage of the cell transistor is lowered by providing the charge flow metal layer 122 between the gate formed in the device isolation layer, that is, the passing gate.

As shown in FIG. 3A, a pad oxide film 102 and a pad nitride film 104 are formed on the semiconductor substrate 100. Next, a photoresist pattern (not shown) defining an isolation layer is formed on the pad nitride layer 104, and the trench is etched by etching the pad nitride layer 104, the pad oxide layer 102, and the semiconductor substrate 100 using an etching mask. Form 106.

As shown in FIG. 3B, a gap fill insulating film is formed over the entire portion including the trench 106, and then the planarization etching process is performed on the gap fill insulating film to expose the pad nitride film 104. The separator 108 is formed.

As shown in FIG. 3C, after applying the hard mask layer over the entirety including the device isolation film 108, the hard mask layer is applied to the passivation gate (recess to be formed in the device isolation film 108) in a subsequent process. The photoresist layer pattern 112 may be formed to expose the region to be formed, and the hard mask layer may be etched using the etch mask to form the hard mask pattern 110.

As shown in FIG. 3D, the barrier layer 114 is formed on the sidewall of the active region by etching the device isolation layer 108 to expose the semiconductor substrate 100 using the hard mask pattern 110 as an etch mask. Here, etching the device isolation layer 108 to expose the semiconductor substrate 100 facilitates transfer of charges flowing through the barrier metal surface to be formed on the barrier insulating layer 114 to the semiconductor substrate rich in electrons and holes in a subsequent process. To make it possible.

As shown in FIG. 3E, a hard mask pattern 116 is formed on the barrier insulating layer 114 and the active region. Using the hard mask pattern 116 as a mask, an ion implantation process (A) is performed over the entire portion to form the ion implantation region 118. At this time, the ion implanted in the ion implantation step (A) is preferably P. The reason for performing the ion implantation process (A) as described above is to improve the contact resistance between the barrier metal and the semiconductor substrate when the barrier metal to be formed on the barrier insulating layer 114 is connected to the semiconductor substrate in a subsequent process. In general, when a metal is in contact with a semiconductor substrate, the work fuction of the metal is usually located in the middle of the band gap of the semiconductor substrate, thereby becoming a schottkey contact. Here, ion implantation changes the Schottky contact into an ohmic contact so that the charges easily move to the semiconductor substrate. That is, the depletion width is narrowed by the ion implantation region 118 formed by being doped into the semiconductor substrate by an ion implantation process, and the width of the potential barrier becomes thin, thereby allowing carriers to be quantum tunneled. Can cause charges to pass through the barrier.

As shown in FIG. 3F, the hard mask pattern 116 is removed. Then, RTA (Rapid Thermal Annealing, B) is performed over the entire top. RTA (B) is for activating the doped ions in the above-described process.

As shown in FIG. 3G, the barrier metal 120 is formed over the entirety. At this time, the barrier metal 120 is preferably TiN. Here, the barrier metal 120 reduces the stress between the barrier insulating layer 114 and the charge flow metal layer interface formed in a subsequent process, thereby facilitating adhesion of the charge flow metal layer.

As shown in FIG. 3H, the charge flow metal layer 122 is formed over the entirety of the barrier metal 120. In this case, the charge flow metal layer 122 is preferably formed by chemical vapor deposition (CVD). Since CVD is superior in terms of step coverage compared to physical vapor deposition (PVD), it can be easily bonded along the surface of the barrier metal 120.

As shown in FIG. 3I, it is preferable to planarize the semiconductor substrate 100 by performing an etch back process so that the semiconductor substrate 100 is exposed to the charge flow metal layer 122. Thereafter, a recess 123 having a predetermined depth is formed in the charge flow metal layer 122. The reason is that during the landing plug hole forming process of exposing the semiconductor substrate to form the landing plug, since the portion where the charge flow metal layer 122 is formed becomes the lower portion of the landing plug that is connected to the bit line contact to be formed in a subsequent process. This is to prevent the charge flow metal layer 122 from being exposed and connected to the landing plug.

As illustrated in FIG. 3J, the oxide film 124, the hard mask layer 126, and the photoresist pattern 128 are formed on the entire surface including the recess 123. The photoresist pattern 128 may define a recess by etching the barrier insulating layer 114 and the semiconductor substrate 100 formed on the device isolation layer.

As shown in FIG. 3K, the recess 130 is defined by etching the hard mask layer 126, the oxide layer 124, and the barrier insulating layer 114 using the photoresist pattern 128 as an etch mask. Although not shown, a recess is preferably formed in the semiconductor substrate 100 as well as the barrier insulating layer 114. Thereafter, the photoresist pattern 128 and the hard mask layer 126 are removed. Next, although not shown, it is desirable to form a gate on the recess 130. Here, the parasitic field effect between the adjacent gates is conventionally removed by the charge flow metal layer 122 to lower the threshold voltage of the cell transistor.

As described above, the present invention improves the characteristics of the semiconductor device by forming a charge flow metal layer to reduce the parasitic field effect caused by the pass gate effect due to the recess gate formed in the device isolation layer and the adjacent gate effect due to the high integration. You can.

1 is a plan view of a semiconductor device according to the present invention.

2 is a cross-sectional view of a semiconductor device according to the present invention.

3A to 3K are cross-sectional views illustrating a method of forming a semiconductor device according to the present invention, (i) is a cross-sectional view of y-y1, and (ii) is a cross-sectional view of x-x1.

Claims (15)

A charge flow metal layer provided in the semiconductor substrate and recessed to have a height lower than a height flattened on the semiconductor substrate; A barrier metal surrounding the sidewalls and the bottom of the charge flow metal layer; And A barrier insulating layer disposed on the barrier metal sidewall and embedded in the semiconductor substrate; And an ion implantation region provided under the charge flow metal layer. A semiconductor device, characterized in that. Claim 2 has been abandoned due to the setting registration fee. The method according to claim 1, And a planarized oxide film formed on the entire surface including the charge flow metal layer and the barrier insulating film. Claim 3 was abandoned when the setup registration fee was paid. The method according to claim 2, And a recess formed in said oxide film and said barrier insulating film. Claim 4 was abandoned when the registration fee was paid. The method of claim 3, And a gate electrode formed on the recess. delete Claim 6 was abandoned when the registration fee was paid. The method according to claim 1, And the charge flow metal layer is tungsten. Claim 7 was abandoned upon payment of a set-up fee. The method according to claim 1, And the barrier metal is TiN. Forming a trench in the semiconductor substrate; Forming a barrier insulating film on the sidewalls of the trench; Forming a barrier metal over the entirety; And Forming a recessed charge flow metal layer over the barrier metal to have a height lower than the flattened height in the semiconductor substrate, After forming the barrier insulating film, And forming an ion implantation region by performing an ion implantation process on the semiconductor substrate exposed between the barrier insulating films. Claim 9 was abandoned upon payment of a set-up fee. The method according to claim 8, After forming the charge flow metal layer Forming a planarized oxide film over the entire surface; And Claim 10 was abandoned upon payment of a setup registration fee. The method according to claim 9, Forming the recess Forming a hard mask layer on the oxide film; Forming a photoresist pattern defining the recess on the hard mask layer; And And etching the oxide film and the semiconductor substrate using the photoresist pattern as an etch mask. Claim 11 was abandoned upon payment of a setup registration fee. The method according to claim 10, After forming the recess, And forming a gate over the recess. delete Claim 13 was abandoned upon payment of a registration fee. The method according to claim 8, The ion implantation process is a method of forming a semiconductor device, characterized in that for implanting P ions. Claim 14 was abandoned when the registration fee was paid. The method according to claim 8, After forming the ion implantation region, Method for forming a semiconductor device, characterized in that further comprising the step of performing a rapid thermal annealing (RTA) over the entire. Claim 15 was abandoned upon payment of a registration fee. The method according to claim 8, The charge flow metal layer is A method of forming a semiconductor device, characterized in that formed by CVD (chemical vapor deposition).

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