KR101086904B1 - Dual mode latch flip-flop circuit, semiconductor circuit comprising the same and method for enhancing timing yield of the semiconductor circuit - Google Patents

Abstract

A dual mode latch flip-flop circuit is provided. The dual-mode latch flip-flop circuit receives a clock signal, delays it, and outputs a delayed clock signal. A NAND gate receives a clock signal, a clock signal, a delayed clock signal, and a data signal to perform a NAND operation to output a NAND output signal. And a latch circuit for receiving a NAND output signal, a clock signal, and a delayed clock signal to store a data signal, and a mode switch having one end connected to the NAND gate circuit and the latch circuit, wherein at least one of the NAND gate circuit and the latch circuit is provided. The operating speed varies according to the output signal of the mode switch.

Dual-Mode Latched Flip-Flop, NMOS Transistor, Threshold Voltage

Description

Dual mode latch flip-flop circuit, semiconductor circuit comprising the same and method for enhancing timing yield of the semiconductor circuit}

The present invention relates to a dual mode latch flip-flop circuit.

As process miniaturization continues in the semiconductor fabrication process, process variations in which variations such as channel length and threshold voltage of transistors occur during the semiconductor fabrication process are increasing. Such process variations result in variations in the operating speed, leakage power consumption, etc., which are the main performance indicators of the semiconductor circuits, resulting in performance variations of the semiconductor chips.

Such variation in performance lowers the yield of the semiconductor chip, and the lowered yield adversely affects the manufacturing cost of the semiconductor chip. Therefore, studies on yield enhancement techniques for improving the yield of semiconductor chips are active.

Flip-flops are used as data storage elements in digital circuits of semiconductor integrated circuits. These flip-flops sample input data at a specific point of time by a clock signal and convert the data into an output signal. In the semiconductor circuit including the flip-flop, when the above-described process variation occurs, various operating characteristics of the flip-flop may occur. In addition, this variation in operating characteristics can cause flip-flops to store incorrect input data, which can cause unexpected errors in semiconductor circuits. This error lowers the yield of the semiconductor chip.

An object of the present invention is to provide a dual mode latch flip-flop circuit that can improve the timing yield of a semiconductor circuit.

Another object of the present invention is to provide a semiconductor circuit including the dual mode latch flip-flop circuit with improved timing yield.

Another object of the present invention is to provide a method for improving timing yield of semiconductor circuits using the dual mode latch flip-flop circuit.

Problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

An aspect of the dual-mode latch flip-flop circuit of the present invention for achieving the above object is a clock delay circuit, a clock signal, a delayed clock signal and a data signal that receives a clock signal and delays it to output a delayed clock signal. A NAND gate circuit for receiving a NAND operation and outputting a NAND output signal, a latch circuit for receiving a NAND output signal, a clock signal, and a delayed clock signal to store a data signal, and one end of the NAND gate circuit and a latch circuit connected to the NAND gate circuit and the latch circuit. Including a mode switch, at least one of the NAND gate circuit and the latch circuit is variable in operation speed according to the output signal of the mode switch.

One aspect of a semiconductor circuit of the present invention for achieving the above another object is a voltage line, a plurality of the dual-mode latch flip-flop circuit, and a plurality of mode switches and voltage lines disposed between each mode switch of each dual-mode latch flip-flop circuit Of the fuse.

One aspect of the timing yield improvement method of the semiconductor circuit of the present invention for achieving the above another object is a predetermined number of latch flip-flops that affect the timing yield of the semiconductor circuit among the plurality of latch flip-flop circuits constituting the semiconductor circuit. Extracting the circuit, replacing the extracted latch flip-flop circuit with the dual-mode latch flip-flop circuit, and converting the mode of the replaced dual-mode latch flip-flop circuit to the fast mode.

Other specific details of the invention are included in the detailed description and drawings.

The latch flip-flop circuit, which adversely affects the timing yield, is replaced by the dual-mode latch flip-flop circuit, and the replaced dual-mode latch flip-flop circuit also checks for a timing failure again. As a result, the timing yield of the entire circuit can be improved at a low cost.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims.

Like reference numerals refer to like elements throughout the specification, and "and / or" includes each and every combination of one or more of the mentioned items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, "comprises" and / or "made of" components, steps, operations and / or elements referred to may include one or more other components, steps, operations and / or elements. It does not exclude the presence or addition of it.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used in a sense that can be commonly understood by those skilled in the art. In addition, the terms defined in the commonly used dictionaries are not ideally or excessively interpreted unless they are specifically defined clearly.

Hereinafter, a dual mode latch flip-flop circuit according to an embodiment of the present invention will be described with reference to FIG. 1.

1 is a circuit diagram of a dual-mode latch flip-flop circuit according to an embodiment of the present invention.

Referring to FIG. 1, the dual mode latch flip-flop circuit 10 includes a clock delay circuit 100, a NAND gate circuit 200, a latch circuit 300, and a mode switch 400.

The clock delay circuit 100 may be a circuit that receives a clock signal CLK and delays the clock signal CLK to output a delayed clock signal / CLK. In detail, the clock delay circuit 100 may be a circuit in which three inverters are connected in series, as shown in FIG. 1, and a difference between a delayed clock signal / CLK and a clock signal CLK is output. May be equal to the delay time of these three inverters. In addition, the state of the delay clock signal / CLK may be opposite to that of the clock signal CLK. For example, when the clock signal CLK is in a high state, the delayed clock signal / CLK may be in a low state. In contrast, when the clock signal CLK is in a low state, the delay clock signal / CLK may be in a high state.

The NAND gate circuit 200 may be a circuit that receives a clock signal CLK, a delayed clock signal / CLK, and a data signal D to perform a NAND operation to output the NAND output signal X. FIG. In detail, the NAND gate circuit 200 includes the first PMOS transistor 201 and the first to third NMOS transistors 202 to 204 connected in series between a voltage terminal provided with a power supply voltage VDD and a ground terminal, and a voltage terminal and a mode. The third PMOS transistor 205 and the fourth to sixth NMOS transistors 206 to 208 connected in series between the switch 400, and the third PMOS transistor connected between the voltage terminal and the gate terminal of the eighth NMOS transistor 303 ( 209).

Here, the threshold voltages of the fourth to sixth NMOS transistors 206 to 208 constituting the NAND gate circuit 200 of the dual mode latch flip-flop circuit 10 according to an embodiment of the present invention are the first. To lower than the threshold voltage of the third NMOS transistors 202 to 204. In FIG. 1, the thick lines displayed at the gate terminals of the fourth to sixth NMOS transistors 206 to 208 represent this. In addition, the widths of the fourth to sixth NMOS transistors 206 to 208 may be smaller than the widths of the first to third NMOS transistors 202 to 204. Therefore, when the first to third NMOS transistors 202 to 204 and the fourth to sixth NMOS transistors 206 to 208 are operated together rather than when only the first to third NMOS transistors 202 to 204 operate. The speed of operation can be faster.

The latch circuit 300 may receive the NAND output signal X, the clock signal CLK, and the delayed clock signal / CLK to store the data signal D.

Specifically, the latch circuit 300 includes the fourth PMOS transistor 301 and the seventh to ninth NMOS transistors 302 to 304 and the fourth PMOS transistor 301 connected in series between the voltage terminal VDD and the ground terminal. The tenth to twelfth NMOS transistors 305 to 307 connected in series between one end and the mode switch 400 may be included.

Here, the threshold voltages of the tenth to twelfth NMOS transistors 305 to 307 constituting the latch circuit 300 of the dual mode latch flip-flop circuit 10 according to an embodiment of the present invention are the seventh to ninth NMOS transistors. It may be lower than the threshold voltage of (302 ~ 304). In FIG. 1, the thick lines marked at the gate ends of the tenth to twelfth NMOS transistors 305 to 307 are also expressed. Similarly, the widths of the tenth to twelfth NMOS transistors 305 to 307 may be smaller than the widths of the seventh to ninth NMOS transistors 302 to 304. Therefore, when the seventh to ninth NMOS transistors 302 to 304 and the tenth to twelfth NMOS transistors 305 to 307 operate together than when only the seventh to ninth NMOS transistors 302 to 304 operate. The speed of operation can be faster.

One end of the mode switch 400 may be connected to the NAND gate circuit 200 and the latch circuit 300. In detail, the mode switch 400 may be configured as a mode switch transistor as shown in FIG. 1, and one end of the mode switch transistor is the sixth NMOS transistor 208 and the latch circuit 300 of the NAND gate circuit 200. May be connected to the twelfth NMOS transistor 307, the other end thereof is connected to the ground terminal, and a mode signal may be provided to the gate terminal.

When the mode signal provided to the gate terminal of the mode switch transistor is a normal mode signal (for example, a low state), the fourth to sixth NMOS transistors 206 to 208 and the tenth to tenth signals. The 12 NMOS transistors 305 to 307 may be disabled, and the fourth to sixth NMOS transistors 206 ˜ when the mode signal is a fast mode signal (for example, a high state). 208 and the tenth to twelfth NMOS transistors 305 to 307 may be enabled.

Next, an operation of the dual mode latch flip-flop circuit 10 according to an exemplary embodiment of the present invention will be described with reference to FIG. 1.

First, operation of the dual mode latch flip-flop circuit 10 in the normal mode will be described. Specifically, when the normal mode signal (for example, a low state) is provided as the mode signal, the fourth to sixth NMOS transistors 206 to 208 and the tenth to twelfth NMOS transistors 305 to 307 are divided. You do not need to consider this because it is enabled.

Referring to FIG. 1, when the clock signal CLK is in a low state (for example, 0), the delayed clock signal / CLK is in a high state (for example, 1), and is related to the data signal D at this time. NAND output signal (X) can be high without. Thus, the latch circuit 300 is in a non-transparent state and the flip-flop circuit 10 can hold the previous data signal D.

In contrast, when the clock signal CLK becomes high, both the clock signal CLK and the delayed clock signal / CLK may be in a high state during a short delay time by the three inverters of the clock delay circuit 100. have. Therefore, the NAND output signal X may be an inverted data signal / D. Since the output signal Q is equal to the inverted NAND output signal / X, which is the same as the data signal D, the flip-flop circuit 10 may store the data signal D.

However, after a short delay by three inverters of the clock delay circuit 100, the clock signal CLK is still high but the delayed clock signal / CLK is low. Regardless, the NAND output signal X may be high. Accordingly, the latch circuit 300 may be in a non-transparent state and the flip-flop circuit 10 may maintain the previously stored data signal D regardless of the input data signal D.

Next, operation of the dual mode latch flip-flop circuit 10 in the fast mode will be described. Specifically, when the fast mode signal (for example, a high state) is provided as the mode signal (Mode), the fourth to sixth NMOS transistors 206 to 208 and the tenth to twelfth NMOS transistors 305 to 307 are This should be taken into account because it is enabled.

The operation of the dual mode latch flip-flop circuit 10 for storing the data signal D according to the clock signal CLK is the same as that of the normal mode described above, but the fourth to sixth NMOS transistors 206 to 208 are formed in the same manner. Since the threshold voltages are lower than those of the first to third NMOS transistors 202 to 204, they may operate at a higher speed. In addition, since the threshold voltages of the tenth to twelfth NMOS transistors 305 to 307 are lower than those of the seventh to ninth NMOS transistors 302 to 304, the tenth to twelfth NMOS transistors 305 to 307 may operate at a higher speed. This is because devices with lower threshold voltages generally have higher leakage current than higher devices, but can operate at higher speeds. In conclusion, when the dual mode latch flip-flop circuit 10 operates in the fast mode, the operating speed is higher due to the fourth to sixth NMOS transistors 206 to 208 and the tenth to twelfth NMOS transistors 305 to 307. Can be faster. Therefore, the dual mode latch flip-flop circuit 10 according to an embodiment of the present invention can improve the timing yield of the semiconductor circuit.

Next, a method of improving a yield of a semiconductor circuit including a dual mode latch flip-flop circuit and a semiconductor circuit including a dual mode latch flip-flop circuit will be described with reference to FIGS. 2 to 5.

2 is a flowchart illustrating a method of improving yield of a semiconductor circuit in accordance with an embodiment of the present invention. 3 and 4 are intermediate steps for explaining a method of improving yield of a semiconductor circuit according to an embodiment of the present invention. 5 is a diagram for describing a semiconductor circuit according to an exemplary embodiment of the present invention.

First, referring to FIG. 2, a predetermined number of latch flip-flop circuits affecting timing yield of a semiconductor circuit among a plurality of latch flip-flop circuits constituting a semiconductor circuit are extracted (S100).

Specifically, referring to FIG. 3, among the plurality of latch flip-flop circuits 20 to be formed on the semiconductor substrate 500 in the circuit design step, greatly affecting the timing yield of the entire circuit. In other words, a certain number of latch flip-flop circuits 30 having a slow operation speed may be extracted. For example, the latch flip-flop circuit 20 of the latch flip-flop circuit 20 constituting the semiconductor circuit through SSTA (Statistical Static Timing Analysis) using a cad tool has a certain number of latch flips in ascending order. It may be to extract the flop circuit (30).

Next, referring to FIG. 2, the extracted latch flip-flop circuit is replaced with the dual mode latch flip-flop circuit described above (S110).

Specifically, referring to FIG. 4, the STC replaces a predetermined number of latch flip-flop circuits (30 in FIG. 3) extracted in the highest order with the dual mode latch flip-flop circuit 10, and replaces each replaced dual mode latch flip-flop. The mode switch 400 of FIG. 10 and the voltage line 510 may be connected through the e-fuse 520.

Next, referring to FIG. 2, the mode of the replaced dual-mode latch flip-flop circuit is converted into the fast mode (S120).

Specifically, referring to FIG. 5, the timing yield is measured using a semiconductor circuit including the replaced dual-mode latch flip-flop circuit 10, and if some of the dual-mode latch flip-flop circuits 10 have a timing fail, If so, the mode of the corresponding dual mode latch flip-flop circuit 10 is converted to the fast mode.

At this time, the mode of the dual mode latch flip-flop circuit 10 in which the timing failure occurs is converted to the fast mode in a state in which the voltage line 510 and the dual mode latch flip-flop circuit 10 are connected through the fuse 520. It may be left as. That is, the dual mode latch flip-flop circuit 10 in which the timing fail has occurred is supplied with the power voltage VCC to the mode switch 400 of FIG. 1 through the fuse 520 to operate in the fast mode, and the timing fail The non-occurring dual-mode latch flip-flop circuit 10 may cut the fuse 520 connected to the voltage line 510 to operate in the normal mode.

When the semiconductor circuit is configured in this manner, the latch flip-flop circuit 30 that adversely affects the timing yield is replaced by the dual mode latch flip-flop circuit 10, and the replaced dual mode latch flip-flop circuit 10 also fails again. In this case, only the dual mode latch flip-flop circuit 10 in which the timing failure occurs is operated in the fast mode, so that the timing yield of the entire circuit can be improved at a low cost.

That is, the semiconductor circuit including the dual mode latch flip-flop circuit 10 having improved timing yield may include a voltage line 510, a plurality of dual mode latch flip-flop circuits 10, and respective dual mode latch flip-flop circuits as shown in FIG. 5. A plurality of fuses 520 disposed between each mode switch 400 of FIG. 10 and the voltage line 510 may be included. In addition, some of the plurality of fuses 520 may be cut to operate the dual mode latch flip-flop circuit 10 in normal mode.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

1 is a circuit diagram of a dual mode latch flip-flop circuit according to an embodiment of the present invention.

2 is a flowchart illustrating a method of improving yield of a semiconductor circuit in accordance with an embodiment of the present invention.

3 and 4 are intermediate steps for explaining a method of improving yield of a semiconductor circuit according to an embodiment of the present invention.

5 is a diagram for describing a semiconductor circuit according to an exemplary embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

10: dual-mode latch flip-flop circuit 100: clock delay circuit

200: NAND gate circuit 300: latch circuit

400: mode switch

S100-S120: Method for Improving Timing Yield of Semiconductor Circuits

Claims (12)

A clock delay circuit receiving a clock signal and delaying the clock signal to output a delayed clock signal; A NAND gate circuit receiving the clock signal, the delayed clock signal, and a data signal to perform a NAND operation to output a NAND output signal; A latch circuit configured to receive the NAND output signal, the clock signal, and the delayed clock signal to store the data signal; And A mode switch having one end connected to the NAND gate circuit and the latch circuit, And at least one of the NAND gate circuit and the latch circuit is variable in operation speed according to an output signal of the mode switch. The method of claim 1, The NAND gate circuit includes a first PMOS transistor and a first to third NMOS transistors connected in series between a voltage terminal provided with a power supply voltage and a ground terminal, and a second PMOS transistor and a fourth connected in series between the voltage terminal and the mode switch. To sixth NMOS transistors, The threshold voltage of the fourth to sixth NMOS transistors is lower than the threshold voltage of the first to third NMOS transistors. 3. The method of claim 2, The latch circuit may include a third PMOS transistor connected in series between the voltage terminal and the ground terminal, and a tenth through twelfth NMOS connected in series between one end of the third PMOS transistor and the mode switch and the seventh through ninth NMOS transistors. Including transistors, The threshold voltage of the tenth to twelfth NMOS transistors is lower than the threshold voltage of the seventh to ninth NMOS transistors. The method of claim 3, The mode switch comprises a mode switch transistor, Wherein one end of the mode switch transistor is connected to one end of the sixth and twelfth NMOS transistors, the other end is connected to the ground terminal, and a mode signal is provided to a gate end of the mode switch transistor. The method of claim 3, The mode switch is provided with a mode signal, The mode signal includes a normal mode signal and a fast mode signal, The fourth to sixth NMOS transistors and the tenth to twelfth NMOS transistors are disabled when the mode signal is the normal mode signal, and the fourth to sixth NMOS transistors and tenth when the mode signal is the fast mode signal. And the twelfth NMOS transistor is enabled. The method of claim 3, Widths of the fourth to sixth NMOS transistors are smaller than widths of the first to third NMOS transistors, And a width of the tenth to twelfth NMOS transistors is smaller than a width of the seventh to ninth NMOS transistors. Voltage line; A dual mode latch flip-flop circuit of any one of the preceding claims; And And a plurality of fuses disposed between the respective mode switches and the voltage lines of the respective dual mode latch flip-flop circuits. The method of claim 7, wherein And at least one of the plurality of fuses is cut off. Extracting a predetermined number of latch flip-flop circuits affecting timing yield of the semiconductor circuits among a plurality of latch flip-flop circuits constituting the semiconductor circuit, Replacing the extracted latch flip-flop circuit with the dual mode latch flip-flop circuit of any one of claims 1 to 6, And converting a mode of the replaced dual-mode latch flip-flop circuit to a fast mode. The method of claim 9, Extracting a predetermined number of latch flip-flop circuits affecting the timing yield of the semiconductor circuit is performed by the predetermined number of latch flip-flops in the order of higher Statistical Static Timing Criticality (SSTC) among the latch flip-flop circuits constituting the semiconductor circuit. A method for improving the timing yield of a semiconductor circuit comprising extracting the circuit. The method of claim 9, Converting the mode of the replaced dual-mode latch flip-flop circuit to the fast mode includes converting the mode of the replaced dual-mode latch flip-flop circuit to the fast mode using e-fuse. Method for improving timing yield of semiconductor circuits. The method of claim 9, Converting the mode of the replaced dual-mode latch flip-flop circuit to the fast mode converts the mode of the dual-mode latch flip-flop circuit into a fast mode in which a timing fail occurs. A method for improving the timing yield of semiconductor circuits, the method comprising.

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