KR101068497B1 - Non volatile memory device and Method of programming thereof - Google Patents

Abstract

The present invention relates to a nonvolatile memory device and a program method thereof, and includes a plurality of bit lines connected to a plurality of memory cells, and a plurality of page buffers connected to the plurality of bit lines, respectively, A bit line connection unit connecting a sensing node and the bit line, first and second latches for temporarily storing program data, and controlling the bit line to a program inhibit potential according to the program data stored in the first latch. A nonvolatile memory device including a first potential controller and a second potential controller for controlling the bit line to a program potential according to the program data stored in the second latch are disclosed.

Capacitance, Threshold Voltage, Bit Line

Description

Non-volatile memory device and method of programming thereof

The present invention relates to a nonvolatile memory device and a program method thereof, and more particularly, to a nonvolatile memory device and a program method thereof capable of suppressing a change in threshold voltage distribution according to a program state of a memory cell of an adjacent bit line.

Semiconductor memory devices, such as DRAM (Dynamic Random Access Memory), are volatile and lose their data over time, and have a random access memory (RAM) product that provides fast data input and output. It can be classified as sustainable non volatile.

Among such nonvolatile memories, there is an increasing demand for flash memory that can electrically input and output data. Flash memory is a device that can be electrically erased at high speed without removing the circuit from the board. The memory cell structure is simple, so the manufacturing cost per unit memory is low and the refresh function for data preservation is unnecessary. There is this.

Flash memory is largely classified into NOR and NAND types, which require one contact per two cells and are disadvantageous for high integration, but are advantageous for high speed due to large cell current. The NAND type has a low cell current, which is disadvantageous for high speed, but has a merit in that a plurality of cells share one contact, which is advantageous for high integration. Accordingly, NAND flash memory devices are in the spotlight as the next generation memory devices due to the rapid increase in the use of digital devices such as MP3, digital cameras, mobile and auxiliary storage devices.

The program operation of the nonvolatile memory device described above is as follows.

1 is a block diagram illustrating a cell array for explaining a program operation of a nonvolatile memory device according to the related art.

Referring to FIG. 1, conventionally, only a program operation of a memory cell connected to a selected bit line (eg, divided into an even bit line group and an odd bit line group) among a plurality of bit lines BL1 to BL3 is executed. This may cause a problem that the threshold voltage distribution is changed according to the interference effect between adjacent bit lines. Because of this, recently, the All Bit-Line (ABL) programming method is used in which all bit lines are simultaneously programmed without distinguishing between even and odd bit lines.

This is set after the plurality of bit lines BL1 to BL3 are set to the ground power supply (Vss) level, the inhibit potential level (Vinhibit = Vcc), and the control potential level (Vm) for controlling the program speed according to the program data value. The program voltage is applied to the word line WL to simultaneously program the memory cells MC1, MC2, and MC3.

However, this program method causes the channel voltage to change from 0V to the boosting level when the integrated memory cell is programmed and the program verify operation passes. As a result, the coupling ratio of the corresponding memory cell changes, and the voltage of the floating gate increases by ΔV due to the influence of the channel voltage rising value of the adjacent memory cell. In addition, when both adjacent memory cells are programmed and the verification operation passes, the rising ΔV value is also doubled, which causes a problem of widening the threshold voltage distribution.

The technical problem to be achieved by the present invention is to compensate the bit line potential by first setting the bit line according to the program data value during the program operation, and secondly setting the bit line using the capacitor value by the potential of the adjacent bit line. Accordingly, the present invention provides a nonvolatile memory device and a method of programming the same, which maintain and program a threshold voltage distribution.

A nonvolatile memory device according to an embodiment of the present invention includes a plurality of bit lines to which a plurality of memory cells are connected, and a plurality of page buffers respectively connected to the plurality of bit lines, wherein each of the plurality of page buffers is a sensing node. And a bit line connection unit for connecting the bit line, first and second latches for temporarily storing program data, and a first potential for controlling the bit line to a program prohibition potential according to the program data stored in the first latch. And a second potential controller configured to control the bit line to a program potential according to the program data stored in the second latch.

The plurality of bit lines are selected in a random manner or divided into even or odd groups during a program operation.

The first potential controller is connected between the sensing node and a power supply terminal, and converts the potential of the bit line through the sense node to a potential of the power supply terminal in response to program data stored in the first latch. To control.

The second potential controller is connected between the sensing node and the second latch, and changes the potential of the bit line to the program potential according to a value of the program data stored in the second latch, wherein the program potential is a ground power supply level or Control potential level.

The control potential level is between a ground power supply level and the program inhibited potential level.

Unselected bit lines of the plurality of bit lines are precharged to the program prohibition potential with the selected bit lines floated, thereby raising the potential of the selected bit lines by a capacitor effect.

The page buffers connected to the unselected bit lines precharge the unselected bit lines to the program inhibit potential using the first potential controller.

The selected bit lines disable and float the bit line connection of the page buffer connected when the unselected bit lines are precharged to the program inhibit potential.

According to an aspect of the present invention, there is provided a nonvolatile memory device including a plurality of bit lines connected to a plurality of memory cells and a plurality of page buffers connected to the plurality of bit lines, respectively. Selecting a bit line to be programmed among the plurality of bit lines, inputting program data into the page buffer connected to the selected bit lines, and applying potentials of the selected bit lines according to the program data. And precharging unselected bit lines of the plurality of bit lines to a program inhibit level, and programming a memory cell connected to the selected bit line by applying a program voltage to a word line.

After plotting the selected bit line, applying a program voltage to a word line to program a memory cell connected to the selected bit line.

The floated selected bit line rises in potential due to a capacitor effect with the unselected bit lines.

Controlling the potential of the selected bit lines according to the program data controls the selected bit lines to a program prohibition level, ground power level, or control voltage level according to the program data value.

According to an embodiment of the present invention, a bit line is first set according to a program data value during a program operation, and a bit line is secondly set by using a capacitor value by a potential of an adjacent bit line, thereby changing the potential of the bit line. The present invention provides a nonvolatile memory device capable of compensating and maintaining a constant threshold voltage distribution, and a program method thereof.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below, but to those skilled in the art It is preferred that the present invention be interpreted as being provided to more fully explain the present invention.

2 is a block diagram illustrating a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 2, the nonvolatile memory device 100 includes a memory cell array 110 and a page buffer unit 120.

The memory cell array 110 includes a plurality of bit lines BLn-1, BLn, and BLn + 1, and each of the plurality of bit lines BLn-1, BLn, and BLn + 1 has a plurality of memory cells. It is connected in series.

The page buffer unit 120 includes page buffers PBn-1, PBn, and PBn + 1 corresponding to the plurality of bit lines BLn-1, BLn, and BLn + 1, respectively. The page buffers PBn-1, PBn, and PBn + 1 control the potential of the plurality of bit lines BLn-1, BLn, and BLn + 1 according to program data values.

FIG. 3 is a detailed circuit diagram of the page buffer shown in FIG. 2. Since multiple page buffers have the same structure, one page buffer will be described by way of example.

Referring to FIG. 3, the page buffer (eg, BLn) includes a bit line connection unit 121 connecting the sensing node SO and the bit line BLn, a precharge unit 122 precharging the sensing node SO, A first latch 123 for storing first program data, a second latch 124 for storing second program data according to a verify operation during a program operation, and a potential of a bit line BLn connected to the sensing node SO; The sensing unit 125 for sensing, the first potential controller 126 for controlling the potential of the sensing node SO according to the first program data, and the bit line BLn connected to the sensing node SO according to the second program data. And a second potential controller 127 for controlling the potential of.

The bit line connector 121 includes NMOS transistors NM1 and NM2. The NMOS transistors NM1 and NM2 connect the bit line BLn and the sensing node SO in response to the bit line selection signal SELBL and the sensing signal PBSENSE, respectively.

The precharge unit 122 includes a PMOS transistor PM1. The PMOS transistor PM1 applies the power supply voltage Vcc to the sensing node SO in response to the precharge signal PREXHb to precharge the sensing node SO to a high level.

The first latch 123 includes inverters IV1 and IV2 and NMOS transistors NM3 and NM4. The inverters IV1 and IV2 are connected in reverse parallel between the first node QM and the second node QM_N to form a latch for temporarily storing data. The NMOS transistors NM3 and NM4 are connected between the first node QM and the input node A, the second node QM_N, and the input node A, respectively. The NMOS transistor NM3 connects the input node A and the first node QM in response to the initialization signal MRST, and the NMOS transistor NM4 is connected to the input node A in response to the set signal MSET. The second node QM_N is connected.

Second latch 124 includes inverters IV3 and IV4 and NMOS transistors NM5 and NM6. The inverters IV3 and IV4 are connected in reverse parallel between the third node QT and the second node QT_N to form a latch for temporarily storing data. The NMOS transistors NM5 and NM6 are connected between the third node QT and the input node A, the fourth node QT_N and the input node A, respectively. The NMOS transistor NM5 connects the input node A and the third node QT in response to the initialization signal TRST, and the NMOS transistor NM6 is connected to the input node A in response to the set signal TSET. The fourth node QT_N is connected.

The sensing unit 125 includes an NMOS transistor NM7. The NMOS transistor NM7 connects the input node A and the ground power supply Vss in response to the potential of the sensing node SO.

The first potential controller 126 includes PMOS transistors PM2 and PM3. The PMOS transistors PM2 and PM3 are connected in series between the sensing node SO and the power supply terminal Vinh1. The PMOS transistor PM2 is turned on in response to the first transmission signal TRANMb, and the PMOS transistor PM3 is turned on or turned off in response to the potential of the first node QM of the first latch 123 to supply power. The potential of Vinh1 is transmitted to the bit line BLn through the sensing node SO.

The second potential controller 127 includes an NMOS transistor NM8. The NMOS transistor NM8 is connected between the sense node SO and the second node QT_N of the second latch 124 and connects the sense node SO according to the potential level of the second transmission signal TRANT. The potential to be transferred to the bit line BLn is controlled.

4 is a waveform diagram of a bit line potential for explaining a program operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.

A program operation method of a nonvolatile memory device according to an embodiment of the present invention will be described with reference to FIGS. 2 to 4 as follows.

First, a bit line (for example, BLn) to be programmed is selected among the plurality of bit lines BLn-1, BLn, and BLn + 1. In an embodiment of the present invention, the selection of one bit line among three bit lines is described as an example, but is not limited thereto. For example, a plurality of bit line groups among 1K bit lines may be selected in a random manner or divided into even or odd groups. In this case, it is preferable to set the selected bit line BLn and the adjacent bit line BLn + 1 or BLn-1 to be unselected.

Thereafter, the first program data is input to the page buffer PBn connected to the selected bit line BLn. This will be described in detail as follows.

First, the sensing node SO is precharged to the high level in response to the low level precharge signal PRECHb. In response to the high level of the sensing node SO, the NMOS transistor NM7 of the sensing unit 125 is turned on and the ground power source Vss is applied to the input node A. FIG. Thereafter, the initialization signal MRST is enabled to initialize the first node QM of the first latch 123 to a low level. In the same manner, the third node QT of the second latch 124 is initialized to a low level.

Thereafter, when the data value to be programmed is 1 (program inhibit cell, Case 1), the set signal MSET is maintained in a disabled state to maintain the first node QM of the first latch 123 at a low level. The first program data is input. When the data value to be programmed is 0 (program cell, Case 3), the set signal MSET is enabled to change the first node QM of the first latch 123 to a high level. In addition, the set signal TSET of the second latch 124 is enabled to set the fourth node QT_N to a low level.

In addition, in the case of using the double verify operation for different verify voltages during the program operation, when the first verify operation passes, the second program data is input to the second latch 124 (Case 2). This is the same as the input method of the first program data, but controls so that the potential of the fourth node QT_N is set to a high level. When the double verify operation passes the verify operation using the first verify voltage, the potential of the bit line is increased to slow down the program speed of the memory cell.

Thereafter, the potential of the selected bit line BLn is first set using the first program data stored in the first latch 123 and the second latch 124. (BL Set1) In detail, Same as

First, the bit line selection signal SELBL and the sensing signal PBSENSE are applied at a high level so that the bit line connection unit 121 connects the bit line BLn and the sensing node SO.

Thereafter, the first transmission signal TRANMb is applied to the first potential controller 126 at a low level, and the second transmission signal TRANT is applied at a level of Vm + Vt (Vt is a threshold voltage of NM8). As a result, when the data value to be programmed is 1 (Case 1), the program inhibit voltage Vinh1 is applied to the bit line BLn. In addition, when the data value to be programmed is 0 (Case 3), the PMOS transistor PM3 of the first potential controller 126 is turned off, and the NMOS transistor NM8 of the second potential controller 127 is the second transmission signal. It turns on in response to (TRANT, Vm + Vt) to discharge the potential of the bit line BLn to the ground power supply Vss level. Also, when the first verify operation is passed during the double verify operation, the PMOS transistor PM3 of the first potential controller 126 is turned off, and the NMOS transistor NM8 of the second potential controller 127 is transferred to the second. It is turned on in response to the signal TRANT, Vm + Vt. At this time, the fourth node QT_N of the second latch 124 maintains the high level, but the NMOS transistor NM8 controls the bit line BLn in response to the second transmission signal TRAT, Vm + Vt. Precharge to (Vm). The control potential level Vm is preferably between the ground power supply Vss and the program prohibition potential Vinh1.

Subsequently, the page buffer connected to the selected bit line BLn and the adjacent bit line (eg BLn + 1 or BLn-1) is controlled to adjust the potential of the adjacent bit line BLn + 1 or BLn-1. The control is performed and the potential of the selected bit line BLn is increased in accordance with the capacitor effect, thereby setting the secondary. (BL Set2) This will be described in detail below.

The first node QM of the first latch 123 of the page buffer connected to the adjacent bit line (eg, BLn + 1 or BLn-1) is initialized to a low level.

Thereafter, the bit line selection signal SELBL and the sensing signal PBSENSE are applied at a high level so that the bit line connection unit 121 connects the bit line BLn and the sensing node SO.

Thereafter, the first transmission signal TRANMb is applied at a low level, and the first potential controller 126 is applied to the program inhibit voltage Vinh1 to the bit lines BLn-1 or BLn + 1. In this case, the applied program inhibit voltage Vinh1 is preferably at the Vcc level. As a result, the selected bit line BLn and the adjacent bit line (eg, BLn + 1 or BLn-1) are precharged to the Vcc level.

When precharging the potential of the above-described adjacent bit line (eg BLn + 1 or BLn-1) to Vcc level, the page buffer PBn of the selected bit line BLn is selected by disabling the bit line connection 121. The bit line BLn is floated. As a result, the floating bit line BLn rises by ΔV in response to the potential of the adjacent bit line (for example, BLn + 1 or BLn-1). That is, the bit line potential is increased by ΔV to compensate for the voltage of the floating gate rising by ΔV due to the channel voltage rising value of the adjacent memory cell.

Thereafter, a program voltage is applied to a word line to simultaneously program a plurality of memory cells. In this case, the voltage of the floating gate is increased by ΔV due to the increase in the channel voltage of the adjacent memory cell by increasing the bit line potential by ΔV to maintain the threshold voltage distribution.

The present invention is not limited to the above-described embodiments, but may be implemented in various forms, and the above embodiments are intended to complete the disclosure of the present invention and to completely convey the scope of the invention to those skilled in the art. It is provided to inform you. Therefore, the scope of the present invention should be understood by the claims of the present application.

1 is a block diagram illustrating a cell array for explaining a program operation of a nonvolatile memory device according to the related art.

2 is a block diagram illustrating a nonvolatile memory device according to an embodiment of the present invention.

FIG. 3 is a detailed circuit diagram of the page buffer shown in FIG. 2.

4 is a waveform diagram of a bit line potential for explaining a program operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.

Description of the Related Art [0002]

110: memory cell array 120: page buffer unit

121: bit line connection 122: precharge unit

123: first latch 124: second latch

125: sensing unit 126: first potential controller

127: second potential controller

Claims (12)

A plurality of bit lines to which a plurality of memory cells are connected; A plurality of page buffers, each connected to the plurality of bit lines; Each of the plurality of page buffers A bit line connection unit connecting the sensing node and the bit line; First and second latches for temporarily storing program data; A first potential controller configured to control the bit line to a program inhibit potential according to the program data stored in the first latch; And A second potential controller configured to control the bit line to a program potential according to the program data stored in the second latch, And a bit line connection connected to the selected bit line is disabled when the non-selected bit lines adjacent to the selected bit line of the plurality of bit lines are precharged by the first potential controller to the program inhibited potential. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, The plurality of bit lines are selected in a random manner or divided into even or odd groups during a program operation. Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, The first potential controller is connected between the sensing node and a power supply terminal, and converts the potential of the bit line through the sense node to a potential of the power supply terminal in response to program data stored in the first latch. Nonvolatile memory device controlled by. Claim 4 was abandoned when the registration fee was paid. The method of claim 1, The second potential controller is connected between the sensing node and the second latch, and changes the potential of the bit line to the program potential according to the value of the program data stored in the second latch, wherein the program potential is a ground power supply level or A nonvolatile memory device having a control potential level. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 4, wherein And the control potential level is between a ground power supply level and the program inhibited potential level. Claim 6 was abandoned when the registration fee was paid. The method of claim 2, The non-selected bit lines of the plurality of bit lines are precharged to the program inhibit potential to raise the potential of the selected bit lines by a capacitor effect. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 6, And the page buffers connected to the non-selected bit lines precharge the non-selected bit lines to the program inhibit potential by using the first potential controller. delete Providing a nonvolatile memory device including a plurality of bit lines connected to a plurality of memory cells and a plurality of page buffers connected to the plurality of bit lines, respectively; Selecting bit lines to be programmed among the plurality of bit lines; Inputting program data into the page buffer connected to the selected bit lines; Controlling the potential of the selected bit lines in accordance with the program data; Precharging unselected bit lines of the plurality of bit lines to a program prohibition level; And And plotting the selected bit line. Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 9, After programming the selected bit line, applying a program voltage to a word line to program a memory cell connected to the selected bit line. Claim 11 was abandoned upon payment of a setup registration fee. 11. The method of claim 10, And the potential of the selected bit line being floated rises due to a capacitor effect with the non-selected bit lines. Claim 12 was abandoned upon payment of a registration fee. The method of claim 9, The controlling of the potential of the selected bit lines according to the program data may include controlling the selected bit lines to a program prohibition level, a ground power level, or a control voltage level according to the program data value.

Images