KR101064377B1 - Non-Volatile Memory of having Cell comprising Diode - Google Patents

Abstract

Disclosed is a structure of PoRAM, which is a nonvolatile memory using a conductive organic material as a resistance change layer. A row address decoder is provided to select a specific cell in the cell region. The column address decoder operates in a read operation to transfer data of the column line to the sense amplifier. In particular, each cell consists of a resistive change layer and a diode. The resistance change layer is formed based on the organic material defining the PoRAM, and is composed of a diode using a p-n junction under the resistance change layer.

PoRAM, nonvolatile memory, polymers,

Description

Non-Volatile Memory of Having Cell comprising Diode

The present invention relates to a nonvolatile memory, and more particularly, to a nonvolatile memory in which a conductive organic material exists between two electrodes, such as a polymer random access memory (PoRAM), thereby inducing a resistance change.

In addition to nonvolatile memory devices represented by conventional flash memory, research on next-generation memory devices is being actively conducted. In other words, technologies that use changes in resistance components, such as PoRAM, ReRAM, NFGM, and MRAM, in memory operations have been gradually developed. In particular, in the case of ReRAM, research on the resistance change material itself is being actively conducted, and in the case of PoRAM, researches on materials and devices based on the material are being conducted in parallel. Memories using the above-described change in resistance components are not completely identified mechanisms for fair control.

Korean Unexamined Patent Publication No. 2008-95761 discloses a nonvolatile memory device based on a PoRAM device and a method of manufacturing the same. The patent discloses various resistance states by providing a plurality of nanocrystals in a conductive organic layer in a PoRAM device. Through such a plurality of resistance states, a unit cell can store a multi-level data. However, in order to operate as the above-mentioned patent application as a memory device, a circuit capable of implementing an assignment of an address, activation of a specific cell according to the assignment of an address, and storage or reading of data for the activated specific cell must be implemented. That is, in a nonvolatile memory device based on PoRAM, not only the structure of a cell but also a driving circuit for driving the same and a mechanism for storing and reading data in one block should be described.

Also, it is known that the cell structure in a PoRAM using a conductive organic layer requires that the conductive organic material and the transistor be electrically coupled to induce a change in resistance. That is, a resistance change can be realized by supplying electric power to the conductive organic layer using a MOS transistor or the like, and in a storage state, a structure must be realized to prevent the resistance state from being changed by an external bias by turning off the transistor.

Implementing a transistor and a resistance change element in a manufacturing process should realize a transistor on a substrate, apply an interlayer insulating film, and then implement a resistance change element on the interlayer insulating film. Such a manufacturing process requires a number of microprocesses, and is a factor in reducing the memory density.

An object of the present invention for solving the above problems is to provide a structure of a PoRAM having a more efficient structure and capable of accurately operating a cell.

The present invention for achieving the above object is a cell region having a cell formed in the region where the row line and column line intersect; A row address decoder for selecting a specific row line in the cell region; A column address decoder for selecting a specific column line of the cell region; And a column line switching unit configured to perform an on / off operation under the control of the column address decoder to transmit an electrical signal transmitted from the column line to a sense amplifier, wherein the cell is electrically connected to the column line. Resistance change layer having a conductive organic material of low molecular or polymer; And a diode electrically connected between the resistance change layer and the row line.

The object of the present invention is a cell region having a cell formed in an area where a row line and a column line intersect; A row address decoder for selecting a specific row line in the cell region; A low line switching unit connected between the row address decoder and the cell area and controlling a signal transmitted to the cell area by a switching operation; A column address decoder for selecting a specific column line of the cell region; And a column line switching unit configured to perform an on / off operation under the control of the column address decoder to transmit an electrical signal transmitted from the column line to a sense amplifier, wherein the cell comprises: the column line formed on a substrate; A diode formed on the column line; A resistance change layer formed on the diode and having a low molecular or polymer conductive organic material; And it can also be achieved through the provision of a PoRAM characterized in that it comprises a row line formed on the resistance change layer.

According to the present invention described above, the cell is composed of a diode and a resistance change layer to implement a simple step in the manufacturing process. In addition, a plurality of switching elements are arranged around the cell region to implement electrical control of the cell region. Through the use of switching elements, interference between cells connected to adjacent column lines or row lines is minimized.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Like reference numerals are used for like elements in describing each drawing.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

Example

1 is a block diagram illustrating a PoRAM according to a preferred embodiment of the present invention.

Referring to FIG. 1, a PoRAM according to the present exemplary embodiment includes a cell region 100, a row address decoder 120, a column address decoder 140, and a column line switching unit 160.

The cell region 100 includes a plurality of nonvolatile memory cells, column lines 101, 102, and 103 and row lines 111, 112, 113, and 114 that cross-connect to the cells. That is, the column lines 101, 102, 103 are parallel to each other and are disposed at regular intervals from each other, and the row lines 111, 112, 113, and 114 are connected to the column lines 101, 102, 103 and the like. The cells have an intersecting shape, but cells are disposed in an area where the lines intersect.

Each cell has a diode and a resistive change layer. The cathode of the diode is connected to the column lines 101, 102, 103 and the anode of the diode is connected to the resistance change layer. In addition, one end of the resistance change layer is connected to the anode of the diode, the other end is connected to the low line. The resistance change layer is modeled as the circuit symbol R of the resistor in FIG.

The cell region 100 may further include a refresh unit 110. The refresh unit 110 is composed of a plurality of switching elements. In addition, the switching element of the refresh unit 110 is preferably composed of a transistor and is connected between the ground and the column lines 101, 102, 103 of the cell region 100. The transistors of the refresh unit 110 are turned on by the refresh control signal REFRESH to initialize the column lines 101, 102, and 103 of the cell region 100 to the ground level.

Row address decoder 120 is used to select a particular row line. That is, when address information of at least one cell to which a read operation is to be performed is input, a high level is supplied to a specific low line corresponding thereto. Therefore, the high level is supplied only to a specific low line that is the target of the read operation, the low level voltage is supplied to the remaining low lines, or the floating state is established.

In addition, the row line switching unit 130 may be further provided between the row address decoder 120 and the cell region 100 for a more clear operation. That is, switching elements are provided between the output terminal of the row address decoder 120 and the row lines 111, 112, 113, and 114 of the cell region 100, so that the row address decoder 120 and the row lines 111, 112 are provided. , 113, 114 may control the electrical connection between. When the low line switching unit 130 is provided, a specific transistor connected to the selected low line is turned on, and the transistors connected to the remaining low lines are turned off. Thus, unselected row lines are floated.

The switching signals SW_0 to SW_M for controlling the switching operation of the low line switching unit 130 may be supplied by a separate controller, and may be generated and supplied by the row address decoder 120.

The column address decoder 140 outputs column line selection signals COL_0, COL_1, ..., COL_N for selecting a specific column line. The output column line selection signals COL_0, COL_1,..., And COL_N are applied to the column line switching unit 160.

The column line switching unit 160 is disposed between the cell region 100 and the sensing amplifier 180. That is, the column line switching unit 160 is disposed between the column lines 101, 102, and 103 and the sense amplifier 180, and the sense amplifiers constituting the sense amplifier 180 are each column line 101. 102, 103). The column line switching unit 160 includes a plurality of switching elements, and the switching elements are turned on / off by the column line selection signals COL_0, COL_1,..., COL_N which are output signals of the column address decoder 140. do.

If a read operation is to be performed on information about a specific cell in the cell region 100 in which data is stored, the row address decoder 120 selects and activates a row line corresponding to the specific cell. For example, when the read cell 115 connected to the second row line 112 is to be selected, the row address decoder 120 supplies a high level to the second row line 112. If the low line switching unit 130 is further provided, the switching control signal SW_1 is activated so that the transistor to which the switching control signal SW_1 is supplied is turned on and the high level signal is supplied to the second low line 112. . The voltage supplied to the second row line 112 is supplied to the read cell 115, and a current corresponding to the resistance state of the transition change layer determined in the read cell 115 flows to the second column line 102.

Subsequently, the transistor of the column line switching unit 160 is turned on / off by the operation of the column address decoder 140. That is, the read current flowing to the second column line 102 is input to the sense amplifier by the column line selection signal COL_1 by the turn-on operation of the corresponding transistor.

The sensing amplifier senses a read current flowing through the second column line 102, converts it to a voltage, amplifies it, and outputs it in the form of a data signal DATA_1.

In the above-described PoRAM configuration, each cell is composed of a resistance change layer and a diode connected in series thereto. Therefore, there is no need for a transistor to induce a change in resistance of the resistance change layer and to control the flow of current according to the resistance value, thereby having the advantage of enabling many cells in a small area.

In addition, the refresh unit 110 may be provided to solve the problem of malfunction occurring in the write and read operation of data by reflashing the cell before the write operation or the read operation.

In addition, row lines that are not selected by the selectively configured low line switching unit 130 may be floated to minimize a malfunction that may occur in a read operation.

2 is another block diagram illustrating a PoRAM according to a preferred embodiment of the present invention.

Referring to FIG. 2, a cell structure, a column line, a row line, a row address decoder 220, a column address decoder 240, and a column line switching unit 260 of the cell region 200 are illustrated in FIG. 1. same. Therefore, in order to avoid duplicate descriptions and to minimize confusion of understanding due to excessive descriptions, descriptions of the same elements will be omitted.

In FIG. 2, the cell region 200 further includes a column line charge / discharge unit 210.

The column line charging and discharging unit 210 includes a column line charging unit 211 and a column line discharge unit 213. In addition, the column line charge / discharge unit 210 is formed in a plurality of series structures in which source / drain stages of two transistors are connected.

When the column line charging signals Cen1 to CenN are applied, the transistors of the column line charging unit 211 are turned on, and a power supply voltage Vpp is supplied to each column line.

In addition, when the column line discharge signals DCen1 to DCenN are applied, the transistors of the column line discharge unit 213 are turned on, and the column line is initialized to the ground level.

For example, when the erase operation is performed on the cells of the cell region 200, the column line discharge signals DCen1 to DCenN are activated to perform a smooth erase operation when an erase voltage is applied to the cells through the low line. In addition, the column line charging signals Cen1 to CenN set the column line to a specific voltage before the write operation to the cell, thereby minimizing an error during the write operation. However, the column line filling unit 211 may be omitted according to aspects of the use of those skilled in the art.

The low line switching unit 230 is disposed between the row address decoder 220 and the row lines of the cell region 200. The normally low line switching unit 230 controls various signals supplied to the low line through a switching operation.

The low line switching unit 230 further includes a low line discharge unit 235. The low line discharge part 235 is composed of transistors interposed between the low line and the ground level. When the low line discharge signals RowDis1 to RowDisM are activated, the transistors of the low line discharge unit 235 are turned on, and the low line is initialized to the ground level. The low line discharge unit 235 may initialize the low line to a stable ground level before the erase operation or the write operation with respect to the cell, thereby minimizing a malfunction due to the unexpected residual of the impedance.

An R / W / E driver 225 is connected to the low line switching unit 230. The R / W / E driver 225 receives a write command, a read command, and an erase command. For example, when a write command is activated, the R / W / E driver 225 generates a write voltage and supplies it to the low line switching unit 230. In this case, the row address decoder 220 may be deactivated. When the erase command is activated, the R / W / E driver 225 supplies an erase voltage to the low line switching unit 230 and performs an erase operation on the cell. In addition, when the read command is activated, the R / W / E driver 225 does not generate a specific voltage, and the row address decoder 220 is activated. Therefore, a read voltage is supplied from the row address decoder 220, and a read operation for a specific cell is performed.

3 is a cross-sectional view illustrating the cell structure shown in FIGS. 1 and 2 according to a preferred embodiment of the present invention. However, since the cell structure illustrated in FIG. 3 corresponds to an example of the implementation of the resistance change layer and the diode, it will be apparent to those skilled in the art that the cell structure may vary according to other various embodiments.

Referring to FIG. 3, a column line 310 is provided on the substrate 300. The column line 310 illustrated in FIG. 3 refers to one of the plurality of column lines illustrated in FIGS. 1 and 2.

The column line 310 may be any material having a predetermined conductivity, but when the substrate 300 is silicon, the column line 310 is preferably a region heavily doped with n +. In addition, the column line 310 may be implemented through a predetermined ion implantation process on the substrate 300, and may also be implemented by an epitaxial growth method. In addition, the column line 310 may be made of metal. When the column line 310 is made of metal, an insulating film may be additionally interposed between the silicon substrate 300 and the column line 310.

The diode 320 is provided on the column line 310. The diode 320 is formed using a p-n junction. First, an n-type semiconductor layer 321 is formed on the column line 310. The n-type semiconductor layer 321 may be formed by deposition or epitaxial growth. Subsequently, the p-type semiconductor layer 323 is formed on the n-type semiconductor layer 321. The diode 320 is implemented by forming the n-type semiconductor layer 321 and the p-type semiconductor layer 323.

In addition, an interlayer insulating layer 325 is formed on both sides of the n-type semiconductor layer 321 and the p-type semiconductor layer 323 constituting the diode 320. The interlayer insulating layer 325 electrically insulates diodes of neighboring cells.

The resistance change layer 340 is provided on the p-type semiconductor layer 323. The electrical contact layer 330 may be selectively interposed according to the material of the material constituting the resistance change layer 340. The electrical contact layer 330 is selected from conductive materials, but preferably selected from a metal material such as Al.

The resistance change layer 330 is a core stacked structure constituting the PoRAM, and may take the structure of a conductive low molecule / intermediate metal layer / conductive low molecule and, if necessary, may be composed of a nano metal particle layer interposed between conductive polymers. have. For example, when the resistance change layer 330 is composed of a conductive low molecule / intermediate metal layer / conductive low molecule, it is preferably composed of AIDCN (2-amino-4, 5-imidazoledicarbonitrile) / Al / AIDCN. In addition, when the resistance change layer 230 is composed of a nano metal particle layer interposed between the conductive polymer, it may be configured in the form of metal nanoparticles interposed between PVK (poly (N-vinylcarbazole)).

As described above, the resistance change layer 330 may be implemented through various forms, but any material may be applicable as long as the resistance change is induced by the interlayer combination of the conductive polymer and the metal.

The row line 350 is disposed on the resistance change layer 340. It will be apparent to those skilled in the art that the low line 350 may be implemented with a conductive metal material.

4 to 6 are cross-sectional views illustrating a method of forming the cell structure shown in FIG. 2 according to a preferred embodiment of the present invention.

Referring to FIG. 4, a column line 310 is formed on the substrate 300. The column line 310 may be formed of a metal or a highly doped n + type semiconductor layer as a conductive material. That is, a metallic line may be formed on the substrate 300 through deposition or the like, and may be formed of an n + type semiconductor layer doped at high concentration by ion implantation or epitaxial growth.

Referring to FIG. 5, a diode 320 is formed on the column line 310. The diode 320 has a structure in which an n-type semiconductor layer 321 and a p-type semiconductor layer 323 are stacked. First, the n-type semiconductor layer 321 and the p-type semiconductor layer 323 are sequentially stacked on the column line 310. A photoresist pattern (not shown) is then formed which opens the region where the interlayer insulating film 325 is formed using a conventional lithography process.

When the etching process is continued, the region where the interlayer insulating layer 325 is to be formed is opened to expose the lower column line 310. If the column line 310 is formed of an n + region, the n-type semiconductor layer 321 is preferably doped with n− for smooth etching according to an etching selectivity.

Subsequently, an insulating material is embedded in the exposed region to form the interlayer insulating film 325. The interlayer insulating film 325 may be any material used in a semiconductor process. That is, an interlayer insulating film 325 is formed by applying an insulating film such as TEOS. If the interlayer insulating film 325 is applied to the upper portion of the n-type semiconductor layer 321 and the p-type semiconductor layer 323, it is preferable to expose the upper portion of the p-type semiconductor layer 323 using chemical mechanical polishing.

Referring to FIG. 6, a resistance change layer 340 is formed on the formed diode 320.

In addition, before the resistance change layer 340 is formed, an electrical contact layer 330 may be formed on the diode 320. The electrical contact layer 330 may be any conductive material, but is preferably made of a metal material. In addition, the metal material used in the electrical contact layer 330 may be Al, W, Ti or alloys thereof. The electrical contact layer 330 is used to facilitate electrical contact between the upper resistance change layer 340 and the lower diode 320. That is, the mismatch between the interface between the p-type semiconductor layer 323 and the interface between the resistance change layer 340 and the unexpected change in physical properties thereof are minimized, and the resistance change layer 340 and the p-type semiconductor layer based on the organic material are substantially minimized. 323 is interposed to achieve ohmic contact in the macro sense.

The resistance change layer 340 is formed on the diode 320 or on the electrical contact layer 330. The resistance change layer 340 is implemented in a low molecular form or a polymer form.

When the low molecular resistance change layer is formed, the resistance change layer 340 may be formed of a conductive low molecular layer and an intermediate metal layer. The conductive low molecular weight layer may be composed of AIDCN, and the intermediate metal layer may be formed of Al. In addition, it may be formed in-situ using evaporation using a shadow mask. Therefore, the low molecular resistance change layer 340 is formed in the form of the intermediate metal layer interposed in the conductive low molecular layer. In addition, the intermediate metal layer may be configured in the form of nanocrystalline particles or an amorphous layer.

When the resistance change layer in the form of a polymer is formed, for example, PVK, which is a conductive polymer, is used, and an intermediate metal layer is interposed in the conductive polymer. First, the low conductivity polymer is formed in a lift-off manner. The lift-off method is to apply the photoresist, open the diode region through normal patterning, and then embed the conductive polymer in the open region. The patterned photoresist is then removed through ashing.

Subsequently, an intermediate metal layer is deposited on the preformed conductive polymer layer, and then an intermediate metal layer is formed through heat treatment. The intermediate metal layer is preferably formed in the form of nanocrystalline particles. In addition, the metal used becomes Au etc.

Subsequently, when the conductive polymer layer is formed on the intermediate metal layer by the method described above, a resistance change layer in a polymer form is formed.

A low line is formed on the resistance change layer. The row line may be any conductive material, but is preferably formed of a metal material. In addition, the formation of the low line of the metal material may damage the lower resistance change layer when using a conventional deposition, patterning and etching process using a photoresist. Therefore, it is preferable to use an evaporation process using a shadow mask or a technique of forming a metal pattern at low temperature using a lift-off process.

As described above, the present invention implements a simple step in the manufacturing process by configuring a cell with a diode and a resistance change layer. In addition, a plurality of switching elements are arranged around the cell region to implement electrical control of the cell region. Through the use of switching elements, interference between cells connected to adjacent column lines or row lines is minimized.

1 is a block diagram illustrating a PoRAM according to a preferred embodiment of the present invention.

2 is another block diagram illustrating a PoRAM according to a preferred embodiment of the present invention.

3 is a cross-sectional view showing the cell structure shown in FIG. 1 according to a preferred embodiment of the present invention.

4 to 6 are cross-sectional views illustrating a method of forming the cell structure shown in FIG. 2 according to a preferred embodiment of the present invention.

Claims (12)

delete delete delete delete delete delete A cell region having a cell formed in an area where a row line and a column line intersect, and a column line charge / discharge unit for setting the column line to a power supply voltage Vpp or initializing to a ground level; A row address decoder for selecting a specific row line in the cell region; A low line switching unit connected between the row address decoder and the cell area and controlling a signal transmitted to the cell area by a switching operation; A column address decoder for selecting a specific column line of the cell region; And A column line switching unit configured to perform an on / off operation under the control of the column address decoder to transfer an electrical signal transmitted from the column line to a sense amplifier, The cell, The column line formed on the substrate; A diode formed on the column line; A resistance change layer formed on the diode and having a low molecular or polymer conductive organic material; And A row line formed on the resistance change layer; Wherein each diode is separated by an adjacent diode and an interlayer insulating film. The method of claim 7, wherein the resistance change layer is composed of AIDCN (2-amino-4,5-imidazoledicarbonitrile) / Al / AIDCN, or metal nanoparticles interposed between PVK (poly (N-vinylcarbazole)). PoRAM which is configured. The method of claim 7, wherein the column line charging and discharging unit, A column line charger including a plurality of transistors and configured to supply the pseudo power supply voltage Vpp to the column line in a switching operation; And And a column line discharge unit configured to supply transistors connected in series to transistors of the column line charging unit, respectively, for supplying and initializing the ground level to the column line by a switching operation. The PoRAM of claim 7, wherein the low line switching unit further comprises a low line discharge unit including transistors interposed between the low line and the ground level. The method of claim 7, wherein the diode, An n-type semiconductor layer formed on the row line; And A p-type semiconductor layer formed on the n-type semiconductor layer. 8. The PoRAM of claim 7, wherein a conductive electrical contact layer is interposed between the diode and the resistance change layer.

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