KR101052930B1 - Buried gate of semiconductor device and fabricating method for the same - Google Patents
Buried gate of semiconductor device and fabricating method for the same Download PDFInfo
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- KR101052930B1 KR101052930B1 KR1020100063062A KR20100063062A KR101052930B1 KR 101052930 B1 KR101052930 B1 KR 101052930B1 KR 1020100063062 A KR1020100063062 A KR 1020100063062A KR 20100063062 A KR20100063062 A KR 20100063062A KR 101052930 B1 KR101052930 B1 KR 101052930B1
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- South Korea
- Prior art keywords
- titanium nitride
- nitride layer
- gate
- layer
- semiconductor device
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 44
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 109
- 239000000460 chlorine Substances 0.000 claims abstract description 62
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims abstract description 49
- 229910052801 chlorine Inorganic materials 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 13
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 40
- 238000000151 deposition Methods 0.000 claims description 36
- XJDNKRIXUMDJCW-UHFFFAOYSA-J titanium tetrachloride Chemical compound Cl[Ti](Cl)(Cl)Cl XJDNKRIXUMDJCW-UHFFFAOYSA-J 0.000 claims description 22
- 229910021529 ammonia Inorganic materials 0.000 claims description 20
- 238000005121 nitriding Methods 0.000 claims description 6
- 238000001179 sorption measurement Methods 0.000 claims description 5
- 238000011065 in-situ storage Methods 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract 3
- 230000008021 deposition Effects 0.000 description 18
- 238000005530 etching Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 1
- 229910018503 SF6 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000003416 augmentation Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor device technology, and more particularly, to a buried gate (BG) and a method of forming improved reliability.
As the degree of integration of semiconductor devices increases, design rules of circuit patterns are also rapidly decreasing. As memory semiconductor devices such as DRAM devices reduce design rules to 40 nm or less, efforts have been made to improve the structure of transistors constituting memory cells. A cell transistor employing a recess gate or a fin gate structure has become difficult to implement a semiconductor device of 40 nm or less, so that a buried gate buried a gate in an active region of a semiconductor substrate. I'm trying to apply it. Such a buried gate is expected to be effectively applied to a 30 nm class memory semiconductor device.
It is expected that a semiconductor device employing a transistor employing a buried gate can realize an effect of suppressing parasitic capacitance between a gate and a bit line disposed above the transistor due to the structural characteristics of the buried gate. . The reduction of parasitic capacitance can induce an effect of securing a larger sensing margin of the bit line, thereby overcoming the problem of greatly increasing the capacitance of the cell capacitor to secure the sensing margin.
Since the buried gate is to be buried in the active region, plasma induced damage (PID) may be caused to the gate dielectric layer during the formation thereof. After depositing the conductive layer for the buried gate, in the process of etching the conductive layer, the gate dielectric layer formed under the conductive layer may be attacked and damaged by the plasma introduced during the etching. Such damage to the gate dielectric layer eventually degrades the operation reliability of the cell transistors constituting the memory cell of the DRAM, and thus, the refresh time of the DRAM element can be drastically reduced. Accordingly, there is a need for development of a method for suppressing the plasma damage caused in the lower gate dielectric layer when the conductive layer is etched to bury the buried gate in the gate trench.
An object of the present invention is to provide a buried gate and a method of forming a semiconductor device capable of suppressing damage to a gate dielectric layer and improving reliability.
One aspect of the invention, forming a gate trench in the semiconductor substrate; Depositing a first titanium nitride (TiN) layer containing a relatively low concentration of residual chlorine (Cl) on the gate trench surface; Depositing a second titanium nitride layer containing a relatively high concentration of residual chlorine on the first titanium nitride layer to form a gate conductive layer; And it provides a method of forming a buried gate of a semiconductor device comprising the step of recessing the gate conductive layer.
Another aspect of the invention, the semiconductor substrate with a gate trench formed; A first titanium nitride (TiN) layer containing relatively low concentration of residual chlorine (Cl) deposited on the gate trench surface; And a second titanium nitride layer deposited on the first titanium nitride layer to contain a relatively high concentration of residual chlorine.
The first titanium nitride layer may be deposited to contain the residual chlorine at a low concentration within 0.2%.
The second titanium nitride layer may be deposited to contain a high concentration of the residual chlorine greater than 0.4% and within 0.9%.
Depositing the first and second titanium nitride layers
An adsorption step of providing titanium tetrachloride; Nitriding by providing ammonia on the adsorbed titanium tetrachloride; And repeating the adsorption step and the nitriding step, wherein the supply flow rate ratio of the ammonia to the titanium tetrachloride in the deposition of the first titanium nitride layer is smaller than in the deposition of the second titanium nitride layer. Thus, the residual chlorine content in the first titanium nitride layer can be induced to a relatively low concentration.
According to the present invention, it is possible to provide a buried gate and a formation method capable of suppressing damage caused by plasma to the gate dielectric layer and improving reliability. In addition, since the buried gate is made of titanium nitride (TiN), it is possible to exclude heterogeneous interfaces in the buried gate, thereby reducing the resistance Rs of the buried gate line. Accordingly, the write recovery time (tWR) of a memory device such as a DRAM may be improved. In addition, since the buried gate is formed of a single TiN material, it is possible to simplify the deposition process when forming the buried gate. In addition, by controlling the chlorine (Cl) residual concentration in the TiN layer differently, it is possible to effectively suppress the phenomenon that the TiN layer is excited at the interface between the gate dielectric layer and the TiN layer. Accordingly, the reliability of the TiN buried gate can be improved.
1 to 5 are cross-sectional views illustrating a buried gate and a forming method according to an embodiment of the present invention.
6 to 9 are cross-sectional photographs provided to explain the effect of the buried gate and the formation method according to an embodiment of the present invention.
According to an embodiment of the present invention, when a buried gate is formed by depositing a titanium nitride single material, the titanium nitride is a deposition process using a titanium source containing chlorine (Cl) such as titanium tetrachloride (TiCl 4 ) and ammonia (NH 3 ). Deposit a layer. At this time, when performing the deposition process by varying the chlorine (Cl) concentration remaining in the titanium nitride layer, a first titanium nitride layer containing a relatively low concentration of chlorine is deposited on the bottom, and on the first titanium nitride layer By depositing a second titanium nitride layer containing a relatively high concentration of residual chlorine, the phenomenon that the interface between the gate dielectric layer and the titanium nitride layer is lifted can be effectively suppressed.
Referring to FIG. 1, a
After the
Referring to FIG. 2, a first titanium nitride (TiN)
The first
The first
When the first
The first
FIG. 8 is a photograph showing a profile after a thermal process when the
Referring back to FIG. 2, after depositing the first
The deposition rate of titanium nitride can be realized by increasing the feed flow rate ratio of ammonia to titanium tetrachloride. For example, at a deposition temperature of 670 ° C., the second titanium nitride layer is repeated by repeatedly supplying titanium tetrachloride at a supply flow rate of approximately 60 sccm and supplying ammonia three times at a supply flow rate of 180 sccm for 8 seconds. 230 is deposited to a thickness of approximately 300 kV to 800 kV. As the deposited layer is deposited relatively thick and nitrided, the deposition rate is increased and the chlorine residual is increased. In this case, it is confirmed that the second
As such, by adjusting the supply flow rate of ammonia, which is a nitride source, the concentration of residual chlorine in the first
FIG. 9 illustrates a thermal process for the
Referring back to FIG. 3, after forming the second
Unlike in the embodiment of the present invention, in the case of depositing tungsten (W) in addition to the second
Referring to FIG. 5, a transistor is formed by depositing an insulating
100 ...
105 ...
210 ... first
Claims (12)
Depositing a first titanium nitride (TiN) layer containing a relatively low concentration of residual chlorine (Cl) on the gate trench surface;
Depositing a second titanium nitride layer containing a relatively high concentration of residual chlorine on the first titanium nitride layer to form a gate conductive layer; And
And recessing the gate conductive layer.
The first titanium nitride layer is
Deposited to have a liner shape along the profile of the gate trench,
And depositing the second titanium nitride layer to fill the gate trench.
The first titanium nitride layer is
The buried gate forming method of the semiconductor device which deposits containing the said residual chlorine in low concentration within 0.2%.
The second titanium nitride layer
The buried gate forming method of a semiconductor device which is deposited to contain a high concentration of the residual chlorine greater than 0.4% and within 0.9%.
Depositing the first and second titanium nitride layers
An adsorption step of providing titanium tetrachloride;
Nitriding by providing ammonia on the adsorbed titanium tetrachloride; And
Repeating the adsorption step and nitriding step,
In the step of depositing the first titanium nitride layer, the supply flow rate ratio of the ammonia to the titanium tetrachloride is smaller than the step of depositing the second titanium nitride layer, so that the residual chlorine content in the first titanium nitride layer is relatively reduced. A buried gate forming method of a semiconductor device induced at low concentration.
Depositing the first titanium nitride layer is
A buried gate forming method of a semiconductor device, wherein the titanium tetrachloride and the ammonia are supplied at a feed flow ratio of 1: 0.9 to 1: 1.1.
Depositing the second titanium nitride layer is
A buried gate forming method of a semiconductor device, wherein the titanium tetrachloride and the ammonia are supplied at a feed flow ratio of 1: 2 to 1: 4.
Depositing the first and second titanium nitride layers
A method for forming a buried gate in a semiconductor device that proceeds in-situ without vacuum disconnection therebetween.
A first titanium nitride (TiN) layer containing relatively low concentration of residual chlorine (Cl) deposited on the gate trench surface; And
An embedded gate of a semiconductor device comprising a second titanium nitride layer deposited on the first titanium nitride layer to contain a relatively high concentration of residual chlorine.
The first titanium nitride layer is
Has a liner shape to form a concave shape in the gate trench,
The buried gate of the semiconductor device, wherein the second titanium nitride layer fills the concave shape.
The first titanium nitride layer is
A buried gate of a semiconductor device containing the residual chlorine at a low concentration within 0.2%.
The second titanium nitride layer
An embedded gate of a semiconductor device containing the residual chlorine in a high concentration of greater than 0.4% and within 0.9%.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR1020100063062A KR101052930B1 (en) | 2010-06-30 | 2010-06-30 | Buried gate of semiconductor device and fabricating method for the same |
Applications Claiming Priority (1)
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KR1020100063062A KR101052930B1 (en) | 2010-06-30 | 2010-06-30 | Buried gate of semiconductor device and fabricating method for the same |
Publications (1)
Publication Number | Publication Date |
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KR101052930B1 true KR101052930B1 (en) | 2011-07-29 |
Family
ID=44924244
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1020100063062A KR101052930B1 (en) | 2010-06-30 | 2010-06-30 | Buried gate of semiconductor device and fabricating method for the same |
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KR (1) | KR101052930B1 (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6333547B1 (en) | 1999-01-08 | 2001-12-25 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
KR100614240B1 (en) | 2004-06-10 | 2006-08-18 | 삼성전자주식회사 | Semiconductor devices including a field effect transistor and methods of the same |
KR20070046201A (en) * | 2004-09-27 | 2007-05-02 | 인텔 코오퍼레이션 | A metal gate electrode semiconductor device |
KR20080064372A (en) * | 2007-01-04 | 2008-07-09 | 삼성전자주식회사 | Semiconductor having buried word line cell structure and a method of fabricating the same |
-
2010
- 2010-06-30 KR KR1020100063062A patent/KR101052930B1/en not_active IP Right Cessation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6333547B1 (en) | 1999-01-08 | 2001-12-25 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
KR100614240B1 (en) | 2004-06-10 | 2006-08-18 | 삼성전자주식회사 | Semiconductor devices including a field effect transistor and methods of the same |
KR20070046201A (en) * | 2004-09-27 | 2007-05-02 | 인텔 코오퍼레이션 | A metal gate electrode semiconductor device |
KR20080064372A (en) * | 2007-01-04 | 2008-07-09 | 삼성전자주식회사 | Semiconductor having buried word line cell structure and a method of fabricating the same |
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