KR101052930B1 - Buried gate of semiconductor device and fabricating method for the same - Google Patents

Buried gate of semiconductor device and fabricating method for the same Download PDF

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Publication number
KR101052930B1
KR101052930B1 KR1020100063062A KR20100063062A KR101052930B1 KR 101052930 B1 KR101052930 B1 KR 101052930B1 KR 1020100063062 A KR1020100063062 A KR 1020100063062A KR 20100063062 A KR20100063062 A KR 20100063062A KR 101052930 B1 KR101052930 B1 KR 101052930B1
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South Korea
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titanium nitride
nitride layer
gate
layer
semiconductor device
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KR1020100063062A
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Korean (ko)
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은병수
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: A buried gate of a semiconductor device and a forming method thereof are provided to suppress effectively a floating space of a TiN layer in an interface between a gate dielectric layer and a TiN layer by controlling the residual density of chlorine within the TiN layer. CONSTITUTION: A gate trench is formed on a semiconductor substrate. A first titanium nitride(TiN) layer containing the residual chlorine(Cl) of the relatively low concentration is deposited on a surface of the gate trench. A second titanium nitride layer containing the residual chlorine of the relatively high concentration is deposited on an upper surface of the first titanium nitride layer. A gate conductive layer is recessed.

Description

Buried gate of semiconductor device and fabricating method for the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor device technology, and more particularly, to a buried gate (BG) and a method of forming improved reliability.

As the degree of integration of semiconductor devices increases, design rules of circuit patterns are also rapidly decreasing. As memory semiconductor devices such as DRAM devices reduce design rules to 40 nm or less, efforts have been made to improve the structure of transistors constituting memory cells. A cell transistor employing a recess gate or a fin gate structure has become difficult to implement a semiconductor device of 40 nm or less, so that a buried gate buried a gate in an active region of a semiconductor substrate. I'm trying to apply it. Such a buried gate is expected to be effectively applied to a 30 nm class memory semiconductor device.

It is expected that a semiconductor device employing a transistor employing a buried gate can realize an effect of suppressing parasitic capacitance between a gate and a bit line disposed above the transistor due to the structural characteristics of the buried gate. . The reduction of parasitic capacitance can induce an effect of securing a larger sensing margin of the bit line, thereby overcoming the problem of greatly increasing the capacitance of the cell capacitor to secure the sensing margin.

Since the buried gate is to be buried in the active region, plasma induced damage (PID) may be caused to the gate dielectric layer during the formation thereof. After depositing the conductive layer for the buried gate, in the process of etching the conductive layer, the gate dielectric layer formed under the conductive layer may be attacked and damaged by the plasma introduced during the etching. Such damage to the gate dielectric layer eventually degrades the operation reliability of the cell transistors constituting the memory cell of the DRAM, and thus, the refresh time of the DRAM element can be drastically reduced. Accordingly, there is a need for development of a method for suppressing the plasma damage caused in the lower gate dielectric layer when the conductive layer is etched to bury the buried gate in the gate trench.

An object of the present invention is to provide a buried gate and a method of forming a semiconductor device capable of suppressing damage to a gate dielectric layer and improving reliability.

One aspect of the invention, forming a gate trench in the semiconductor substrate; Depositing a first titanium nitride (TiN) layer containing a relatively low concentration of residual chlorine (Cl) on the gate trench surface; Depositing a second titanium nitride layer containing a relatively high concentration of residual chlorine on the first titanium nitride layer to form a gate conductive layer; And it provides a method of forming a buried gate of a semiconductor device comprising the step of recessing the gate conductive layer.

Another aspect of the invention, the semiconductor substrate with a gate trench formed; A first titanium nitride (TiN) layer containing relatively low concentration of residual chlorine (Cl) deposited on the gate trench surface; And a second titanium nitride layer deposited on the first titanium nitride layer to contain a relatively high concentration of residual chlorine.

The first titanium nitride layer may be deposited to contain the residual chlorine at a low concentration within 0.2%.

The second titanium nitride layer may be deposited to contain a high concentration of the residual chlorine greater than 0.4% and within 0.9%.

Depositing the first and second titanium nitride layers

An adsorption step of providing titanium tetrachloride; Nitriding by providing ammonia on the adsorbed titanium tetrachloride; And repeating the adsorption step and the nitriding step, wherein the supply flow rate ratio of the ammonia to the titanium tetrachloride in the deposition of the first titanium nitride layer is smaller than in the deposition of the second titanium nitride layer. Thus, the residual chlorine content in the first titanium nitride layer can be induced to a relatively low concentration.

According to the present invention, it is possible to provide a buried gate and a formation method capable of suppressing damage caused by plasma to the gate dielectric layer and improving reliability. In addition, since the buried gate is made of titanium nitride (TiN), it is possible to exclude heterogeneous interfaces in the buried gate, thereby reducing the resistance Rs of the buried gate line. Accordingly, the write recovery time (tWR) of a memory device such as a DRAM may be improved. In addition, since the buried gate is formed of a single TiN material, it is possible to simplify the deposition process when forming the buried gate. In addition, by controlling the chlorine (Cl) residual concentration in the TiN layer differently, it is possible to effectively suppress the phenomenon that the TiN layer is excited at the interface between the gate dielectric layer and the TiN layer. Accordingly, the reliability of the TiN buried gate can be improved.

1 to 5 are cross-sectional views illustrating a buried gate and a forming method according to an embodiment of the present invention.
6 to 9 are cross-sectional photographs provided to explain the effect of the buried gate and the formation method according to an embodiment of the present invention.

According to an embodiment of the present invention, when a buried gate is formed by depositing a titanium nitride single material, the titanium nitride is a deposition process using a titanium source containing chlorine (Cl) such as titanium tetrachloride (TiCl 4 ) and ammonia (NH 3 ). Deposit a layer. At this time, when performing the deposition process by varying the chlorine (Cl) concentration remaining in the titanium nitride layer, a first titanium nitride layer containing a relatively low concentration of chlorine is deposited on the bottom, and on the first titanium nitride layer By depositing a second titanium nitride layer containing a relatively high concentration of residual chlorine, the phenomenon that the interface between the gate dielectric layer and the titanium nitride layer is lifted can be effectively suppressed.

Referring to FIG. 1, a gate trench 105 in which a gate of a transistor is buried is formed in a semiconductor substrate 100. A portion of the semiconductor substrate 100 under the bottom of the gate trench 105 is used as a channel region 101 of the transistor, and portions of the semiconductor substrate 100 on both sides of the gate trench 105 are formed as source or drain regions. It is used as a junction region 103 such as a source or drain region.

After the gate trench 105 is formed by recessing the semiconductor substrate 100 through a selective etching process, the gate dielectric layer 150 is formed on the surface of the semiconductor substrate 100 on which the gate trench 105 is formed. The gate dielectric layer 150 may be formed by an oxidation process and extends along sidewalls and bottoms along a profile of the gate trench 105.

Referring to FIG. 2, a first titanium nitride (TiN) layer 210 containing a low concentration of residual chlorine (Cl) is deposited on the gate dielectric layer 150. The second titanium nitride layer 230 is deposited on the first titanium nitride layer 210 in a subsequent process step. The first titanium nitride layer 210 has a lower concentration of residual chlorine (Cl) than the second titanium nitride layer. It is deposited to contain. The first titanium nitride layer 210 is deposited to contain residual chlorine at a low concentration within 0.2%, and may include 0.001% to 0.2% residual chlorine.

The first titanium nitride layer 210 is deposited to have a liner shape along the profile of the gate trench 105, and thus is deposited to have a concave shape in the gate trench 105. In order to fill this concave shape, a second titanium nitride layer is deposited in a subsequent process.

The first titanium nitride layer 210 may be formed by a deposition process using a titanium chloride source such as titanium tetrachloride (TiCl 4 ) and a nitride source such as ammonia (NH 3 ). Titanium tetrachloride was supplied at approximately 60 sccm at a supply flow rate of about 3 seconds to adsorb titanium tetrachloride onto the gate dielectric layer 150, and then ammonia was supplied at a supply flow rate of 60 sccm at an equivalent time of approximately 8 seconds, The formation of titanium nitride is induced by the nitriding process by the reaction of adsorbed titanium tetrachloride and ammonia. This adsorption and nitriding step is repeated in one cycle, and the cycle is repeated so that the first titanium nitride layer 210 is grown to a thickness of approximately 55 kPa. At this time, the deposition temperature may be maintained at about 670 ℃. At this time, the supply flow rate may be varied in the range of plus or minus (+), (-) 10%, and the deposition temperature may also be varied in the range of plus or minus (+), (-) 10%.

When the first titanium nitride layer 210 is deposited, hydrogen chloride (HCl) is generated and discharged as a reaction by-product of titanium tetrachloride and ammonia, but a certain amount of chlorine (Cl) component may remain in the first titanium nitride layer 210. have. Such residual amount of chlorine has been confirmed experimentally to increase the amount depending on the deposition rate of titanium nitride (TiN). It is also confirmed experimentally that the deposition rate of titanium nitride tends to increase depending on increasing the ratio of the feed flow rate of ammonia to the feed flow rate of titanium tetrachloride. Therefore, when titanium tetrachloride is supplied at about 60 sccm at a supply flow rate of about 3 seconds and ammonia is supplied at a feed flow rate of 60 sccm, that is, when the feed flow rate ratio of titanium tetrachloride and ammonia is 1: 1, deposition is relatively low. It shows the speed, it is confirmed experimentally that less than 0.2% chlorine remains in the first titanium nitride layer 210 obtained at this time. Since titanium nitride is formed and nitrided in a very thin thickness by cycle deposition, it exhibits a very low deposition rate. Meanwhile, as long as the first titanium nitride layer 210 exhibits a residual chlorine concentration of 0.2% or less, titanium tetrachloride and ammonia may be provided in a supply flow rate ratio range of 1: 0.9 to 1: 1.1.

The first titanium nitride layer 210 serves as a barrier to prevent the lifting phenomenon. 6 and 7, when the TiN layer 310 is deposited on the gate dielectric layer 150 of the semiconductor substrate 100 using TiCl 4 , a cross-sectional view of the cross section of the TiN layer 310 is observed using a transmission electron microscope (TEM). 6, no voids or empty spaces are observed at the interface between the TiN layer 310 and the gate dielectric layer 150 immediately after deposition, but after the thermal process such as annealing is performed, FIG. 7. As shown in FIG. 3, the void 311 or the empty space is observed at the interface between the TiN layer 310 and the gate dielectric layer 150, and the TiN layer 310 is lifted up. 6 and 7 are cross-sectional views cut in a direction in which a gate, a word line, extends in a cross section perpendicular to the cross section of FIG. 1. Accordingly, the portion of the semiconductor substrate 100 set by the device isolation layer 120 corresponds to the channel region 101 of FIG. 1. Therefore, as shown in FIG. 7, the film quality lifting phenomenon in which the voids 311 are caused at the interface serves to deteriorate the reliability of the transistor. This lifting phenomenon is experimentally confirmed to be caused by residual chlorine (Cl) in the TiN layer 310.

FIG. 8 is a photograph showing a profile after a thermal process when the TiN layer 330 is deposited with a residual chlorine concentration of 0.2% or less as in the first titanium nitride layer 210 of the present invention. When the residual chlorine concentration is limited to 0.2% or less, it can be experimentally confirmed that the film quality lifting phenomenon as shown in FIG. 7 is suppressed. However, when the TiN layer 330 is deposited in a thick thickness as described above, as long as the residual chlorine concentration is maintained at a low concentration, the deposition rate may be too low, thereby causing a problem in that the productivity is reduced. Therefore, in the exemplary embodiment of the present invention, the first titanium nitride layer 210 is deposited to a thickness of about 40 kPa to 70 kPa, which is a thickness sufficient to act as a barrier to suppress the lifting phenomenon.

Referring back to FIG. 2, after depositing the first titanium nitride layer 210 to act as a barrier to suppress the lifting phenomenon, as shown in FIG. 3, the second titanium nitride layer 210 is deposited on the first titanium nitride layer 210. A layer 230 is deposited to fill the gate trench 150. The second titanium nitride layer 230 is deposited to fill the concave shape of the first titanium nitride layer 210. The second titanium nitride layer 230 is deposited to have a higher deposition rate than the first titanium nitride 210. Increasing the deposition rate increases the concentration of residual chlorine, causing the second titanium nitride layer 230 to have a higher concentration of residual chlorine than the first titanium nitride layer 210, but at the interface the first titanium nitride layer Since 210 is present, the lifting phenomenon can be effectively suppressed in the subsequent thermal process.

The deposition rate of titanium nitride can be realized by increasing the feed flow rate ratio of ammonia to titanium tetrachloride. For example, at a deposition temperature of 670 ° C., the second titanium nitride layer is repeated by repeatedly supplying titanium tetrachloride at a supply flow rate of approximately 60 sccm and supplying ammonia three times at a supply flow rate of 180 sccm for 8 seconds. 230 is deposited to a thickness of approximately 300 kV to 800 kV. As the deposited layer is deposited relatively thick and nitrided, the deposition rate is increased and the chlorine residual is increased. In this case, it is confirmed that the second titanium nitride layer 230 contains residual chlorine at most about 0.9%. More than 0.9% residual chlorine is undesirable because it can lead to deterioration of transistor performance. This flow rate can be varied in 10% range, and as long as the first titanium nitride layer 210 exhibits a residual chlorine concentration of 0.2% or less, titanium tetrachloride and ammonia are supplied in a flow rate ratio of 1: 2 to 1: 4. It may be provided as. Although the chlorine residual amount increases with increasing deposition rate, it is effective to adjust the chlorine residual concentration within the range of 0.4% to 0.9%.

As such, by adjusting the supply flow rate of ammonia, which is a nitride source, the concentration of residual chlorine in the first titanium nitride layer 210 and the second titanium nitride layer 230 can be induced differently. Augmentation can be implemented together. Since other process conditions can be maintained in addition to the different application of ammonia feed flow rate, the deposition of the first titanium nitride layer 210 and the second titanium nitride layer 230 may be performed in-situ without mutual vacuum disconnection. ) May be performed. Thus, the introduction of substantial additional processes can be ruled out.

FIG. 9 illustrates a thermal process for the TiN layer 350 in which the first titanium nitride layer 351 and the second titanium nitride layer 353 are deposited in situ to have different residual chlorine concentrations according to an exemplary embodiment of the present invention. It is a TEM photograph which observed the cross section after performing. The first TiN layer 351 is identified at a residual chlorine concentration of 0.2%, and the second TiN layer 355 is identified at a residual chlorine concentration of 0.9%. In the cross section of FIG. 9, it can be seen that the lifting phenomenon such as voids is effectively suppressed at the interface with the gate dielectric layer 150.

Referring back to FIG. 3, after forming the second titanium nitride layer 230 to fill the gate trench 105, as shown in FIG. 4, the second titanium nitride layer 230 includes first and second titanium nitride layers 210 and 230. And recess the gate conductive layer so that its upper surface is lowered into the gate trench 105. Accordingly, the buried gate 200 is formed to partially fill the bottom portion of the gate trench 105 to partially fill the gate trench 105. In this case, the recess process may be performed by an etching process using chlorine gas (Cl 2 ), or may be performed by further using argon (Ar) together with the chlorine gas. Since the etching process for the recess is basically performed using chlorine gas, and the silicon oxide substantially forming the gate dielectric layer 150 has a relatively strong resistance to the chlorine component, the etching process is performed by plasma to the gate dielectric layer 150. Damage can be effectively suppressed. Accordingly, it is possible to improve that the refresh time of the transistor is reduced.

Unlike in the embodiment of the present invention, in the case of depositing tungsten (W) in addition to the second titanium nitride layer 230, sulfur hexafluoride (SF 6 ) must be used as an etching gas in this recess process. However, in this etching process, it is experimentally confirmed that the damage caused by the plasma to the gate dielectric layer 150 is relatively large. Therefore, since the buried gate 200 according to the embodiment of the present invention does not contain tungsten, it may be formed while effectively suppressing the damage to the gate dielectric layer 150. Furthermore, since the first and second titanium nitride layers 210 and 230 include substantially the same titanium nitride, a heterogeneous interface is not induced in the investment gate 200, thereby reducing the resistance of the investment gate. TWR improvement can be implemented.

Referring to FIG. 5, a transistor is formed by depositing an insulating layer 250 blocking the buried gate 200 and injecting impurities into the junction region 103 to form source and drain regions.

100 ... Semiconductor Board 101 ... Channel Area
105 ... gate trench 200 ... burying gate
210 ... first titanium nitride layer 230 ... second titanium nitride layer.

Claims (12)

Forming a gate trench in the semiconductor substrate;
Depositing a first titanium nitride (TiN) layer containing a relatively low concentration of residual chlorine (Cl) on the gate trench surface;
Depositing a second titanium nitride layer containing a relatively high concentration of residual chlorine on the first titanium nitride layer to form a gate conductive layer; And
And recessing the gate conductive layer. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1,
The first titanium nitride layer is
Deposited to have a liner shape along the profile of the gate trench,
And depositing the second titanium nitride layer to fill the gate trench. Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1,
The first titanium nitride layer is
The buried gate forming method of the semiconductor device which deposits containing the said residual chlorine in low concentration within 0.2%. Claim 4 was abandoned when the registration fee was paid. The method of claim 1,
The second titanium nitride layer
The buried gate forming method of a semiconductor device which is deposited to contain a high concentration of the residual chlorine greater than 0.4% and within 0.9%. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1,
Depositing the first and second titanium nitride layers
An adsorption step of providing titanium tetrachloride;
Nitriding by providing ammonia on the adsorbed titanium tetrachloride; And
Repeating the adsorption step and nitriding step,
In the step of depositing the first titanium nitride layer, the supply flow rate ratio of the ammonia to the titanium tetrachloride is smaller than the step of depositing the second titanium nitride layer, so that the residual chlorine content in the first titanium nitride layer is relatively reduced. A buried gate forming method of a semiconductor device induced at low concentration. Claim 6 was abandoned when the registration fee was paid. The method of claim 5,
Depositing the first titanium nitride layer is
A buried gate forming method of a semiconductor device, wherein the titanium tetrachloride and the ammonia are supplied at a feed flow ratio of 1: 0.9 to 1: 1.1. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 5,
Depositing the second titanium nitride layer is
A buried gate forming method of a semiconductor device, wherein the titanium tetrachloride and the ammonia are supplied at a feed flow ratio of 1: 2 to 1: 4. Claim 8 was abandoned when the registration fee was paid. The method of claim 1,
Depositing the first and second titanium nitride layers
A method for forming a buried gate in a semiconductor device that proceeds in-situ without vacuum disconnection therebetween. A semiconductor substrate on which a gate trench is formed;
A first titanium nitride (TiN) layer containing relatively low concentration of residual chlorine (Cl) deposited on the gate trench surface; And
An embedded gate of a semiconductor device comprising a second titanium nitride layer deposited on the first titanium nitride layer to contain a relatively high concentration of residual chlorine. Claim 10 was abandoned upon payment of a setup registration fee. 10. The method of claim 9,
The first titanium nitride layer is
Has a liner shape to form a concave shape in the gate trench,
The buried gate of the semiconductor device, wherein the second titanium nitride layer fills the concave shape. Claim 11 was abandoned upon payment of a setup registration fee. 10. The method of claim 9,
The first titanium nitride layer is
A buried gate of a semiconductor device containing the residual chlorine at a low concentration within 0.2%. Claim 12 was abandoned upon payment of a registration fee. 10. The method of claim 9,
The second titanium nitride layer
An embedded gate of a semiconductor device containing the residual chlorine in a high concentration of greater than 0.4% and within 0.9%.
KR1020100063062A 2010-06-30 2010-06-30 Buried gate of semiconductor device and fabricating method for the same KR101052930B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6333547B1 (en) 1999-01-08 2001-12-25 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
KR100614240B1 (en) 2004-06-10 2006-08-18 삼성전자주식회사 Semiconductor devices including a field effect transistor and methods of the same
KR20070046201A (en) * 2004-09-27 2007-05-02 인텔 코오퍼레이션 A metal gate electrode semiconductor device
KR20080064372A (en) * 2007-01-04 2008-07-09 삼성전자주식회사 Semiconductor having buried word line cell structure and a method of fabricating the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6333547B1 (en) 1999-01-08 2001-12-25 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
KR100614240B1 (en) 2004-06-10 2006-08-18 삼성전자주식회사 Semiconductor devices including a field effect transistor and methods of the same
KR20070046201A (en) * 2004-09-27 2007-05-02 인텔 코오퍼레이션 A metal gate electrode semiconductor device
KR20080064372A (en) * 2007-01-04 2008-07-09 삼성전자주식회사 Semiconductor having buried word line cell structure and a method of fabricating the same

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