KR101048707B1 - Multichannel Elements of Liquid Crystal Display and Formation Method Thereof - Google Patents

Abstract

The present invention provides a liquid crystal that improves self heating, floating body effect, and kink effect, which are particularly problematic in wide devices by varying the shape of the semiconductor layer during patterning of the device. The present invention relates to a multi-channel device of a display device and a method of manufacturing the same, wherein the multi-channel device of a liquid crystal display device of the present invention includes a substrate, a plurality of first semiconductor layers arranged at regular intervals on the substrate, and the first semiconductor. A gate metal layer crossing the layers, a source metal layer and a drain metal layer spaced apart from both sides of the gate metal layer at both ends of the first semiconductor layers in the same direction as the gate metal layer, and the first semiconductor layers on both sides of the gate metal layer; An image between the first impurity layer defined in the second semiconductor layer and spaced apart from the first semiconductor layer corresponding to the gate metal layer and the source metal layer Claim it characterized by yirueojim including the second impurity layer formed in the second semiconductor layer and the second semiconductor layer formed in the first semiconductor layer and the integral.

Floating body effect, multi-channel, thin film transistor (TFT), self-heating, kink effect, body contact, reliability

Description

Multi-Channel Device for Liquid Crystal Display and Forming Method thereof {Multi-Channel Device for Liquid Crystal Display Device and Method for Forming the same}

1 is a plan view showing a typical liquid crystal panel

FIG. 2A is a circuit diagram illustrating a 3-terminal thin film transistor, and FIG. 2B is a circuit diagram of the thin film transistor of FIG. 2A connected in parallel.

3A and 3B are graphs illustrating changes in drain current according to gate voltage when the widths W and lengths L of the channels are the same and the widths are relatively longer than the lengths, respectively.

4 is a plan view of a conventional multi-channel device

5 is a structural cross-sectional view taken along line II ′ of FIG. 4.

6 is a cross-sectional view taken along line II-II 'of FIG.

FIG. 7 is a cross-sectional view taken along line III-III ′ of FIG. 4;

FIG. 8 is a cross-sectional view taken along line IV-IV 'of FIG.

9 is a photograph showing an example of a multi-channel device having equal intervals

FIG. 10 is a graph illustrating a change in drain current with respect to a gate voltage for each of the first to fifth thin film transistors of the multichannel device of FIG.

FIG. 11 is a photograph showing thermal damage due to self heating of the device of FIG.                 

12A is a diagram schematically illustrating movement of electrons and holes when a bias voltage is applied to a general thin film transistor.

FIG. 12B is a diagram schematically illustrating an increase in hole concentration occurring in the source region in the case of FIG. 12A.

13A and 13B are circuit diagrams and schematic diagrams illustrating four terminal devices having body contacts;

14 is a circuit diagram showing a state in which four terminal devices having body contacts are connected in parallel;

15 is a plan view illustrating a multichannel device of a liquid crystal display according to a first exemplary embodiment of the present invention.

16 is a cross-sectional view taken along the line VV ′ of FIG. 15.

17 is a cross-sectional view taken along the line VI-VI 'of FIG. 15.

18 is a cross-sectional view taken along line VII-VII 'of FIG. 15;

19 is a structural cross-sectional view taken along line VII-VII ′ of FIG. 15.

20A to 20F are process plan views illustrating a method of manufacturing a multichannel device of a liquid crystal display of the present invention.

21A-21F are cross-sectional views of respective processes of FIGS. 20A-20F.

22 is a plan view illustrating a multichannel device of a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 23 is a plan view illustrating the semiconductor layer of FIG. 22.                 

24 is a plan view illustrating the semiconductor layer and an impurity layer thereof of FIG. 22.

* Description of the main parts of the drawings *

100 substrate 103 gate insulating film

101: buffer layer 102: semiconductor layer (intrinsic semiconductor layer)

102a: source region (type 1 impurity layer)

102b: drain region (type 1 impurity layer)

104: gate metal layer 104a, 204a: gate electrode

105: interlayer insulating film 106: protective film

107 and 207 source metal layers 107a and 207a source electrode

108, 208: drain metal layer 108a, 208a: drain electrode

110: first semiconductor layer 111: second semiconductor layer

112: type 2 impurity layer 118, 218: first contact (body contact) hole

119, 219: Second contact (source contact) hole

120, 220: 3rd contact (drain contact) hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and in particular, by varying the shape of the semiconductor layer during patterning of the device, self heating, floating body effect, and kink effect, which are particularly problematic in wide-width devices. The present invention relates to a multi-channel device of a liquid crystal display device having improved Kink effect and a method of manufacturing the same.

As the information society develops, the demand for display devices is increasing in various forms, and in recent years, liquid crystal display devices (LCDs), plasma display panels (PDPs), electro luminescent displays (ELD), and vacuum fluorescent (VFD) Various flat panel display devices such as displays have been studied, and some of them are already used as display devices in various devices.

Among them, LCD is the most widely used as the substitute for CRT (Cathode Ray Tube) for mobile image display device because of its excellent image quality, light weight, thinness, and low power consumption. In addition to the use of the present invention has been developed in various ways such as a television and a computer monitor for receiving and displaying broadcast signals.

In order to use such a liquid crystal display as a general screen display device in various parts, it is a matter of how high quality images such as high definition, high brightness and large area can be realized while maintaining the characteristics of light weight, thinness and low power consumption. Can be.

A general liquid crystal display device may be largely divided into a liquid crystal panel displaying an image and a driving unit for applying a driving signal to the liquid crystal panel, wherein the liquid crystal panel includes first and second glass substrates bonded to each other with a predetermined space; It consists of a liquid crystal layer injected between the said 1st, 2nd glass substrate.                         

The first glass substrate (TFT array substrate) may include a plurality of gate wires arranged in one direction at a predetermined interval, a plurality of data wires arranged at regular intervals in a direction perpendicular to the respective gate wires, A plurality of pixel electrodes formed in a matrix form in each pixel region defined by crossing gate lines and data lines, and a plurality of thin film transistors switched by signals of the gate lines to transfer signals of the data lines to each pixel electrode. Is formed.

The second glass substrate (color filter substrate) includes a light shielding layer for blocking light in portions other than the pixel region, an R, G, and B color filter layers for expressing color colors, and a common electrode for implementing an image. Is formed.

The driving principle of the general liquid crystal display device uses the optical anisotropy and polarization property of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the arrangement of molecules can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal by optical anisotropy, thereby representing image information.

Currently, an active matrix LCD, in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner, is attracting the most attention due to its excellent resolution and ability to implement video.

On the other hand, the driving unit of the liquid crystal display device is an external type to connect the pad portion of the panel to an external driver, and the built-in type is formed together with the panel. In the embedded case, the semiconductor layer deposited on the substrate is polysilicon in which amorphous silicon is crystallized. This is because polysilicon has much higher mobility of carriers than amorphous silicon, thereby ensuring high speed and reliability of the IC for driving circuits.

Here, the liquid crystal display device includes, in particular, polysilicon which is crystallized in a low temperature process (425 ° C. or lower) as a semiconductor layer, because crystallization is performed on a glass substrate susceptible to heat.

Hereinafter, a multichannel device of a device of a conventional liquid crystal display will be described with reference to the accompanying drawings.

1 is a plan view illustrating a general liquid crystal panel.

As shown in FIG. 1, a general liquid crystal panel includes a liquid crystal layer (not shown) filled between an upper substrate 10, a lower substrate 20, and upper and lower substrates 10 and 20 that are largely opposed to each other.

Here, a color filter array is formed on the upper substrate 10, and a TFT array is formed on the lower substrate 20. In the TFT array, a gate line and a data line crossing each other to define a pixel region, a thin film transistor formed at an intersection of the gate line and the data line, and a pixel electrode formed in the pixel region (TN (Twisted Nematic) mode) In the case of an in-plane switching (IPS) mode, the pixel region further includes a common electrode that is alternately formed with the pixel electrode. The color filter array includes a black matrix layer formed to cover the non-pixel region and the thin film transistor. And a color filter layer formed corresponding to the pixel region, and a common electrode (in TN mode) or overcoat layer (in IPS mode) formed on the entire surface of the upper substrate 10.

Meanwhile, the dotted line inner portion of the liquid crystal panel of FIG. 1 is a display area, and the dotted line outer portion is a non-display area. Here, the reason why the lower substrate 20 is further formed with a margin at the periphery of the upper substrate 10 is to configure the driving unit at the margin. As described above, in the case of the external type, the driving part is connected to the pad part of the lower substrate 20 to be configured outside the liquid crystal panel, and in the case of the internal type, the driving part is the margin part of the lower substrate 20 (the lower substrate not covered by the upper substrate). Site).

Hereinafter, the element comprised in the said drive part is demonstrated.

2A is a circuit diagram illustrating a three-terminal thin film transistor, and FIG. 2B is a circuit diagram of the thin film transistors of FIG. 2A connected in parallel.

As shown in FIG. 2A, a general thin film transistor includes three terminals of a gate terminal G, a source terminal S, and a drain terminal D. FIG.

As shown in FIG. 2B, when the plurality of thin film transistors are configured to have a common gate, a common drain, and a common source, the plurality of thin film transistors have a shape in which the plurality of thin film transistors are configured in parallel. The channels of are arranged in parallel and are gathered in one path at the source and drain ends.

As such, the reason for forming an element in which one path is divided into a plurality of multi-channels is that when a wide width channel element is formed of a single transistor, heat is concentrated in the element when the element is driven. This is to prevent the phenomenon of being destroyed. That is, in the case of a wide element having multiple channels with a plurality of transistors, the heat generated when the device is driven is divided into a plurality of transistors, and the heat discharged to the spaces spaced between the transistors is released so that the element is caused by the heat. This is because the deterioration phenomenon can be prevented to some extent.

In addition, in order to implement a wide element having a high output characteristic with a single transistor formed in a TFT process in a situation where a single transistor is formed with a smaller and smaller size, a single wide element is formed of a plurality of single transistors. .

3A and 3B are graphs illustrating changes in drain current according to gate voltages when the widths W and lengths L of the channels are the same and the widths are relatively longer than the lengths, respectively.

3A shows a case where both the width and the length of the channel of the semiconductor layer are equal to 10 μm, and FIG. 3B shows the case where the width and the length of the channel of the semiconductor layer are 100 μm and 10 μm, respectively, as in the wide element.

3A and 3B, as the ratio (W / L) of the channel width and length of the semiconductor layer of the device is larger, the lowering of the threshold voltage occurs, and the current Id flowing in the drain. It can be seen that the value increases.

In addition, when the bias element Vd applied to the drain is large (in the case of FIG. 3B) and is large, it is determined to be a stress situation, and the current Id flowing in the drain is continuously increased, resulting in a saturation state. Difficult to reach was observed. As described above, when the bias voltage Vd applied to the drain is large and the drain element is large, the transition curve of the graph showing the characteristics Vg-Id of the drain current Id with respect to the gate voltage Vg is transferred. curve split) is intensified.

As described above, when the saturation state of the drain current is not obtained in the wide element, there is a problem in that the gain of the element is lowered because a high output resistance is not obtained.

Also, in the wide element, the reduction of the threshold voltage Vth due to source barrier lowering increases the amount of electrons contributing to the drain avalanche, which in turn causes the hole current ( Increasing the hole current, and again, source barrier lowering causes a positive feedback (positive feed back), which appears as a device reliability problem after a long drive. Due to this cause, a kink effect (a phenomenon in which the drain current does not saturate with the increase of the gate voltage and continuously increases) appears due to the Ids-Vds output characteristic.

4 is a plan view of a conventional multi-channel device, FIG. 5 is a structural cross-sectional view taken along line I-I 'of FIG. 4, FIG. 6 is a structural cross-sectional view taken along line II-II' of FIG. 4, and FIG. It is structural sectional drawing of III-III 'line | wire, and FIG. 8 is a structural sectional view of IV-IV' line | wire of FIG.

In the multi-channel device formed on the driving unit of a general polysilicon liquid crystal display, a plurality of three-terminal devices are connected in parallel, as shown in the circuit diagram of FIG. 2B.                         

As shown in FIG. 4, a multi-channel device of a conventional liquid crystal display having three terminal devices configured in parallel includes a plurality of semiconductor layers arranged to be spaced apart from each other in a predetermined direction on a predetermined portion of a lower substrate (see 20 of FIGS. 5 to 8). 22, a gate metal layer 24 formed in a line shape across the center of the semiconductor layers 22, and a source metal layer formed on both sides of the semiconductor layers 22 in parallel with the gate metal layer 24, respectively. And a drain metal layer 28. Here, the widths W1, W2, W3, and W4 of the semiconductor layers are formed in the same manner, and the intervals between the semiconductor layers 22 are also formed in the same manner.

In this case, as shown in FIG. 7, the gate metal layer overlapping the semiconductor layer 22 of the corresponding portion in each semiconductor layer 22 functions as the gate electrode 24a, and the source metal layer overlaps the semiconductor layer 22. The drain metal layer, which functions as the source electrode 27a and overlaps the semiconductor layer 22, functions as the drain electrode 28a. Each of the electrodes 24a, 27a, and 28a and the semiconductor layer 22 of the corresponding region is provided. Including a thin film transistor.

In this case, each of the formed thin film transistors passes through the gate metal layer 24 having a constant width W, and defines a channel region 22c corresponding to the size of the gate metal layer 24 corresponding to each semiconductor layer 22. Has Therefore, the channels formed in the respective thin film transistors are all the same length (L). In this case, each thin film transistor is formed in parallel so that the width of the channel of the device is the sum of the widths of the thin film transistors, that is, the value of W (= W1 + W2 + W3 + W4). As described above, when a multichannel is formed, a wide channel is formed. In this case, distortion of the change curve Vg-Id of the current according to the gate voltage occurs. That is, the threshold voltage Vth is lowered and the current saturation state is not achieved.

Hereinafter, a method of manufacturing a multichannel device of a conventional liquid crystal display will be described with reference to FIGS. 4 to 8.

First, a buffer layer 21 is deposited on the entire surface of the substrate 20.

Subsequently, an amorphous silicon layer is entirely deposited on the buffer layer 21 and crystallized by irradiating the laser.

Subsequently, the crystallized silicon layer is patterned to form a plurality of semiconductor layers 22 arranged at equal intervals in a predetermined direction.

Next, a gate insulating film 23 is deposited on the entire buffer layer 21 including the plurality of semiconductor layers 22.

Subsequently, a metal material is entirely deposited on the entire surface of the gate insulating layer 23, and then selectively removed to form a gate metal layer 24 in a direction crossing the center of the semiconductor layer 22.

Subsequently, n + doping is performed on portions of the semiconductor layer 22 corresponding to both sides of the gate metal layer 24 using the gate metal layer 24 as a mask to drain the source region 22a and the drain of the semiconductor layer 22. The area 22b is defined. At this time, an intrinsic semiconductor region not doped with impurities under the gate metal layer 24 functions as a channel 22c. The portion of the gate metal layer 24 corresponding to the upper portion of the channel 22c serves as the gate electrode 24a.

Subsequently, an interlayer insulating layer 25 is deposited on the buffer layer including the gate metal layer 24, and then selectively removed to remove a predetermined portion of the source region 22a and the drain region 22b of the semiconductor layer 22. The first and second contact holes 29 and 30 are respectively exposed.

Subsequently, after depositing a metal material on the entire surface of the interlayer insulating layer 25 including the first and second contact holes 29 and 30, the metal material is selectively removed to be parallel to the gate metal layer 24, and the gate metal layer The source metal layer 27 and the drain metal layer 28 spaced apart from the same at 24 are formed. Here, a portion of the source metal layer 27 corresponding to the source region 22a of the semiconductor layer functions as a source electrode 27a and a portion of the drain metal layer 28 corresponding to the drain region 22b of the semiconductor layer. Functions as the drain electrode 28a.

Next, the passivation layer 26 is deposited on the entire surface of the interlayer insulating layer 25 including the source / drain metal layers 27 and 28.

Such a multi-channel element of the liquid crystal display device is formed in the driving portion (outside the pixel) of the liquid crystal panel, and is formed in the same process as the TFT forming process of the liquid crystal panel.

9 is a photograph showing an example of a multi-channel device having equal intervals.

As illustrated in FIG. 9, in the multi-channel device of the conventional liquid crystal display, a plurality of semiconductor layers are formed at equal intervals. In FIG. 9, a total of five semiconductor layers are formed at equal intervals, and channels are formed in the same width in each semiconductor layer.

For convenience, each transistor of the multi-channel device is named as first to fifth thin film transistors (TFT (1), TFT (2), TFT (3), TFT (4), and TFT (5)) in order from the left. do.

FIG. 10 is a graph illustrating a change in drain current with respect to a gate voltage for each of the first to fifth thin film transistors of the multichannel device of FIG. 9, and FIG. 11 is due to self-heating of the device of FIG. 9. Photo shows a thermal damage.

10 and 11, when the multi-channel device of FIG. 9 is driven for a predetermined time, a self-heating phenomenon occurs in which heat of the device itself occurs.

As shown in FIG. 9, when the semiconductor layers having the respective channels are arranged at equal intervals, heat concentration in the center of the multi-channel device, that is, the third thin film transistor TFT 3 is reduced as shown in FIGS. 10 and 11. The most severe, gradually falling heat is observed around it.

FIG. 10 shows the change of the Vg-Id curve of each thin film transistor due to such self heating. As a result, it can be seen that the gain of the thin film transistor decreases as the self heating phenomenon increases.

In FIG. 11, in particular, it can be seen that thermal damage having concentric circles in the width direction occurs. This result, together with the result of FIG. 10, can be understood as a relatively difficult heat release of the central region.

As such, it is confirmed that heat generation occurs at a temperature of more than 300 ° C. in a region where heat is concentrated, which is caused by cracking of silicon and hydrogen bonding (Si-H bonding) in the channel of the polysilicon layer due to self heating. It is reported as the cause of re-generation of dangling bonding.                         

Heat is inevitably generated during operation of the device, and it is recognized that heat generated at this time is due to the applied power (Ids × Vds). Therefore, after heat is generated in each thin film transistor, the semiconductor layer does not dissipate heat due to an oxide film having a low thermal conductivity surrounded around the semiconductor layer, thereby forming a heat island.

In contrast, in the case of a semiconductor device formed on a silicon wafer (Si wafer), the heat island is not formed because heat generated by the high thermal conductivity of silicon (Si) itself is easily released. However, the multi-channel device introduced herein is an element formed on the substrate of the liquid crystal display device, and does not prevent the generation of heat island with the element formed on the glass substrate.

In particular, in the second to fourth thin film transistors TFT (2), TFT (3), and TFT (4) located at the center, deterioration due to self heating is severe, and the gate voltage-drain current (Vg-Id) curve is rightward. Shifting (increasing the threshold voltage) occurs, and the drain current Id after the turn-on of the thin film transistor is compared with the first and fifth thin film transistors TFT (1) and TFT (5) located at both ends. Observed at low values.

As described above, the reason why the deterioration phenomenon is severe in the second to fourth thin film transistors TFT (2), TFT (3), and TFT (4), which are the centers of the multichannel devices, is due to the component located around the semiconductor layer channel 22c. This is because the gate insulating film 23 having a low thermal conductivity is difficult to dissipate heat even if a space is provided between the semiconductor layer channels 22c.

In addition, since the semiconductor layer 22 made of polycrystalline silicon breaks the bond between silicon (Si) and hydrogen (H), or the regeneration of dangling bonding occurs, the degradation phenomena becomes worse. have.

FIG. 12A is a diagram schematically illustrating movement of electrons and holes when a bias voltage is applied to a general thin film transistor, and FIG. 12B is a diagram schematically illustrating an increase in hole concentration occurring in a source neighborhood in FIG. 12A.

As shown in FIG. 12A, when the voltages Vg and Vd are applied to the gate electrode 24a and the drain electrode (see 28a in FIGS. 4 and 7, respectively), the drain region 22b and the source region 22a in the semiconductor layer 22. The channel region 22c is formed in the intrinsic semiconductor region between the holes, and there is exchange of holes and electrons between the source region 22a and the drain region 22b in the channel region 22c. That is, the movement of the electrons (e−) from the source region 22a to the drain region 22b occurs, and the movement of the hole h + from the drain region 22b to the source region 22a occurs.

At this time, electrons e- are accelerated by applying the bias voltages Vg and Vd to generate a drain avalanche in which a large amount of electrons e- and holes h + are generated in the drain region 22b. The generated electron (e−) exits the drain electrode 28a, and the hole h + passes through the channel again (see FIGS. 27A of FIGS. 4 and 7 and not shown in FIGS. 9 and 10). Exit to However, in this case, the hole h + moves to the lower layer of the channel region 22c, which is an intrinsic semiconductor region, when the voltage Vg is applied to the gate electrode 24a, and when the hole h + passes through the channel to the source region 22a, FIG. 12B. As shown, some remain trapped at the interface of the buffer layer 21 (lower layer of the semiconductor layer). Such an increase in the hole (h +) concentration near the source region 22a is overcome when electrons e- are transferred from the source region 22a to the drain region 22b through the channel region 22c which is an intrinsic semiconductor region. It causes a source barrier lowering that lowers the barriers that must. That is, after the bias voltage is applied to the gate electrode 24a and the drain electrode 28a, the threshold voltage Vth is lowered after a predetermined time is delayed. As described above, a phenomenon in which a hole concentration increases at an interface between a lower layer of the semiconductor layer 22, causes source barrier lowering, and a lower threshold voltage Vth is called a floating body effect. .

In addition, the reduction of the threshold voltage (Vth) due to source barrier lowering increases the amount of electrons contributing to the drain avalanche, which in turn increases the hole current and again the source barrier. Source barrier lowering causes a positive feed back, which is weighted, and appears as a device reliability problem for long time driving.

The deterioration of device characteristics due to the floating body effect is exacerbated in the case of a short channel device, and is an important reliability factor that must be overcome in order to implement polysilicon panels.

On the other hand, in recent years, a structure for forming a body contact (body contact) has been proposed to suppress the above-mentioned floating body effect (floating body effect).

Hereinafter, a configuration of a device forming a body contact will be described with reference to the drawings.

13A and 13B are circuit diagrams and schematic diagrams illustrating four terminal devices having body contacts.                         

13A and 13B illustrate four terminal devices having a total of four terminals as a source terminal S, a drain terminal D, a gate terminal G, and a body terminal B. FIGS. In this case, the body end B is in contact with the source end S.

The reason for having such a source terminal S and a body contact is a floating body effect due to an increase in hole concentration in the source region 22a of the semiconductor layer 22 when driving a device in a short channel. In order to prevent this from happening, an excess hole in the source region 22a exits to the body due to such a body contact.

However, in order to form such a body contact, the source region 22a, the drain region 22b and the channel region 22c and the channel region 22c are connected to the body region when the semiconductor layer is formed. Since the patterning is performed to further include a predetermined region to be defined as 22d), the body region 22d must be further provided as compared with the thin film transistor having the three-terminal configuration, so that the total area of the semiconductor layer 22 becomes large.

After the semiconductor layer 22 is patterned as described above, the source region 22a and the drain region 22b are doped with n + impurities, and then the body region 22d is doped with a heterogeneous p + region. When a voltage is applied to the terminals (gates, drains, and sources), the excess hole h + in the source region 22a is removed to the body region 22d.

However, such a four-terminal body contact structure is pointed out as a problem because the body portion is located outside of the three-terminal structure, which inevitably increases in area compared to conventional three-terminal elements.                         

The device of the multi-channel structure is a structure for preventing floating body effects and kinks, which are problematic in polysilicon thin film transistors, or a structure having an area increase problem.

The multi-channel device of the conventional liquid crystal display device as described above has the following problems.

In general, low temperature process polycrystalline silicon thin film transistors (poly-Si TFTs) have been found for manufacturing liquid crystal displays (LCDs) having integrated circuits (drivers) on large area glass substrates.

The low-temperature process polycrystalline silicon thin film transistor is formed in both the pixel portion and the driving portion of the glass substrate, and the liquid crystal display device formed in the driving portion is formed of a multi-channel element, so that heat is concentrated on one semiconductor layer in the wide element. To prevent.

On the other hand, in such a large-area substrate, in order to improve the efficiency of the driving unit of the liquid crystal display including the multi-channel elements, the mobility of each thin film transistor constituting the multi-channel element should be improved, and the threshold voltage Vth is reduced. The size of the thin film transistor should be reduced.

However, when the size of the thin film transistor is reduced, a phenomenon in which the semiconductor layer of the thin film transistor is self heating occurs under a stress state in which a high voltage is applied to the gate voltage and the drain voltage. Severe cases are observed above 300 ° C., in particular, such self heating is more severely observed in the center of the multichannel device.                         

The semiconductor layer of the thin film transistor constituting the multichannel device of the conventional liquid crystal display device is surrounded by SiO ₂ having a very low thermal conductivity.

When the multi-channel device is operated, heat is inevitably generated, and it is recognized that the heat generated at this time is due to the applied power (Ids × Vds). Therefore, the semiconductor layer of the thin film transistor surrounded by the oxide film (SiO ₂ ) having low thermal conductivity does not escape heat to form a heat island by itself.

As described above, heat generated in the semiconductor layer of the thin film transistor is severely identified as 300 ° C. or higher, which is known to be caused by device degradation including cracking of silicon-hydrogen bonding (Si-H bonding).

In particular, the center of the multi-channel device heat is concentrated compared to both ends of the multi-channel device, the highest temperature is observed, the heat damage with concentric circles long in the width direction occurs at this site. As a result, it is known that heat dissipation at the center of the multichannel device is difficult.

Each thin film transistor constituting a conventional multichannel device is a thin film transistor of a general three terminals (gate, drain, source), and the three terminal thin film transistor has a low threshold voltage (Vth) due to an increase in the hole concentration near the source region. Loss introduces a new problem, the floating body effect.

In addition, reducing the threshold voltage (Vth) increases the amount of electrons contributing to the drain avalanche, which in turn increases the generation of holes and, in turn, increases the positive feed back with source barrier lowering. feed back), which presents a problem of device reliability in long time operation.

Overcoming such deterioration of device characteristics due to the floating body effect is a problem in the case of application of a short channel device, and is an important reliability item that must be overcome in order to implement a polysilicon panel.

In order to solve the floating body effect, a four-terminal thin film transistor structure in which a source and a body are contacted and grounded is selected. In this case, a large area thin film transistor is formed. In particular, when the four-terminal thin film transistors are formed in parallel to form a device to prevent heating, the problem due to the large area becomes worse.

The present invention has been made to solve the above problems, by changing the shape of the semiconductor layer when the device is patterned, self heating (floating body effect), floating body effect (particularly a problem in the wide width device) And a multi-channel element of a liquid crystal display device having improved kink effect, and a method of manufacturing the same.

The multi-channel device of the liquid crystal display device of the present invention for achieving the above object is a substrate, a plurality of first semiconductor layers arranged at regular intervals on the substrate, and a gate metal layer across the first semiconductor layers And source and drain metal layers spaced apart from both sides of the gate metal layer at both ends of the first semiconductor layers in the same direction as the gate metal layer, and first impurities defined in the first semiconductor layers on both sides of the gate metal layer. A second semiconductor layer integrally formed with the first semiconductor layers between the layer, a portion of the gate metal layer, and a source metal layer, and the second impurity layer formed in the second semiconductor layer. Its features are made to include.

The first semiconductor layers have the same width.

The second semiconductor layers have the widest width at the center of the multichannel device and the relatively narrow width at the outer portion.

The width of the second semiconductor layer positioned at the center of the multichannel device among the second semiconductor layers is larger than the width of the first semiconductor layer.

The second semiconductor layers are the same width.

The second semiconductor layers are the same as or larger than the first impurity layer on one side of the first semiconductor layers, and are equal to or smaller than the sum of the longitudinal lengths of the first impurity layer and the gate metal layer of the first semiconductor layer.

The second semiconductor layers have a length of one half of the first semiconductor layers.

The first impurity layer is an n + type doped layer, and the second impurity layer is a p + doped layer.

The first impurity layer is a p + type doping layer, and the second impurity layer is an n + type doping layer.

The first impurity layer is in contact with the source / drain metal layer, and the second impurity layer is in contact with the source metal layer.

An interval between the second impurity layer and the first impurity layer is smaller than 1/2 of an interval between the second semiconductor layer.                     

An interval between the second impurity layer and the gate metal layer is 3 μm or less.

In addition, the multi-channel device of the liquid crystal display device of the present invention for achieving the same object includes a substrate, a plurality of first semiconductor layers arranged to be spaced apart from each other with a relatively large distance from the center portion, A gate metal layer crossing the first semiconductor layers, a source metal layer and a drain metal layer formed across the first semiconductor layers on both sides of the gate metal layer, and a first semiconductor layer defined on both sides of the gate metal layer A second semiconductor layer integrally formed with the first semiconductor layers between the impurity layer, a portion of the gate metal layer, and a source metal layer and spaced apart from the first semiconductor layers, and a second impurity formed in the second semiconductor layer Another feature is that it comprises a layer.

The first semiconductor layers are formed to have the same width.

The first impurity layer is in contact with the source metal layer and the drain metal layer, respectively, and the second impurity layer is in contact with the source metal layer.

In addition, a method of manufacturing a multi-channel device of a liquid crystal display of the present invention for achieving the same object is defined by being divided into a first region and a second region on both sides of the substrate in a predetermined direction, respectively, Forming a first semiconductor layer, a second semiconductor layer integral with the first region of the first semiconductor layers, forming a gate insulating film on the entire surface of the substrate including the first and second semiconductor layers, and Forming a gate metal layer in a direction crossing the center of the first semiconductor layer, implanting first type ions into the first and second regions of the first semiconductor layer to form a first impurity layer, and Implanting ions of a second type into a predetermined region of the second semiconductor layer to form a second impurity layer, depositing an interlayer insulating film over the gate insulating film including the gate metal layer; Forming a contact hole by removing the interlayer insulating layer to expose predetermined portions of the first impurity layer and the second impurity layer in the first and second regions, and filling the contact hole and paralleling the gate metal layer. Another feature is that the method includes forming a source metal layer and a drain metal layer on the interlayer insulating layer so as to pass through both sides of the layers.

The first semiconductor layers are formed to have the same width.

The second semiconductor layers are formed to have the widest width at the center of the multi-channel device and the relatively narrow width at the outer portion.

The width of the second semiconductor layer positioned at the center of the multichannel device among the second semiconductor layers is greater than the width of the first semiconductor layer.

The second semiconductor layers are formed to have the same width.

The second semiconductor layers may be formed to be equal to or larger than a first impurity layer on one side of the first semiconductor layers, and to be equal to or smaller than the sum of the longitudinal lengths of the first impurity layer and the gate metal layer of the first semiconductor layer.

The second semiconductor layers have a length of one half of the first semiconductor layers.

First and second regions of the first semiconductor layer are defined at both sides of the gate metal layer.

The second impurity layer is spaced apart from each other by less than 1/2 of the width of the first semiconductor layer and the second semiconductor layer, and is spaced apart from the gate metal layer by 3 μm or less.

Hereinafter, a multichannel device and a manufacturing method thereof of the liquid crystal display of the present invention will be described in detail with reference to the accompanying drawings.

14 is a circuit diagram illustrating a state in which four terminal devices having a body contact are connected in parallel.

The multi-channel device of the liquid crystal display of the present invention is a four-terminal thin film transistor, as shown in FIG. 14, thus forming the device with four terminals of a gate, a drain, a source, and a body. The source is contacted to the body.

Here, in the multi-channel device of the liquid crystal display of the present invention, the second semiconductor layer is formed between the multi-channel devices, that is, between the first semiconductor layer of the source region, without defining an arbitrary space outside the device in the body region. Is further formed to define, by injecting impurities of a different type from the impurities injected into the first semiconductor layer in this region, to define the floating body effect and the kink effect without increasing the area of the device. It is possible to form a multi-channel device that can suppress the effect).

As described above, the reason why the device of the liquid crystal display is formed to have a plurality of multi-channels in the present invention is that when a wide width device is composed of a single transistor, In order to prevent a self heating phenomenon in which heat is concentrated on the panel, and to implement a wide device using a small size unit transistor formed in the liquid crystal panel. In this case, in order to prevent deepening of self-heating in the central portion of the multi-channel device, sufficient space between the thin film transistors is secured in the central portion, thereby widening the heat emission path to prevent damage to the device due to self-heating. You can prevent it.

In the multi-channel device of the liquid crystal display device of the present invention, a polysilicon layer is deposited, and in the liquid crystal display device using polysilicon as a semiconductor layer, a driving part, that is, a gate driving part and a data driving part is formed outside the pixel part of the liquid crystal panel. Is formed. This is to meet the demand of the device for driving with higher mobility and more stable.

Hereinafter, the multichannel device of the liquid crystal display of the present invention will be described with reference to the accompanying drawings.

First Embodiment

FIG. 15 is a plan view illustrating a multi-channel device of a liquid crystal display according to a first exemplary embodiment of the present invention, FIG. 16 is a cross-sectional view taken along the line VV ′ of FIG. 15, and FIG. 17 is a line VI-VI ′ of FIG. 15. Fig. 18 is a structural cross sectional view taken along the line 'VIII' of Fig. 15, and Fig. 19 is a structural cross sectional view taken along the line XVIII 'of Fig. 15.

As shown in FIG. 15, in the multi-channel device of the liquid crystal display according to the first exemplary embodiment of the present invention, a plurality of thin film transistors are connected in parallel, a channel is formed in each thin film transistor, and each thin film transistor has four terminals (gates). It has a gate, a source, a drain, and a body.                     

When each of the thin film transistors is configured to have a common gate, a common drain, and a common source, the plurality of thin film transistors are configured in parallel. In addition, when the body of each thin film transistor is electrically connected to each source, and the source is grounded, holes in the source side exit through the body to float the floating body. Floating body effect is suppressed.

 As shown in FIGS. 15 to 19, a plurality of channel elements of the liquid crystal display according to the first exemplary embodiment in which four terminal elements are configured in parallel are spaced apart from each other in a predetermined direction on a substrate (not shown). Between the first semiconductor layer (see 110 in FIG. 20A) and the first semiconductor layers 110 adjacent to each other, one half of the first semiconductor layer 110 is formed from one side of the first semiconductor layer 110. The formed second semiconductor layer (see 111 in FIG. 20A), the gate metal layer 104 crossing the center of the first semiconductor layers 110, and the gate metal layer 104 in parallel with the gate metal layer 104. And a source metal layer 107 and a drain metal layer 108 spaced apart at predetermined intervals from both sides.

In the first semiconductor layer 110, first impurity layers 102a-source region and 102b-drain region are defined on both sides of the gate metal layer 104, and in the second semiconductor layer 111. And a second type impurity layer 112 defined at a predetermined portion. At this time, regions of the remaining undoped semiconductor layers of the first and second semiconductor layers 110 and 111 remain as intrinsic semiconductor regions 102. In this case, the channel region is the intrinsic semiconductor region 102 in the first semiconductor layer 110, and the region except the second type impurity layer 112 is in the second semiconductor layer 111.

In the first embodiment, each of the first semiconductor layers 110 is formed to have the same width, and each of the second semiconductor layers 111 is also formed to have the same width.

In this case, the length of the second semiconductor layer 111 is approximately 1/2 of the first semiconductor layer 110, and the source region of the first semiconductor layer 110 is not defined to be exactly 1/2. It is equal to or larger than 102a and is determined at a level equal to or less than the sum of the source region 102a and the gate metal layer 104 of the first semiconductor layer 110.

The first impurity layers 102a and 102b and the second impurity layer 112 are impurity layers doped with ions of different types. When the first impurity layers 102a and 102b are n + type doping layers and the second impurity layer is p + doping layers, the multichannel elements of the liquid crystal display according to the first exemplary embodiment of the present invention are formed as n-channel elements. When the first impurity layers 102 and 120b are p + type doped layers and the second impurity layer 112 is n + type doped layers, the first impurity layers 102 and 120b are formed of p-channel elements.

Here, the source metal layer 107 and the drain metal layer 108 are formed to be spaced apart from each other by the gate metal layer 104. The source metal layer 107 contacts the source region 102a of the first semiconductor layer 110 and the second impurity layer 112 of the second semiconductor layer 111, respectively, and the drain metal layer 108. Is in contact with the drain region 102b of the first semiconductor layer 110. In this case, contact between the second impurity layer 112 of the second semiconductor layer 111 and the source metal layer 107 is referred to as a body contact. In addition, the metal layer of the site | part used as a contact is called an electrode. Accordingly, the source metal layer in contact with the source region 102a of the first semiconductor layer 110 may be a source electrode 107a and the drain metal layer in contact with the drain region 102b of the first semiconductor layer 110 may be a drain electrode. (108a).

As shown, the body contact of the multi-channel device of the liquid crystal display according to the first embodiment of the present invention is not in the outside of the multi-channel device, but in the space between the thin film transistors forming the multi-channel device. Form. Therefore, the body contact is made without increasing the area to suppress the floating body effect and the kink effect.

Meanwhile, an interval between the second impurity layer 112 and the source region 102a is smaller than 1/2 of an interval between the second semiconductor layer 111 and the second impurity layer 112 and the gate metal layer ( The spacing between 104) is 3 μm or less. Therefore, the second impurity layer 112 is formed in the second semiconductor layer 111 without overlapping with the gate metal layer 104.

The first type impurity layer 102a of the source region is in contact with the source metal layer 107 to form a source contact 119, and the first type impurity layer 102b of the drain region is the drain metal layer. The second impurity layer 112 is in contact with the 108 to form a drain contact, and the second impurity layer 112 is in contact with the source metal layer, respectively, to form a body contact.

An intrinsic semiconductor region 102 serving as a channel is positioned between the source region 102a and the drain region 102b of the first semiconductor layer 110. The sum of the widths of the channels of the plurality of first semiconductor layers 110 is the total width of the multichannel devices of the liquid crystal display according to the first embodiment of the present invention.

The multi-channel elements of the liquid crystal display of the present invention are formed at the same time in the TFT array forming process, and the above-described object can be achieved by changing the patterning between layers in a general TFT array forming process without adding a separate process. Can be. Here, the TFT manufactured during TFT array formation is a polysilicon type in which a semiconductor layer is crystallized through a laser, and the elements of the driving unit are formed in the panel together with the elements in the array.

Here, the first semiconductor layers 110 and the second semiconductor layers 111 are all formed by one patterning process, and the first impurity layer 102a, by using the gate metal layer 104 and a predetermined mask, respectively. 102b) and the second impurity layer 112 are formed.

Here, the buffer layer 101 is formed under the first and second semiconductor layers 110 and 111 on the substrate 100. The first semiconductor layer 111 is provided with a source region 102a and a drain region 102b of the first impurity layer defined on both sides of the intrinsic semiconductor region 102 functioning as a channel at the center. The second semiconductor layer 112 is provided with the second impurity layer 112 defined in a predetermined region.

A front gate insulating layer 103 is interposed between the first and second semiconductor layers 110 and 111 and the gate metal layer 104, and the gate metal layer 104 and the source / drain metal layers 107 and 108 are deposited. An interlayer insulating layer 105 is interposed therebetween, and a passivation layer is entirely deposited on the source / drain metal layers 107 and 108.

The gate metal layer 104, the source metal layer 107, and the drain metal layer 108 overlap the gate metal layer 104, the source electrode 107a, and the drain electrode 108a. This is called.

The first semiconductor layer 110 and the electrodes 104a, 107a, and 108a overlapping each other form a thin film transistor, and the plurality of thin film transistors are connected in parallel to each other.

Meanwhile, regions in which the first and second impurity layers 102a, 102b, and 112 are not defined in the first and first semiconductor layers 110 and 111 remain as intrinsic semiconductor layer 102 regions due to impurity doping. .

Hereinafter, a method of manufacturing a multichannel device of a liquid crystal display according to a first embodiment of the present invention will be described with reference to the drawings.

20A to 20F are process plan views illustrating a method of manufacturing a multichannel device of a liquid crystal display according to a first exemplary embodiment of the present invention, and FIGS. 21A to 21F are cross-sectional views of respective processes of FIGS. 20A to 20F.

In the method of manufacturing a multi-channel device of the liquid crystal display according to the first exemplary embodiment of the present invention, first, as shown in FIGS. 20A and 21A, the buffer layer 101 is entirely deposited on the substrate 100.

Subsequently, after depositing an amorphous silicon layer on the buffer layer 101, the polysilicon layer is formed by crystallization using a laser or the like.

Subsequently, the polysilicon layer may be selectively removed to separate the plurality of first semiconductor layers 110 spaced apart from each other in a predetermined direction, and the second semiconductor layer 111 integral with one side of the first semiconductor layer 111. Form. Here, the widths of the plurality of first semiconductor layers 110 are the same as W, and the liquid crystal display according to the first exemplary embodiment of the present invention has a value 4W, which is the sum of the widths of the first semiconductor layers 110. Corresponds to the total width of the multichannel device. In some cases, different widths of the first semiconductor layer 111 may be formed. In this case, the sum of the widths of the first semiconductor layers 111 corresponds to the total width of the multi-channel device. However, when different widths of the first semiconductor layer are formed, self-heating appears for each device, and in consideration of the severe self-heating at the central portion, the self-heating of the first semiconductor layer is considerably different from that of the first semiconductor layer located at the outer portion. 1 The width of the semiconductor layer should not be large.

Here, the second semiconductor layer 111 is formed between the first semiconductor layer 111, the length is half the value of the first semiconductor layer 111, the first semiconductor layer ( 111 is formed to be biased to one side.

Next, as shown in FIG. 21B, the gate insulating layer 103 is formed on the entire surface of the substrate 100 including the first and second semiconductor layers 110 and 111. The first and second semiconductor layers 110 and 111 are both intrinsic poly-silicon regions in which impurities are not injected.

Subsequently, as shown in FIG. 20B, the metal layer is entirely deposited on the entire surface of the substrate 100 including the first semiconductor layers 110 and then selectively removed to cross the center of the first semiconductor layer 110. The gate metal layer 104 is formed.                     

20C and 21C, a photoresist layer is deposited on the gate insulating layer 103, and the photoresist layer is exposed and developed to form a first photoresist layer pattern 121 covering the second semiconductor layer 111. . Using the first photoresist pattern 121 as a mask, ions of a first type are implanted into the first and second regions of the first semiconductor layer 110 to the source region 102a and the drain region 102b, respectively. A first type impurity layer defined is formed.

Next, the first photoresist film pattern 121 is peeled off.

Next, as shown in FIGS. 20D and 21D, a photoresist is deposited on the gate insulating layer 103, and the photosensitive layer is exposed and developed to cover predetermined portions of the first semiconductor layer 110 and the second semiconductor layer 111. A second photosensitive film pattern 122 is formed. Subsequently, a second type impurity layer 112 is formed by implanting a second type of ion into the second semiconductor layer 111 using the second photoresist pattern 122 as a mask. Here, the first type impurity layers 102a and 102b are n + type, and the second type impurity layer 112 is p + type.

Next, the second photoresist pattern 122 is peeled off.

20E and 21E, an interlayer insulating layer 105 is deposited on the gate insulating layer 103 including the gate metal layer 104.

Next, second contact holes exposing predetermined regions of the source region 102a and the drain region 102b of the first semiconductor layer 110 by selectively removing the interlayer insulating layer 105 and the gate insulating layer 103. 119, a third contact hole 120, and a first contact hole 118 exposing a predetermined portion of the second impurity layer 112 of the second semiconductor layer 111.

20F and 21F, by depositing a metal layer on the entire surface of the substrate 100 including the interlayer insulating layer 105 and filling the first to third contact holes 118, 119 and 120, and selectively removing it, A source metal layer 107 and a drain metal layer 108 are formed to cross both sides of the gate metal layer 104 in a direction parallel to the gate metal layer 104.

Next, a passivation layer 106 is formed on the interlayer insulating layer 105 including the source metal layer 107 and the drain metal layer 108.

The second type impurity layer 112 of the second semiconductor layer 111 may be spaced apart from the first semiconductor layer 110 by less than 1/2 of the width of the second semiconductor layer 111. It is spaced within 3 μm from the metal layer 104. In this case, when the second type impurity layer 112 is the largest, it corresponds to the area of the second semiconductor layer 111.

In the multi-channel device of the liquid crystal display of the present invention manufactured by the above method, when the voltages Vg and Vd are applied to the gate electrode 104a and the drain electrode 108a, respectively, the drain region 102b of the semiconductor layer 102. ) And a channel is formed in the intrinsic semiconductor region 102 between the source region 102a. That is, the movement of the electron (e-) from the source region 102a to the drain region 102b and the movement of the hole h + from the drain region 102b to the source region 102a occur.

At this time, the electrons e- are accelerated by applying the bias voltages Vg and Vd to generate a drain avalanche in which a large amount of electrons e- and holes h + are generated in the drain region 102b. In addition, the generated electron (e−) exits to the drain electrode 108a, and the hole h passes through the channel to the source electrode 107a.                     

In this case, a body, which is the second semiconductor layer 111 adjacent to the source electrode 107a, is formed in contact with the side of the n + type source region 102a, and the source region of the second semiconductor layer 111 is formed. The second impurity layer 112 doped with 102a and a heterogeneous p + type is in contact with the source metal layer 107 to be electrically connected to the source electrode 107a and to ground the source electrode 107a. Holes accumulated in the body are pulled out to the ground through the source electrode 107a.

In this case, excess holes do not accumulate in adjacent portions of the source region 102a due to the contact between the body and the source electrode 107a, and the floating body effect does not occur due to escape to the source electrode 107a side. The kink effect caused by the floating body effect is also prevented.

Therefore, device reliability is improved and the device can be driven for a long time.

Second Embodiment

FIG. 22 is a plan view illustrating a multi-channel device of a liquid crystal display according to a second exemplary embodiment of the present invention, FIG. 23 is a plan view showing the semiconductor layer of FIG. 22, and FIG. 24 is a view showing the semiconductor layer and impurity layer thereof of FIG. 22. It is the top view shown.

As shown in FIGS. 22 and 23, the multichannel device of the liquid crystal display according to the second exemplary embodiment of the present invention, as in the first embodiment, connects a plurality of thin film transistors having the same width and the same spacing in parallel to the multichannel device. Is a structure to solve the phenomenon in which the self heating phenomenon is intensified in the central part where heat dissipation paths are difficult to form during long time driving, and the width of the second semiconductor layer 211, that is, the separation distance between the first semiconductor layers 210. Form differently in the center and the outer part.

In this case, the second semiconductor layers 211 are formed to have a wider width D ₂ at the central portion and a relatively smaller width D ₁ <D _{2 at the} outer portion. In this case, each of the plurality of first semiconductor layers 210 is formed to have the same width, and the second semiconductor layer 211 at the central portion is formed to have a width larger than that of one of the first semiconductor layers 210.

In addition, the multi-channel device of the liquid crystal display according to the second embodiment follows the same conditions as the first embodiment except for the width condition of the second semiconductor layer.

Hereinafter, a multichannel element of the liquid crystal display according to the second embodiment will be described in detail with reference to the drawings.

As shown in FIGS. 22 to 24, a multi-channel device of a liquid crystal display according to a second exemplary embodiment of the present invention may include a plurality of first semiconductor layers formed on a substrate (not shown) and spaced apart from each other in a predetermined direction. 23, 210) and between the adjacent first semiconductor layers 210 are formed to have a length 1/2 of the first semiconductor layer 210 from one side of the first semiconductor layer 210 and relatively at the center thereof. A second semiconductor layer (see 211 of FIG. 23) formed at a wider width and relatively narrow at an outer side thereof, a gate metal layer 204 crossing the center of the first semiconductor layers 210, and the gate And a source metal layer 207 and a drain metal layer 208 spaced apart from the gate metal layer 204 to both sides in parallel with the metal layer 204.                     

Here, first type impurity layers 202a-source region and 202b-drain region are defined in both sides of the gate metal layer 204 in the first semiconductor layer 210, and in the second semiconductor layer 211. And a second type impurity layer 212 defined at a predetermined portion. At this time, regions of the remaining undoped semiconductor layers of the first and second semiconductor layers 210 and 211 remain as intrinsic semiconductor regions 202. In this case, the channel region is the intrinsic semiconductor region 202 in the first semiconductor layer 210, and the region except the second type impurity layer 212 is in the second semiconductor layer 211.

The multichannel device of the liquid crystal display according to the second exemplary embodiment of the present invention is an intrinsic semiconductor layer as shown in FIG. 23 immediately after patterning of the first and second semiconductor layers. Subsequently, as shown in FIG. 24, after depositing a gate metal layer in a direction crossing the center of the first semiconductor layer, a first impurity is implanted into the first semiconductor layer using the gate metal layer together with a predetermined photoresist pattern. After the source region 202a and the drain region 202b are defined, and a second impurity layer 212 (body region) is defined by injecting a second impurity into the second semiconductor layer, the first and second semiconductor layers are first and second. Impurity layers are formed respectively.

In the second embodiment, each of the first semiconductor layers 210 is formed to have the same width, but are formed to have different widths in the outer and central regions of each of the second semiconductor layers 211.

In this case, the length of the second semiconductor layer 211 is approximately 1/2 of the first semiconductor layer 210, but is not limited to exactly 1/2, and the source region of the first semiconductor layer 210 is defined. 202a is determined between the sum of the source region 102a and the gate metal layer 104 of the first semiconductor layer 110.

In addition, the first impurity layers 202a and 202b and the second impurity layer 212 are impurity layers doped with ions of different types. When the first impurity layers 202a and 202b are n + doped layers and the second impurity layer is p + doped layers, the multichannel elements of the liquid crystal display according to the first exemplary embodiment of the present invention are formed as n-channel elements. When the first impurity layers 202a and 202b are p + type doping layers and the second impurity layer 212 is n + type doping layers, the first impurity layers 202a and 202b are formed of p-channel elements.

Here, the source metal layer 207 and the drain metal layer 208 are formed spaced apart from each other by the gate metal layer 204. The source metal layer 207 contacts the source region 202a of the first semiconductor layer 210 and the second impurity layer 212 of the second semiconductor layer 211, respectively, and the drain metal layer 208. Is in contact with the drain region 102b of the first semiconductor layer 110. In this case, contact between the second impurity layer 212 of the second semiconductor layer 211 and the source metal layer 207 is referred to as body contact.

In the second embodiment, like the first embodiment, the body contact of the multichannel elements of the liquid crystal display device is formed not in the outside of the multichannel elements, but in the interspace of each thin film transistor constituting the multichannel elements. do. Therefore, the body contact is made without increasing the area to suppress the floating body effect and the kink effect.

Meanwhile, an interval between the second impurity layer 212 and the source region 202a is less than half of an interval between the second semiconductor layer 211 and the second impurity layer 212 and the gate metal layer. The interval between 204 is 3 micrometers or less. Thus, the second impurity layer 212 is formed in the second semiconductor layer 211 without overlapping with the gate metal layer 204.

The source region 202a is in contact with the source metal layer 207 to form a source contact 219, and the drain region 202b is in contact with the drain metal layer 208 to form a drain contact. 220, the second impurity layer 212 is in contact with the source metal layer 207 to form a body contact 218.

After the impurity ion doping, as shown in FIG. 24, an intrinsic semiconductor region 202 serving as a channel is positioned between the source region 202a and the drain region 202b of the first semiconductor layer 210. The sum of the widths of the channels of the plurality of first semiconductor layers 210 is the total width of the multichannel devices of the liquid crystal display according to the second exemplary embodiment. Each channel width of each of the plurality of first semiconductor layers 210 is formed as in the first embodiment, and the width of each region of the second semiconductor layer 211 is varied so that the multichannels of the liquid crystal display of the second embodiment are provided. An element can be formed.

And, as in the first embodiment, the multichannel elements of the liquid crystal display according to the second embodiment of the present invention are formed at the same time in the TFT array forming process. By changing the patterning between the layers, the above object can be achieved. Here, the TFT manufactured during TFT array formation is a polysilicon type in which a semiconductor layer is crystallized through a laser, and the elements of the driving unit are formed in the panel together with the elements in the array.

Here, the first semiconductor layers 210 and the second semiconductor layers 211 are all formed in one patterning process, and the first impurity layer 202a, the gate metal layer 204 and a predetermined mask, respectively, are formed. 202b and the second impurity layer 212 are formed. That is, the impurity doping process is performed through two mask processes.

In the method for manufacturing a multi-channel device of the liquid crystal display according to the second embodiment of the present invention, the multi-channel device of the liquid crystal display according to the first embodiment is manufactured except for the width of the second semiconductor layer 211. Follow the method.

The multi-channel device of the liquid crystal display of the present invention described in the above embodiments is a device formed in the driving unit of the liquid crystal panel on which the polysilicon layer is deposited, and is a wide width transistor for implementing a high speed.

Such large devices have a problem in that electrical characteristics are deteriorated by Joule heat generated during long time operation. This is called heat generated by the device itself and is called self heating.

In order to solve the above self-heating, in the present invention, a plurality of devices are formed to be spaced apart at predetermined intervals to form a space in which heat between the devices and the elements escape, and in addition, a semiconductor layer including an impurity layer between the devices and the devices. By defining the body region, the thermal conductivity is high, so that the heat escapes quickly. In addition, the self-heating is intensified in the center of the multi-channel device. Minimize degradation.

In addition, through the structure having the body region, the effect of minimizing the floating body effect and the kink effect by the drain avalanche can also be obtained. In this case, the body region is defined inside the region defined as the multichannel device, that is, between the unit transistors constituting the multichannel device, thereby obtaining the above-described effect without increasing the area.

As described above, the multichannel device and the manufacturing method thereof of the liquid crystal display of the present invention have the following effects.

First, in the multi-channel device of the liquid crystal display of the present invention, a plurality of thin film transistors are connected in parallel to form multiple channels, each thin film transistor is formed into four terminals, and the source and body of each thin film transistor are contacted. By injecting source and heterogeneous impurities into the body, it is possible to quickly remove excess holes accumulated in the body when the source side is grounded, thereby suppressing the floating body effect, thereby allowing a threshold voltage (Vth). The fall phenomenon can be prevented.

Second, when the threshold voltage value is applied to the gate voltage of a predetermined value or more can be maintained in the saturation state, the conventional thin film transistor is a constant time of the thin film transistor, as compared with the gain is continuously dropped after a certain time, the output impedance is lowered The gain can be maintained, the kink effect is prevented at the source, and the effect of increasing the output impedance can be obtained.                     

Third, by partially expanding the semiconductor layer and injecting ions of a type different from the type of the thin film transistor to a predetermined portion of the extended region without the addition of a separate mask process to form a 4-terminal thin film transistor constituting the device. The body contact can be made, and the process is simple.

Fourth, unlike a general multichannel device structure, a second semiconductor layer integral with a first semiconductor layer constituting an element is further formed in a space between each device constituting the multichannel element, and a body region is defined thereby. In the channel device structure, a semiconductor layer having a high thermal conductivity is positioned as compared with a structure in which an oxide film is disposed between the device and the device, thereby preventing self heating.

Fifth, considering that the self heating is particularly severe in the center of the multichannel device, the body region, i.e., the width of the second semiconductor layer is formed in the center of the multichannel device, and the heat dissipation path is extended so that the self heating is effective. This can prevent deterioration and improve the reliability of the device.

Claims (24)

Board; A plurality of first semiconductor layers arranged on the substrate at predetermined intervals; A gate metal layer crossing the first semiconductor layers; A source metal layer and a drain metal layer spaced apart from both sides of the gate metal layer at both ends of the first semiconductor layers in the same direction as the gate metal layer; First impurity layers defined in the first semiconductor layers on both sides of the gate metal layer and in contact with the source metal layer and the drain metal layer, respectively; A second semiconductor layer corresponding to the gate metal layer and the source metal layer and integrally formed with the first semiconductor layers between the first semiconductor layers spaced apart from each other; And And a second impurity layer formed in contact with the source metal layer in the second semiconductor layer, the second impurity layer having a different conductivity type from that of the first impurity layer. The method of claim 1, The first semiconductor layers have the same width, the multi-channel device of the liquid crystal display device. 3. The method of claim 2, The second semiconductor layers have the widest width at the center of the multi-channel device and a relatively narrow width at the outer portion of the multi-channel device. The method of claim 3, The width of the second semiconductor layer located in the center of the multi-channel device of the second semiconductor layer is larger than the width of the first semiconductor layer, the multi-channel device of the liquid crystal display device. 3. The method of claim 2, And the second semiconductor layers have the same width. The method of claim 1, The second semiconductor layers may be the same as or greater than the first impurity layer on one side of the first semiconductor layers, and the same as or less than the sum of the longitudinal lengths of the first impurity layer and the gate metal layer of the first semiconductor layer. Multichannel device in the device. The method of claim 6, And the second semiconductor layers have a length of 1/2 of the first semiconductor layers. The method of claim 1, Wherein the first impurity layer is an n + type doping layer and the second impurity layer is a p + doping layer. The method of claim 1, Wherein the first impurity layer is a p + type doping layer, and the second impurity layer is an n + type doping layer. delete The method of claim 1, The gap between the second impurity layer and the first impurity layer is less than half of the distance between the second semiconductor layers. The method of claim 1, The gap between the second impurity layer and the gate metal layer is greater than 0 µm and less than or equal to 3 µm. Board; A plurality of first semiconductor layers arranged on the substrate to be spaced apart from each other so as to have a relatively wide distance from the center portion; A gate metal layer crossing the first semiconductor layers; A source metal layer and a drain metal layer formed on both sides of the gate metal layer to cross the first semiconductor layers; First impurity layers defined on the first semiconductor layer in contact with the source metal layer and the drain metal layer, respectively, on both sides of the gate metal layer; A second semiconductor layer corresponding to the gate metal layer and the source metal layer and integrally formed with the first semiconductor layers between spaced first semiconductor layers; And And a second impurity layer formed in contact with the source metal layer in the second semiconductor layer. The method of claim 13, The first semiconductor layers are formed to have the same width multi-channel device of the liquid crystal display device. delete A plurality of first semiconductor layers spaced in one direction on the substrate and spaced apart from each other by being defined as a first region and a second region on both sides of the center, and integral with the first region of the first semiconductor layers Forming a second semiconductor layer; Forming a gate insulating film on an entire surface of the substrate including the first and second semiconductor layers; Forming a gate metal layer in a direction crossing the center of the first semiconductor layer; Implanting ions of a first type into first and second regions of the first semiconductor layer to form a first impurity layer; Implanting ions of a second type of conductivity type different from the first type into the second semiconductor layer to form a second impurity layer; Depositing an interlayer insulating film over the entire gate insulating film including the gate metal layer; Forming a contact hole by removing the interlayer insulating layer to expose the first impurity layer and the second impurity layer in the first and second regions; The first impurity layer contacts the source metal layer and the drain metal layer, respectively, and the second impurity layer contacts the source metal layer by filling the contact hole and passing both sides of the semiconductor layers in parallel with the gate metal layer. And forming a source metal layer and a drain metal layer on the interlayer insulating film. The method of claim 16, The first semiconductor layers are formed to have the same width, the method of manufacturing a multi-channel device of the liquid crystal display device. The method of claim 17, And the second semiconductor layers are formed to have a widest width at the center of the multichannel device and a relatively narrow width at the outer portion of the multichannel device. The method of claim 18, The width of the second semiconductor layer located in the center of the multi-channel device of the second semiconductor layer is formed to be larger than the width of the first semiconductor layer, the manufacturing method of the multi-channel device of the liquid crystal display device. The method of claim 17, The second semiconductor layers are formed in the same width, the method of manufacturing a multi-channel device of the liquid crystal display device. The method of claim 16, The second semiconductor layers may be formed to be equal to or larger than a first impurity layer on one side of the first semiconductor layers, and to be equal to or smaller than the sum of the longitudinal lengths of the first impurity layer and the gate metal layer of the first semiconductor layer. The manufacturing method of the multichannel element of a liquid crystal display device. The method of claim 21, And the second semiconductor layers have a length of 1/2 of the first semiconductor layers. The method of claim 16, The first and second regions of the first semiconductor layer are defined on both sides of the gate metal layer, the method of manufacturing a multi-channel device of the liquid crystal display device. The method of claim 16, The second impurity layer is spaced apart from each other by less than half of the width of the first semiconductor layer and the second semiconductor layer, the liquid crystal display, characterized in that formed larger than 0㎛, 3㎛ or less from the gate metal layer A method of making a multichannel device of an apparatus.

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