KR101046692B1 - Method of manufacturing vertical channel semiconductor device - Google Patents

Abstract

The present invention is to provide a method for manufacturing a vertical channel semiconductor device for preventing the pillar (pillar) collapse, the present invention for forming a hard mask film having an opening for opening the substrate on the substrate, and the hard mask Etching the substrate using a film as a mask to define an offset region, forming spacers on side surfaces of the hard mask film and the offset region, etching the substrate using the hard mask film and the spacer as a mask to form a pillar, Forming a pillar oxide having a width narrower than that of the offset region by oxidizing the substrate exposed by the hard mask layer and the spacer mask to form a thermal oxide layer, and removing the thermal oxide layer. A method of manufacturing a channel semiconductor device is provided.

Vertical channel, pillar, pillar neck, thermal oxide

Description

Manufacturing Method of Vertical Channel Semiconductor Device {METHOD FOR FABRICATING VERTICAL CHANNEL SEMICONDUCTOR DEVICE}

TECHNICAL FIELD The present invention relates to semiconductor technology, and more particularly, to a method of manufacturing a vertical channel semiconductor device.

As the degree of integration of semiconductor devices increases, the size of the MOS transistors, that is, the channel lengths of the MOS transistors, are reduced in order to integrate a larger number of devices in a limited space. However, when the channel length of the MOS transistor is reduced in this way, the degree of integration of the semiconductor device is increased, but the drain induced barrier lowering (DIBL), the hot carrier effect and the punch through are used. Likewise, a short channel effect that abnormally drives the semiconductor device is generated. Currently, in order to prevent short channel effects, various methods, such as a method of reducing the depth of the junction region and a method of extending the channel length by forming a groove in the channel region, have been researched and developed.

By the way, in the case of a semiconductor memory device such as a dynamic random access memory (DRAM), an MOS transistor having a channel length below an exposure limit is required as the integration degree approaches a giga bit band. This makes it difficult to apply planar type MOS transistors that form source and drain on the same plane to virtual gigabit memory devices.

Accordingly, a vertical channel semiconductor device has been proposed in which a source and a drain are disposed above and below the gate electrode to induce a vertical channel.

1A to 1D are cross-sectional views illustrating a method of manufacturing a vertical channel semiconductor device according to the prior art.

First, as shown in FIG. 1A, the pad oxide layer 11 and the hard mask layer 12 are sequentially formed on the substrate 10, and the hard mask layer 12 and the portion of the substrate 10 are exposed. After the pad oxide layer 11 is patterned, the substrate 10 is etched to a relatively shallow depth using the patterned hard mask layer 12 as a mask to define the offset region 15A. The offset region 15A is a portion where a source or a drain is to be formed, and is formed at a height of about 100 to 500 ms.

Next, the protective film 13 is formed on the side surface of the offset area 15A.

Subsequently, as shown in FIG. 1B, the pillars 15 are formed by etching the substrate 10 to a depth of 800 to 1000 GPa using the hard mask layer 12 as a mask.

Subsequently, as shown in FIG. 1C, the substrate 10 is isotropically etched using the hard mask layer 12 and the protective layer 13 as a mask to fill the pillar 15 directly below the offset region 15A. 14). As an isotropic etching process, a dry etching process is used. Here, the pillar 15 portion having a width narrowed by the isotropic etching process is referred to as pillar neck 15B.

Subsequently, as shown in FIG. 1D, the gate insulating layer 16 is formed on the recess 14, and the conductive layer is filled in the recess 14 to form the gate electrode 17 surrounding the pillar neck 15B. do.

However, the above-described prior art has a problem that the pillar 15 collapses.

More specifically, as the isotropic etching process is used when forming the pillar neck 15B, the pillar neck 15B has a rounded side profile, and the portion where the pillar neck 15B CD is minimized becomes a weak point. (15) collapses.

In addition, a dry etching process is used as an isotropic etching process for forming the pillar neck 15B, and the pillar neck 15B is directly damaged by plasma used during the dry etching process, and thus the pillar ( 15) collapses.

On the other hand, during the isotropic etching process for forming the pillar neck 15B, it is very difficult to control the degree of side etching. Accordingly, the pillar that collapses is extremely difficult to uniformly adjust the thickness of the pillar neck 15B over the entire wafer. The number of (15) is large.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a vertical channel semiconductor device capable of preventing pillar collapse.

According to an aspect of the present invention, there is provided a hard mask layer having an opening for opening the substrate on a substrate, and etching the substrate using the hard mask layer as a mask to define an offset region. Forming a spacer on the side of the hard mask layer and the offset region, etching the substrate using the hard mask layer and the spacer as a mask to form a pillar, and forming the pillar and the spacer Forming a pillar neck having a narrower width than the offset region in the pillar below the offset region by oxidizing the substrate exposed with a mask to form a thermal oxide layer, and removing the thermal oxide layer. A method of manufacturing a channel semiconductor device is provided.

According to the present invention, since the substrate of the region where the pillar neck is to be formed is oxidized to form a thermal oxide film and the thermal oxide film is removed to form a pillar neck, the side profile of the pillar neck can be vertically formed, and the pillar is etched through the etching process. Compared to the case of forming the neck, damage to the pillar neck can be reduced, and the pillar neck formed on a single wafer can be formed with a uniform thickness. As a result, the possibility and degree of peeling of the peel are reduced, so that the reliability and yield of the semiconductor device can be improved.

In addition, the possibility and extent of the pillar collapse can be reduced, thereby maximizing the lateral depth of the depression which was difficult to increase due to the pillar collapse. Therefore, since the area of the gate electrode filled in the recess can be increased, the characteristics of the semiconductor device can be improved.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

2A through 2F are cross-sectional views illustrating a method of manufacturing a vertical channel semiconductor device according to an exemplary embodiment of the present invention.

First, as shown in FIG. 2A, the pad oxide layer 21 and the hard mask layer 22 are formed on the substrate 20, and the hard mask layer 22 is formed by a photolithography process so that a part of the substrate 20 is exposed. ) The pad oxide film 21 is patterned.

The pad oxide film 21 may be formed by growing a silicon oxide film SiO ₂ by a thermal oxidation method. The pad oxide film 21 preferably has a thickness of about 50 to 150 kPa. The hard mask film 22 may be formed of a silicon nitride film.

Subsequently, the substrate 20 is etched by the first depth H1 using the hard mask layer 22 as a mask to define the offset region 26A. Preferably, the first depth H1 is about 100 to 500 kPa.

Next, the first protective film 23 is formed on the entire surface.

The first passivation film 23 can be formed using an oxide film. The first protective layer 23 may be formed by a chemical vapor deposition (CVD) process, a plasma enhanced CVD (PECVD) process, an atomic layer deposition (ALD) process, or a high density plasma. Chemical vapor deposition (High Density CVD, HDCVD) processes can be used.

Subsequently, as shown in FIG. 2B, the first passivation layer 23 is etched to form a first spacer 23A on the side of the hard mask layer 22, the pad oxide layer 21, and the offset region 26A. do.

Next, the grooves 24 are formed in the substrate 20 directly below the first spacer 23A by isotropically etching the substrate 20 using the hard mask film 22 and the first spacer 23A as a mask. . As an isotropic etching process, a dry etching process or a wet etching process may be used.

The groove 24 is subsequently filled by the second spacer 25A made of a material having an etch selectivity with an oxide film, so that the first spacer 23A is attacked during the subsequent thermal oxide film 27 removing process (see FIG. 2F). In order to prevent the phenomenon, the etching time is adjusted so that the substrate 20 is not excessively etched when the recesses 24 are formed so that the recesses 24 may be completely filled by the second spacers 25A.

Subsequently, as shown in FIG. 2C, a second passivation layer 25 is formed on the entire surface.

The second passivation layer 25 may be formed to a thickness of about 70 to about 100 μs using an oxide film and a material having an etching selectivity with silicon, for example, a nitride film. As the method of forming the second protective film 25, a CVD process, a PECVD process, an ALD process, or an HDCVD process may be used.

In this case, the recess 24 is filled by the second passivation layer 25.

Next, as shown in FIG. 2D, the second passivation layer 25 is etched entirely to form the second spacer 25A in the side surface of the first spacer 23A and the groove 24, and then the hard mask layer. The pillars 26 are formed by etching the substrate 20 with a second depth H2, for example, about 800-1500 mm by using the 22 and the second spacers 25A as a mask.

Subsequently, as illustrated in FIG. 2E, the substrate 20 exposed by the thermal oxidation process is oxidized to form a thermal oxide film 27.

At this time, the thickness of the substrate 20 to be oxidized is about 15 to 17nm. Therefore, the thickness of the thermal oxide film 27 grown below the surface of the substrate 20 is about 15 to 17 nm. In addition, the thermal oxide film 27 is further grown on the surface of the substrate 20 by about 18 to 20 nm to form a total thickness of 33 to 37 nm.

A thermal oxide film 27 is also formed on the side of the pillar 26 below the offset region 26A, and thus a pillar neck 26B is formed below the offset region 26A having a reduced width compared to the offset region 26A. .

At this time, the thickness of the substrate 20 to be oxidized is uniformly adjusted regardless of its position. Thus, the pillar neck 26B has a vertical side profile, and the pillar neck 26B formed on a single wafer has a uniform thickness.

Subsequently, as shown in FIG. 2F, the thermal oxide film 27 is removed to form the depression 28 on the side of the pillar neck 26B.

The thermal oxide film 27 may be removed using a wet dip out process. HF may be used as an etching solution. At this time, since the first spacer 23A is protected by the second spacer 25A filled in the recess 24 in the lower portion thereof, the loss of the first spacer 23A by the etching solution does not occur.

Subsequently, although not shown, a gate insulating film is formed on the recess 28, a gate electrode is filled in the recess 28 to form a gate electrode surrounding the pillar neck 26B, and a pillar 26 is formed around the gate electrode. Source and drain regions are formed above and below). As a result, a channel perpendicular to the main surface of the substrate 20 is formed.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, in the above-described embodiment, only the case where the spacer is doubled is illustrated. However, the spacer may be formed in a single structure of the second spacer 25A. In this case, the step of forming the first spacer 23A and the step of forming the recess 24 may be omitted.

1A to 1D are cross-sectional views illustrating a method of manufacturing a vertical channel semiconductor device according to the prior art.

2A through 2F are cross-sectional views illustrating a method of manufacturing a vertical channel semiconductor device according to an exemplary embodiment of the present invention.

Description of the Related Art

20: substrate

21: pad oxide film

22: hard mask

23A, 25A: first and second spacer

24: groove

26: pillar

26A: Offset Area

26B: Pillar Neck

27: thermal oxide film

28: depression

Claims (9)

Forming a hard mask film having an opening for opening the substrate on the substrate; Defining an offset region by etching the substrate using the hard mask layer as a mask; Forming a spacer on side surfaces of the hard mask layer and the offset region; Forming a pillar by etching the substrate using the hard mask layer and the spacer as a mask; Forming a pillar neck having a width narrower than that of the offset region by forming a thermal oxide layer by oxidizing the substrate exposed by the hard mask layer and the spacer as a mask; Removing the thermal oxide film Method of manufacturing a vertical channel semiconductor device comprising a. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, And forming the spacer as a double layer of an oxide spacer and a nitride spacer. Claim 3 was abandoned when the setup registration fee was paid. 3. The method of claim 2, Forming the spacers on the sidewalls of the hard mask layer and the offset region; Forming a recess in the substrate under the oxide spacer; And forming the nitride film spacers in the sidewalls and the grooves of the oxide film spacers. Claim 4 was abandoned when the registration fee was paid. The method of claim 3, And forming the grooves by isotropically etching the substrate using the hard mask layer and the oxide spacer as a mask. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1, After removing the thermal oxide film, And filling a gate electrode through a gate insulating film in an indentation portion of the pillar neck exposed by removing the thermal oxide film. Claim 6 was abandoned when the registration fee was paid. The method of claim 1, And a thickness of the substrate oxidized when the thermal oxide film is formed is in a range of 15 to 17 nm. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 1, The method of manufacturing a vertical channel semiconductor device to form the thermal oxide film to a thickness of 33 to 37nm. Claim 8 was abandoned when the registration fee was paid. The method of claim 1, A method of manufacturing a vertical channel semiconductor device using a wet dip out process when removing the thermal oxide film. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 8, A method of manufacturing a vertical channel semiconductor device using HF as an etchant in the wet dip out process.

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