KR101046389B1 - Via buried method and through-electrode formation method of semiconductor package using same - Google Patents

Abstract

The present invention discloses a via filling method capable of filling vias having an aspect ratio of 5 or more without generation of voids, and a through-electrode forming method of a semiconductor package using the same, and the via filling method according to the present invention provides a method for forming vias in an underlying layer. step; Depositing a thin film for adsorption on the underlayer including the via; Adsorbing catalysts in a uniform distribution on the surface of the catalyst adsorption thin film; Performing a plasma treatment on a product in which the catalysts are adsorbed in a uniform distribution on the catalyst adsorption thin film so that the distribution of the catalysts is changed from an inlet portion of the via to a non-uniform distribution showing a higher distribution toward the bottom; And embedding a metal film in the via where the catalysts are adsorbed in a non-uniform distribution.

Description

Method for filling via and method forming through electrode of semiconductor package using the same}

The present invention relates to a method for manufacturing a semiconductor package, and more particularly, to a via filling method capable of filling vias having an aspect ratio of 5 or more without generation of voids, and a method of forming a through electrode of a semiconductor package using the same.

In general, the stack package has a weak point that the electrical signal exchange through the metal wire, the operation speed is slow, the deterioration of the electrical characteristics of each stacked chip due to the use of a large number of wires. In addition, the stack package has a large overall size because an additional area is required in the substrate for the connection of metal wires, and the overall thickness is thick because a gap (Gap) for wire bonding between stacked semiconductor chips is required.

Accordingly, a stack package structure using a through electrode has been proposed to overcome the problem of the stack package using the metal wire and to prevent and deteriorate electrical characteristics.

The through electrode is formed by forming a via in each semiconductor chip at the wafer level, and then filling a conductive film in the via. Conventionally, electroplating and chemical vapor deposition have been used as methods for filling the vias, and recently, catalytic enhanced chemical vapor deposition has been improved. Deposition) method is used.

Via filling using the electroplating method, after depositing a seed layer for flowing current in a sputtering or chemical vapor deposition process, the bath (Bath) containing a plating solution for the wafer-level semiconductor chip on which the seed layer is deposited ) By flowing a current through the seed layer in a state of being immersed in

However, the electroplating method has an advantage that the process is relatively easy compared to other methods and the process cost is low, but vias having a diameter of 10 μm and an aspect ratio of 5 or more despite optimizing variables such as additives, current density, and pulse, etc. Since it takes more than one hour to bury the landfill, the situation is showing its limitation in terms of process time.

In addition, the electroplating method has a process limitation in that the dry process for forming the conductive seed layer and the wet process for actually filling the vias must be sequentially performed in two different processes. .

Via filling using the catalytic chemical vapor deposition method causes the catalyst to precipitate on the surface of the deposition film during the deposition process, wherein the catalyst concentration in the via bottom portion becomes higher than that in the other portion. Since metal film growth is faster than that in other parts, it is in the form of a bottom-up where the bottom rises before the via inlet is blocked.

Accordingly, the catalytic chemical vapor deposition method can achieve via filling in a short time as compared with the electroplating method, and can be advantageously used for via filling with high aspect ratio.

However, in the case of via filling using the catalytic chemical vapor deposition method, as shown in FIG. 1, before the growth of the metal film 140 is filled from the bottom of the via 112 in the actual process for filling the via having an aspect ratio of 5 or more. Clogging of the inlet portion is occurring. Therefore, the catalytic chemical vapor deposition method also shows a limitation in filling the high aspect ratio vias having an aspect ratio of 5 or more.

In FIG. 1, the non-explained reference numeral 130 denotes a catalyst.

As a result, the conventional techniques such as the electroplating method and the catalytic chemical vapor deposition method have difficulty in filling the high aspect ratio vias, and thus, the through electrodes cannot be reliably formed.

The present invention provides a via filling method capable of filling a high aspect ratio via without generation of voids.

In addition, the present invention provides a method of forming a through electrode of a semiconductor package using a via filling method capable of filling a high aspect ratio via without generation of voids.

In one aspect, a method of filling a via according to the present invention includes: forming a via in an underlayer; Depositing a thin film for adsorption on the underlayer including the via; Adsorbing catalysts in a uniform distribution on the surface of the catalyst adsorption thin film; Performing a plasma treatment on a product in which the catalysts are adsorbed in a uniform distribution on the catalyst adsorption thin film so that the distribution of the catalysts is changed from an inlet portion of the via to a non-uniform distribution showing a higher distribution toward the bottom; And embedding a metal film in the via where the catalysts are adsorbed in a non-uniform distribution.

The vias are formed to have an aspect ratio of 5-40.

In addition, the via filling method according to the present invention further includes forming a barrier film on the underlayer including the via surface after forming the via and before depositing the catalyst adsorption thin film. .

The catalyst comprises iodine.

The nonuniform adsorption distribution of the catalysts is optimized by adjusting at least one of the pressure or time during the plasma treatment.

The pressure is adjusted in the range of 0.1-50 mTorr, and the time is adjusted in the range of 0.1-600 seconds.

In another aspect, a method of forming a through electrode of a semiconductor package according to the present invention includes forming vias on a semiconductor chip; Forming an insulating film on the via surface and the semiconductor chip; Depositing a thin film for adsorption on the insulating film; Adsorbing catalysts in a uniform distribution on the surface of the catalyst adsorption thin film; Plasma treatment is performed on the result of the semiconductor chip in which the catalysts are adsorbed in a uniform distribution on the catalyst adsorption thin film so that the distribution of the catalysts is changed from the inlet portion of the via to the bottom. step; And filling vias adsorbed in a non-uniform distribution of the catalysts with a metal film.

The vias are formed to have an aspect ratio of 5-40.

The method of forming a through electrode of a semiconductor package according to the present invention further includes forming a barrier film on the insulating film after forming the insulating film and before depositing the catalyst adsorption thin film.

The catalyst adsorption thin film includes a copper thin film.

The catalyst comprises iodine.

The nonuniform adsorption distribution of the catalysts is optimized by adjusting at least one of the pressure or time during the plasma treatment.

The pressure is adjusted in the range of 0.1-50 mTorr, and the time is adjusted in the range of 0.1-600 seconds.

The metal film includes a copper film.

The filling of the via with a metal film may include forming a metal film on a catalyst adsorption thin film in which the catalysts are adsorbed in a non-uniform distribution; Removing portions of the metal film, the catalyst adsorption thin film, and the insulating film formed on the semiconductor chip; And backgrinding the back surface of the semiconductor chip so that the metal film embedded in the via is exposed.

In the method of forming a through-electrode of a semiconductor package according to the present invention, after backgrinding the back surface of the semiconductor chip so that the metal film embedded in the via is exposed, the backside of the backgrinded semiconductor chip is formed to protrude the exposed metal film. Further comprising the step of etching.

In the method of forming a through-electrode of a semiconductor package according to the present invention, after backgrinding the back surface of the semiconductor chip so that the metal film embedded in the via is exposed, the metal film portion of the upper surface of the semiconductor chip or the lower surface of the semiconductor chip may be formed. The method may further include forming a connection pad on at least one portion of the exposed metal film portion.

In the method of forming a through-electrode of a semiconductor package according to the present invention, after backgrinding the back surface of the semiconductor chip so that the metal film embedded in the via is exposed, a redistribution line is connected to the exposed metal film portion on the semiconductor chip. It further comprises the step.

According to the present invention, the catalyst is uniformly adsorbed on the magnetic field by applying plasma while the catalysts are uniformly adsorbed on the entire surface of the high aspect ratio via. By changing the distribution to a higher catalyst distribution toward the bottom, it is possible to reliably perform the filling of the high aspect ratio via without generation of voids.

Accordingly, the present invention can stably perform the formation of the penetrating electrode through being able to reliably fill the high aspect ratio vias, and as a result, also improve the reliability of the semiconductor package. In addition, the present invention can achieve a high aspect ratio via buried in a single dry process, so that the process time can be reduced compared to the conventional electroplating method and catalytic chemical vapor deposition method, it is possible to improve the productivity.

In addition, since the present invention can reliably fill high aspect ratio vias without generation of voids, the present invention can be very advantageously applied to the manufacturing process of semiconductor devices in addition to the packaging field.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a schematic cross-sectional view of a copper catalytic chemical vapor deposition apparatus in which an inductively coupled plasma (ICP) generator is installed as a plasma processing means according to an embodiment of the present invention.

As shown, a reactor 210 is provided for plasma treatment and copper film deposition. The reactor 210 is, for example, provided in a rectangular box shape, in addition to the rectangular box shape may be provided in various shapes as needed.

The lower portion of the inside of the reactor 210 is provided with a stage 212 is the object to be plasma treatment and deposition is provided. The stage 212 is connected to a power supply 220 for applying a bias from the outside of the reactor 210 to enable power application and heating.

The bottom of the reactor 310 is provided with a pumping unit 230 for maintaining a high vacuum therein. The reactor 210 is connected to a copper source gas supply unit 240 for supplying gaseous copper, and the copper source gas supply unit 240 is a copper precursor container 242, a flow controller 244, and a vaporizer ( 246). In addition, the vaporizer 246 is connected to a carrier gas supply unit 250 for carrying a copper source gas. In addition, an iodine supply unit 260 for supplying iodine as a catalyst is connected to the reactor 210.

In the upper portion of the inside of the reactor 210, for example, an inductively coupled plasma generator 270 is provided as a plasma processing means. The inductively coupled plasma generator 270 includes a coil 272 installed at an upper portion of the reactor 210 and a power supply unit 274 installed to be connected to the coil 272 from the outside of the reactor 210. .

Although not shown, a pressure gas line is connected to the reactor 210, and each of the predetermined portions of the pressure gas line has a pressure gauge and a throttle valve for adjusting the pressure in the reactor 210. ) Is installed.

3A to 3E are cross-sectional views of processes for explaining a via filling method according to the present invention using the catalytic chemical vapor deposition apparatus equipped with the aforementioned plasma processing means of FIG. 2.

Referring to FIG. 3A, an underlayer 310 having a high aspect ratio via 312 having an aspect ratio of 5 or more, preferably 5 to 40 is provided. The base layer 310 may be, for example, a wafer level semiconductor chip on which a semiconductor device manufacturing process is completed, or a unit level semiconductor chip obtained through a wafer sawing process. In addition, it may be an interlayer insulating film in a semiconductor device manufacturing process.

The base layer 310 having the high aspect ratio vias 312 is loaded into the reactor of the copper catalytic chemical vapor deposition apparatus shown in FIG. 2 and then deposited on the stage. Thereafter, the base layer 310 is heated to a specific temperature from the stage in which the base layer 310 is heated, and the copper source gas including the carrier gas is supplied into the reactor in an appropriate amount. Through the deposition of the thin film 320 for the catalyst adsorption made of a thin copper film on the base layer 310 including the via (312). Here, the catalyst adsorption thin film 320 may be deposited as another metal thin film by supplying a metal source gas other than a copper source gas into the reactor.

Meanwhile, as shown in FIG. 4, before the deposition of the catalyst adsorption thin film 320, the barrier layer 314 is formed on the underlayer 310 including the via 312, and then, The catalyst adsorption thin film 320 may be deposited. The barrier layer 314 serves to prevent copper in the copper layer 340 embedded in the via 312 from diffusing to the outside of the via 312 to cause various defects. , Ti film or TiN film, or a laminated film thereof. Of course, the barrier film 314 may omit its formation if the catalyst adsorption thin film 320 also serves as a barrier to prevent copper diffusion in addition to the catalyst adsorption.

Referring to FIG. 3B, the argon gas is supplied at a constant flow rate into the reactor of the apparatus, and the iodine is supplied into the reactor while the pressure in the reactor is controlled by a throttle valve to the surface of the thin film 320 for catalyst adsorption. Adsorb the catalysts 330 made of iodine. In this case, the catalysts 330 are adsorbed in a uniform distribution on the surface of the catalyst adsorption thin film 320. In other words, the catalysts 330 are adsorbed in a uniform distribution on the entire surface of the via 312 having the high aspect ratio.
Here, the catalysts 330 made of iodine are supplied from the iodine supply unit 260 in the catalytic chemical vapor deposition apparatus shown in FIG. 2 to the inside of the reactor 210. Just by opening a valve (not shown) disposed between the iodine supply unit 260 and the reactor 210 for at least one minute, the entire surface of the catalyst adsorption thin film 320 may be adsorbed in a uniform distribution. This is because the concentration of iodine adsorbed on the surface of the catalyst adsorption thin film 320 does not continue to increase, but increases slightly to reach a saturation surface coverage. This is because iodine reaches the saturation surface concentration on all surfaces of the thin film 320.

Referring to FIG. 3C, a plasma treatment is performed on a result of the underlayer 310 having the catalysts 330 adsorbed in a uniform distribution on the entire surface of the via 312 having the high aspect ratio. The uniformly distributed catalysts 330 are changed into a nonuniform distribution advantageous for high aspect ratio via filling, that is, a nonuniform distribution showing a higher distribution from the inlet to the bottom of the via 312. Here, the plasma treatment for changing the catalysts 330 adsorbed in the uniform distribution into a non-uniform distribution advantageous for filling the high aspect ratio vias 312 proceeds as follows.

First, different radio frequency powers are applied to the coil and the base layer of the apparatus shown in FIG. 2, thereby generating plasma in the reactor. It can be understood that the application of radio frequency power to the base layer is achieved by applying the radio frequency power from a power supply to a stage on which the base layer is seated. When the plasma is generated, the cations in the plasma are accelerated by the bias applied to the underlayer to impinge on the underlayer, thereby starting the plasma treatment. On the contrary, when the bias application to the underlayer is released, the cations in the plasma no longer collide with the underlayer, thereby ending the plasma treatment.

In this process, the uniform distribution of the catalysts 330 made of iodine uniformly adsorbed to the high aspect ratio vias 312 may result in a non-uniform distribution advantageous for the via filling process of a subsequent metal film, for example, a copper film. Will change. That is, the catalysts 330 are changed to have a non-uniform distribution indicating a higher distribution from the inlet portion of the via 312 toward the bottom.

On the other hand, the above-described embodiment of the present invention has been described for the inductively coupled plasma method as a plasma processing method, in addition to the plasma by direct current power (capacitive coupled plasma) by radio frequency power (radio frequency power) Capacitively coupled plasma, electron cyclotron resonance plasma, surface wave plasma and helicon wave plasma are also available.

3D and 3E, the non-uniform distribution of the metal film according to the catalytic chemical vapor deposition process to fill the via 312 on the catalyst adsorption thin film 320 on which the catalysts 330 are adsorbed. For example, a copper film 340 is deposited. At this time, the deposition of the copper film 340 is basically a bottom-up (bottom-up) method of filling the bottom portion before the inlet portion of the via 312 is blocked, in particular, the catalyst 330 made of iodine The via 312 having a high aspect ratio of 5 or more can be quickly and stably buried without generation of voids in connection with the non-uniform distribution showing a higher distribution from the inlet portion of the via 312 toward the bottom.

5A and 5B are optical micrographs of vias having an aspect ratio of 7.8, each of which is buried according to the conventional catalytic chemical vapor deposition process and the catalytic chemical vapor deposition process to which the plasma treatment of the present invention is applied.

As shown in FIG. 5A, in the conventional case where vias are buried according to a catalytic chemical vapor deposition process of a copper film without performing a plasma treatment, specific catalyst chemical vapor deposition process conditions exist because the catalyst is uniformly distributed in the vias. The via inlet is blocked before the bottom-up via filling is completely completed, and thus, a large void is generated inside the via.

On the other hand, as shown in Figure 5b, in the case of the present invention that the plasma treatment before the catalytic chemical vapor deposition process of the copper film, the catalyst is almost removed at the inlet portion of the via, only at the bottom of the via bottom and sidewalls Due to the large amount of catalyst remaining, it is possible to see an intermediate state in which via filling is achieved in a bottom-up manner without clogging the via inlet and resulting voids.

On the other hand, when filling the high aspect ratio via according to the present invention, the stable filling of the via can be controlled by adjusting at least one of the time or pressure during the plasma treatment.

In detail, during the plasma treatment, as the process pressure increases, the direction of ions deteriorates, so that the amount of ions reaching the bottom portion is smaller than the ions reaching the inlet portion, while the total flow rate impinging on the underlying layer per unit time increases. . Thus, applying an appropriate pressure, the catalyst is almost eliminated at the inlet of the via at a uniform catalyst distribution, and the catalyst is changed to a heterogeneous catalyst distribution with a large amount of catalyst remaining at the bottom of the via and at the bottom of the sidewalls, resulting in clogging of the inlet and Bottom-up landfilling occurs without voids.

In addition, during plasma treatment, desorption of the catalyst iodine occurs in the order of the field portion, the via inlet portion, the via bottom portion, and the bottom side portion of the via in the order of time. Thus, applying an appropriate plasma treatment time under an appropriate pressure can result in a homogeneous distribution of the catalyst as described above, thus ensuring complete bottom-up of the copper film to the vias in the catalytic chemical vapor deposition process. Will be done.

For example, FIGS. 6A to 6D are optical micrographs of vias having an aspect ratio of 12.8 showing via filling patterns of copper films in a catalytic chemical vapor deposition process according to pressure and time changes during plasma treatment. Is the same as 6A illustrates a case where the plasma treatment is not performed, FIG. 6B illustrates a case where the plasma treatment is performed for 10 seconds at a pressure of 5 mTorr, and FIG. 6C illustrates a case where the plasma treatment is performed for 10 seconds at a pressure of 10 mTorr. And, Figure 6d is a photograph showing a case of performing a plasma treatment for 5 seconds at a pressure of 10mTorr, respectively.

Referring to FIG. 6A, when the plasma treatment is not performed, as a result of the deposition of the copper film by the catalytic chemical vapor deposition process, it can be seen that a very large void exists in the via.

Referring to FIG. 6B, when the plasma treatment was performed for 10 seconds at a pressure of 5 mTorr, as a result of the deposition of the copper film by the catalytic chemical vapor deposition process, it can be seen that the via filling is relatively well performed without the via inlet being blocked. have.

Referring to FIG. 6C, when the plasma treatment is performed for 10 seconds at a pressure of 10 mTorr, as a result of deposition of the copper film by the catalytic chemical vapor deposition process, it can be seen that the via filling is performed in a bottom-up manner.

Referring to FIG. 6D, when the plasma treatment was performed at a pressure of 10 mTorr for 5 seconds, the deposition of the copper film by the catalytic chemical vapor deposition process resulted in complete filling of the via without generation of voids according to the bottom-up method. can see.

Therefore, when the pressure and time during the plasma treatment are adjusted in the range of 0.1 to 50 mTorr and 0.1 to 600 seconds, preferably in the range of 5 to 10 mTorr and 5 to 10 seconds, the copper film by the subsequent catalytic chemical vapor deposition process It can be inferred that during deposition, complete via filling can be achieved without generation of voids.

On the other hand, the change from the uniform distribution of the catalyst to the non-uniform distribution, in addition to the method of adjusting the pressure or time during the plasma treatment, conditions that may affect the directionality of the ions, the incident energy of the ions and the total flow rate, for example For example, it is expected that this may be achieved through the adjustment of the power applied to the coil and the underlayer (= stage).

As described above, in the present invention, the via filling of the copper film according to the catalytic chemical vapor deposition process is voided by changing the catalysts to a non-uniform distribution through plasma treatment before performing the via filling of the copper film according to the catalytic chemical vapor deposition process. It can be made stable without the occurrence of.

In addition, the present invention can achieve a high aspect ratio via filling only in a single dry process can reduce the process time compared to the conventional electroplating process and catalytic chemical vapor deposition process, thereby improving productivity Can be.

In particular, since the present invention can reliably achieve via filling having a high aspect ratio of 5 or more, the present invention can stably form through-electrodes in a semiconductor package. As a result, the reliability of the semiconductor package can be improved. Can be improved.

In addition, since the present invention can completely fill a high aspect ratio via without generating voids, the high aspect ratio plug is applied to a manufacturing process of a semiconductor device, for example, a metal wiring forming process, in addition to the packaging field. It can be formed reliably without the occurrence of, through which, it is possible to improve the manufacturing yield and reliability of the semiconductor device.

7A to 7E are cross-sectional views illustrating processes of forming a through electrode of a semiconductor package according to another aspect of the present invention using the above-described via filling method.

Referring to FIG. 7A, a semiconductor chip 710 having a wafer level at which a semiconductor device manufacturing process is completed or a unit level obtained at a wafer sawing process is prepared. For example, the semiconductor chip 610 may be etched to form a plurality of vias 712. The via 712 is formed to have a high aspect ratio of 5 or more, for example, 5 to 40 aspect ratio. After forming an insulating film 714 on the semiconductor chip 710 including the surface of the via 712, a thin film 720 for adsorption of catalyst is deposited on the insulating film 714. The catalyst adsorption thin film 720 is preferably formed of a copper thin film.

Although not shown, in order to prevent the copper of the copper film to be subsequently embedded in the via 712 before the deposition of the catalyst adsorption thin film 720, the insulating film 714 is prevented from diffusing to the outside of the via 712. Barrier film can be formed on ().

Referring to FIG. 7B, a plurality of catalysts 730 are adsorbed on the surface of the catalyst adsorption thin film 720. As the catalyst 730, for example, iodine is formed, wherein the catalysts 730 include the entire surface of the via 712 to absorb the field portion, that is, the upper portion of the semiconductor chip 710. The thin film 720 is adsorbed in a uniform distribution.

Referring to FIG. 7C, a plasma treatment may be performed on a result of the semiconductor chip 710 on which the catalysts 730 are adsorbed in a uniform distribution, and thereby the distribution of the catalysts 730 may be via 712. ), Which is not in the upper part of the semiconductor chip 710, but changes to a non-uniform distribution showing a higher distribution from the inlet of the via 712 to the pile of the via 712. . At this time, the plasma treatment adjusts at least one of the pressure and the time so that the heterogeneous distribution of the catalysts is optimal for the buried landfill. For example, the pressure during the plasma treatment is adjusted in the range of 0.1 to 50 mTorr and the time in the range of 0.1 to 600 seconds. Preferably, the pressure is in the range of 5-10 mTorr, and the time is in the range of 5-10 seconds.

Referring to FIG. 7D, a metal film, for example, may be embedded to fill the via 712 according to the catalytic chemical vapor deposition process with respect to the result of the semiconductor chip 710 having a non-uniform distribution of the catalysts 730 by the plasma treatment. For example, a copper film 740 is deposited. Here, the copper film 740 is completely free of the vias 730 without the generation of voids in the bottom-up manner with respect to the catalysts 730 being hardly adsorbed toward the bottom portion of the catalyst 730. ), And the catalysts 730 are only partially present on the surface of the copper layer on the via.

Referring to FIG. 7E, an etch back may be exposed to expose the top surface of the semiconductor chip 710 with respect to the result of the semiconductor chip 710 having the high aspect ratio via 712 embedded by the copper film 740. Alternatively, the copper film including the catalyst, the thin film for adsorption of the catalyst, and the insulating film are etched by using a chemical mechanical polishing process.

Thereafter, back grinding of the back surface of the semiconductor chip 710 is performed such that a portion of the copper film 740 buried in the bottom of the via 710 is exposed, and thus, a via 712 having a high aspect ratio. A through electrode 750 according to the present invention is formed therein. Here, the through electrode 750 is formed reliably itself in connection with the via filling having a high aspect ratio is made completely without the generation of voids.

Meanwhile, as shown in FIG. 8, after the through electrode 750 is formed, an additional etching process, for example, a wet etch process is performed on the rear surface of the semiconductor chip 710. The thickness of a portion of the rear surface of the semiconductor chip 710 may be removed, and through this, the through electrode 750 may protrude to the rear surface of the semiconductor chip 710.

Although not shown, it may be understood that the semiconductor package is easily mounted on a printed circuit board when the semiconductor module is manufactured.

In addition, as shown in FIGS. 9A to 9C, after the through electrode 750 is formed, at least one portion of the through electrode 750 exposed to the upper and lower surfaces of the semiconductor chip 710 is connected. The pad 760 may be formed.

Although not shown, this may be understood to be to facilitate mounting on a printed circuit board during the manufacture of a semiconductor module and to facilitate electrical connection between upper and lower semiconductor packages during the manufacture of a stack package. .

In addition, as shown in FIG. 10, after the through electrode 750 is formed, the cultivation is connected to a portion of the through electrode 750 exposed to the top surface of the semiconductor chip 710 on the top surface of the semiconductor chip 710. Line 770 may be formed.

It may be understood that this is to facilitate easier electrical connection through pad rearrangement.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

1 is a cross-sectional view for explaining a conventional problem.

2 is a cross-sectional view schematically showing a copper catalytic chemical vapor deposition apparatus equipped with an inductively coupled plasma generator as a plasma processing means according to the present invention.

3A to 3E are cross-sectional views of processes for describing a method of filling a via according to an aspect of the present invention.

4 is a cross-sectional view illustrating a via filling method according to another exemplary embodiment of the present invention.

5A and 5B are optical micrographs of vias having an aspect ratio of 7.8, which is buried according to the conventional catalytic chemical vapor deposition process and the catalytic chemical vapor deposition process to which the plasma treatment of the present invention is applied.

6A through 6D are optical micrographs of vias having an aspect ratio of 12.8 showing via fill patterns of copper films in a catalytic chemical vapor deposition process with pressure and time changes during plasma treatment.

7A to 7E are cross-sectional views illustrating processes of forming a through electrode of a semiconductor package according to another aspect of the present invention using the above-described via filling method.

8 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to another embodiment of the present invention.

9A to 9C are cross-sectional views illustrating a method of manufacturing a semiconductor package according to still another embodiment of the present invention.

10 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to still another embodiment of the present invention.

Claims (20)

Forming vias in the underlying layer; Depositing a thin film for adsorption on the underlayer including the via; Adsorbing catalysts in a uniform distribution on the surface of the catalyst adsorption thin film; Performing a plasma treatment on a product in which the catalysts are adsorbed in a uniform distribution on the catalyst adsorption thin film so that the distribution of the catalysts is changed from an inlet portion of the via to a non-uniform distribution showing a higher distribution toward the bottom; And Embedding a metal film in a via where the catalysts are adsorbed in a non-uniform distribution; Via filling method comprising a. The method of claim 1, The via is buried method characterized in that it is formed to have an aspect ratio of 5 to 40. The method of claim 1, After forming the via, and before depositing the catalyst adsorption thin film, And forming a barrier film on the underlayer including the via surface. The method of claim 1, And the catalyst comprises iodine. The method of claim 1, The non-uniform adsorption distribution of the catalysts are optimized by adjusting at least one of the pressure or time during the plasma treatment. The method of claim 5, Via pressure filling method characterized in that the pressure is adjusted to the range of 0.1 ~ 50mTorr. The method of claim 5, And the time is adjusted to a range of 0.1 to 600 seconds. Forming vias in the semiconductor chip; Forming an insulating film on the via surface and the semiconductor chip; Depositing a thin film for adsorption on the insulating film; Adsorbing catalysts in a uniform distribution on the surface of the catalyst adsorption thin film; Plasma treatment is performed on the result of the semiconductor chip in which the catalysts are adsorbed in a uniform distribution on the catalyst adsorption thin film so that the distribution of the catalysts is changed from the inlet portion of the via to the bottom. step; And Burying the vias adsorbed with a non-uniform distribution of the catalysts into a metal film; The through-electrode forming method of a semiconductor package comprising a. The method of claim 8, And forming the vias to have an aspect ratio of about 5 to about 40. The method of claim 8, After forming the insulating film, and before depositing the catalyst adsorption thin film, And forming a barrier film on the insulating film. The method of claim 8, The catalyst adsorption thin film is a through electrode forming method of a semiconductor package, characterized in that it comprises a copper thin film. The method of claim 8, The catalyst is a through-electrode forming method of the semiconductor package, characterized in that it comprises iodine. The method of claim 8, The non-uniform adsorption distribution of the catalyst is optimized by adjusting at least one of the pressure or time during the plasma treatment. The method of claim 13, The pressure is a through-electrode formation method of a semiconductor package, characterized in that to adjust in the range of 0.1 to 50mTorr. The method of claim 13, Said time is adjusted to the range of 0.1 to 600 seconds. The method of claim 8, And the metal film comprises a copper film. The method of claim 8, Filling the via with a metal film Forming a metal film on the catalyst adsorption thin film in which the catalysts are adsorbed in a non-uniform distribution; Removing portions of the metal film, the catalyst adsorption thin film, and the insulating film formed on the semiconductor chip; And Backgrinding a back surface of the semiconductor chip to expose a metal film embedded in the via; The through-electrode forming method of the semiconductor package further comprising. The method of claim 17, After backgrinding the back surface of the semiconductor chip to expose the metal film embedded in the via, And etching the back surface of the backgrinded semiconductor chip such that the exposed metal film protrudes. The method of claim 17, After backgrinding the back surface of the semiconductor chip to expose the metal film embedded in the via, And forming a connection pad on at least one portion of the exposed metal film portion of the upper surface of the semiconductor chip or the exposed metal film portion of the lower surface of the semiconductor chip. Formation method. The method of claim 17, After backgrinding the back surface of the semiconductor chip to expose the metal film embedded in the via, And forming a redistribution line connected to the exposed metal film part on the semiconductor chip.

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