KR101043347B1 - Quad-channel pulse width modulation signal generator and electronic system including the same - Google Patents

Abstract

PURPOSE: A quad-channel pulse width modulation signal generating device and electronic system with the same are provided to generate a plurality of independent pulse width modulation signals, thereby reducing unnecessary power consumption. CONSTITUTION: A programmed programmable logic unit(200) receives a 8 bit digital input signal and a four bit selection signal. The programmed programmable logic unit generates first to fourth program signals by latching a digital input signal based on a logic level of each bit of a selection signal. A binary counter unit(300) generates 8 bit count signals which are successively up-counted based on a clock signal and a control signal. A four channel binary comparing unit(400) respectively compares the count signals with first to fourth program signals respectively. An output buffer unit(500) stores first to fourth pulse width modulation signals.

Description

Quad-channel pulse width modulation signal generator and electronic system including the same}

The present invention relates to an apparatus for generating a drive signal, and more particularly, to an apparatus for generating a 4-channel pulse width modulated signal and an electronic system including the same.

Pulse width modulation (PWM) is a method of modulating by changing the width of the output pulse, that is, the duty cycle of the output signal according to the size of the input signal. It is widely used in various applications such as communication, power control, and conversion, and is particularly widely used in amplifiers (eg, class D amplifiers) or data processing devices (eg, audio processing devices).

In general, a conventional pulse width modulated signal generating device generates one pulse width modulated signal by modulating one input signal, and is implemented by including a plurality of logic elements. In a system driven based on a pulse width modulated signal, driving a plurality of applications requires generating a plurality of pulse width modulated signals that are changed independently of each other, and a plurality of pulse width modulated signal generating apparatuses are required. In this case, however, power consumption may increase, and system size, circuit complexity, and manufacturing cost may increase. Therefore, there is a need for an apparatus capable of generating a plurality of pulse width modulated signals with low power consumption, simple structure, and independent of each other.

One object of the present invention for solving the above problems is to provide a four-channel pulse width modulated signal generating apparatus for generating four independent pulse width modulated signals.

Another object of the present invention is to provide an electronic system including the apparatus for generating a four-channel pulse width modulated signal.

In order to achieve the above object of the present invention, a four-channel pulse width modulated signal generating apparatus according to an embodiment of the present invention includes a programmable logic unit, a binary counter unit, a four-channel binary comparison unit and an output buffer unit. The programmable logic unit receives an 8-bit digital input signal and a 4-bit selection signal, and latches the digital input signal based on a logic level of each bit of the selection signal, respectively, the first to fourth program signals having 8 bits. Are programmed to generate them. The binary counter unit receives a clock signal and a control signal and generates an 8-bit count signal sequentially up counted based on the clock signal and the control signal. The four-channel binary comparator compares the count signal with the first to fourth program signals, respectively, to generate first to fourth pulse width modulation signals independent of each other. The output buffer unit stores and outputs the first to fourth pulse width modulation signals. The frequency of the first to fourth pulse width modulation signals has a value obtained by dividing the frequency of the clock signal by a division ratio of 2 ⁸ , respectively. When the magnitude of the count signal is greater than or equal to the magnitude of the first to fourth program signals, respectively, the logic level of the first to fourth pulse width modulation signals corresponds to a first logic level, respectively. When the magnitudes are respectively smaller than the magnitudes of the first to fourth program signals, the logic levels of the first to fourth pulse width modulation signals correspond to the second logic levels, respectively.

In one embodiment, the programmable logic unit may include a first programmable logic, a second programmable logic, a third programmable logic, and a fourth programmable logic. The first programmable logic receives the digital input signal and the first bit of the selection signal and generates the first program signal by latching the digital input signal when the first bit of the selection signal is enabled. Stores and outputs the generated first program signal, and outputs the stored first program signal when the first bit of the selection signal is disabled. The second programmable logic receives the digital input signal and the second bit of the selection signal, and generates the second program signal by latching the digital input signal when the second bit of the selection signal is enabled. Store and output the generated second program signal, and output the stored second program signal when the second bit of the selection signal is disabled. The third programmable logic receives the digital input signal and the third bit of the selection signal, and generates the third program signal by latching the digital input signal when the third bit of the selection signal is enabled. Store and output the generated third program signal, and output the stored third program signal when the third bit of the selection signal is disabled. The fourth programmable logic receives the digital input signal and the fourth bit of the selection signal, and generates the fourth program signal by latching the digital input signal when the fourth bit of the selection signal is enabled. Stores and outputs the generated fourth program signal, and outputs the stored fourth program signal when the fourth bit of the selection signal is disabled.

In an embodiment, the four-channel binary comparator may include a first binary comparator, a second binary comparator, a third binary comparator, and a fourth binary comparator. The first binary comparator compares the count signal with the first program signal and has the first logic level when the count signal is greater than or equal to the magnitude of the first program signal. The first pulse width modulated signal having the second logic level is generated when it is smaller than the magnitude of the first program signal. The second binary comparator compares the count signal with the second program signal and has the first logic level when the count signal is greater than or equal to the magnitude of the second program signal. The second pulse width modulated signal having the second logic level is generated when smaller than the magnitude of the second program signal. The third binary comparator compares the count signal with the third program signal and has the first logic level when the count signal is greater than or equal to the magnitude of the third program signal. The third pulse width modulated signal having the second logic level is generated when smaller than the magnitude of the third program signal. The fourth binary comparison unit compares the count signal with the fourth program signal and has the first logic level when the count signal is greater than or equal to the magnitude of the fourth program signal. The fourth pulse width modulated signal having the second logic level is generated when smaller than the magnitude of the fourth program signal.

In an embodiment, the first binary comparator may include a lower bit comparator and an upper bit comparator. The lower bit comparator receives a power supply voltage, a ground voltage, a lower 4 bits of the count signal, and a lower 4 bits of the first program signal, and compares the lower 4 bits of the count signal with the lower 4 bits of the count signal based on the supply voltage and the ground voltage. The first four bits of the first program signal are compared to generate a first comparison signal and a second comparison signal. The upper bit comparator receives the power supply voltage, the first comparison signal, the second comparison signal, the upper 4 bits of the count signal, and the upper 4 bits of the first program signal, and the power supply voltage, the first comparison. The first pulse width modulation signal is generated by comparing the upper four bits of the count signal with the upper four bits of the first program signal based on the signal and the second comparison signal.

In one embodiment, each of the second to fourth binary comparison units may have the same configuration as that of the first binary comparison unit.

In order to achieve the above object of the present invention, an electronic system according to an embodiment of the present invention includes a microprocessor, a four-channel pulse width modulated signal generating device, and a driver. The microprocessor provides a clock signal, a control signal, an 8-bit digital input signal and a 4-bit select signal. The four-channel pulse width modulated signal generating device latches the digital input signal based on a logic level of each bit of the selection signal to generate first to fourth program signals having 8 bits, respectively, the clock signal and the control. An 8-bit count signal that is sequentially up-counted is generated based on the signal, and the first to fourth pulse width modulation signals independent of each other are generated by comparing the count signal and the first to fourth program signals, respectively. The driver is driven based on the first to fourth pulse width modulation signals. The frequency of the first to fourth pulse width modulation signals has a value obtained by dividing the frequency of the clock signal by a division ratio of 2 ⁸ , respectively. When the magnitude of the count signal is greater than or equal to the magnitude of the first to fourth program signals, respectively, the logic level of the first to fourth pulse width modulation signals corresponds to a first logic level, respectively. When the magnitudes are respectively smaller than the magnitudes of the first to fourth program signals, the logic levels of the first to fourth pulse width modulation signals correspond to the second logic levels, respectively.

The pulse width modulated signal generating apparatus according to the embodiments of the present invention as described above generates a plurality of independent pulse width modulated signals, thereby reducing unnecessary power consumption, and the size, manufacturing cost, and complexity of the pulse width modulated signal generating apparatus. Can be reduced.

However, the effects of the present invention are not limited to the above-mentioned effects, and may be variously expanded within a range without departing from the spirit and scope of the present invention.

1 is a block diagram illustrating an apparatus for generating a 4-channel pulse width modulated signal according to an exemplary embodiment of the present invention.
FIG. 2 is a block diagram illustrating an example of a programmable logic unit included in the apparatus for generating a 4-channel pulse width modulated signal of FIG. 1.
3 is a circuit diagram illustrating an example of a binary counter included in the apparatus for generating a four-channel pulse width modulated signal of FIG. 1.
4 is a block diagram illustrating an example of a four-channel binary comparator included in the four-channel pulse width modulated signal generator of FIG. 1.
FIG. 5 is a block diagram illustrating an example of a first binary comparison unit included in the four-channel binary comparison unit of FIG. 4.
FIG. 6 is a circuit diagram illustrating an example of a lower bit comparator included in the first binary comparator of FIG. 5.
FIG. 7 is a table illustrating logic levels of output signals according to logic levels of input signals of the lower bit comparator of FIG. 6.
FIG. 8 is a block diagram illustrating an electronic system including an apparatus for generating a 4-channel pulse width modulated signal, according to an exemplary embodiment.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for the components.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

1 is a block diagram illustrating a four-channel pulse width modulated signal generating apparatus 100 according to an embodiment of the present invention.

Referring to FIG. 1, the apparatus for generating a 4 channel pulse width modulation signal 100 includes a programmable logic unit 200, a binary counter unit 300, a 4 channel binary comparison unit 400, and an output buffer unit 500. .

The programmable logic unit 200 is programmed for operation by a user. That is, the user may create a program using a tool such as a schematic through a design using a specific language or a symbol, and then download the created program to the programmable logic unit 200 to operate the program. Language and hardware description language (HDL), Altera HDL (AHDL), Very High Speed Integrated Circuit (VHSIC) HDL (VHDL), Verilog used for low complexity devices such as PALASM, ABEL, etc. A language used for a high complexity device such as the above may be used. Meanwhile, the programmable logic unit 200 may be implemented to include units having a field programmable gate array (FPGA), a complex programmable logic device (CPLD), a D fabric array (DFA), or other programmable logic device (PLD) structures. .

The programmable logic unit 200 receives the digital input signal D and the selection signal S. The programmable logic unit 200 performs a logic operation on the digital input signal D based on the logic level of the selection signal S and generates first to fourth program signals PS1, PS2, PS3, and PS4. Is programmed to. For example, the logic operation may be a latch operation, and the programmable logic unit 200 latches the digital input signal D based on the logic level of the selection signal S to form first to fourth program signals. It can be programmed in the form of a flip-flop to produce (PS1, PS2, PS3, PS4).

In one embodiment, the digital input signal D and the selection signal S may consist of a plurality of bits. For example, the digital input signal D may be an 8-bit digital signal, and the selection signal S may be a 4-bit digital signal. In this case, the first to fourth program signals PS1, PS2, PS3, and PS4 may be 8-bit digital signals having the same number of bits as the digital input signal D, respectively. According to an embodiment, the digital input signal D may be a digital signal composed of 4N bits (N is a natural number of two or more), and the selection signal S may be a digital signal composed of N bits. In addition, the operation of the programmable logic unit 200 may be different according to the logic level of each bit of the selection signal S, which will be described later with reference to FIG. 2.

The binary counter unit 300 receives a clock signal CCK and a control signal CON. In one embodiment, the clock signal CCK may have a frequency obtained by dividing the main clock signal used in the main processor by a predetermined division ratio. For example, the predetermined division ratio may be 2 ⁶ , that is, 64. When the frequency of the main clock signal is 11.0592 MHz, the frequency of the clock signal CCK may be 172.8 kHz. The control signal CON may include a clock enable signal CCKEN, an initialization signal CCLR, a register clock signal RCK, an output enable signal G, and the like.

The binary counter unit 300 generates a count signal CS that is sequentially updated based on the clock signal CCK and the control signal CON. Since the digital input signal D and the first to fourth program signals PS1, PS2, PS3, and PS4 are 8-bit digital signals, the count signal CS may also be the same as the 8-bit digital signal. That is, the count signal CS may perform 2 ⁸ , that is, 256 counts from "00000000" to "11111111". If the count is completed up to "11111111", the count signal CS may repeatedly count from "00000000" again. Can be.

In an embodiment, the frequencies of the first to fourth pulse width modulation signals PWM1, PWM2, PWM3, and PWM4 that are finally generated may be determined based on the number of bits of the count signal CS. For example, when the count signal CS is a digital signal composed of 4N bits, the frequency of the first to fourth pulse width modulation signals PWM1, PWM2, PWM3, and PWM4 is the clock signal CCK. The frequency of 2 may be divided by the division ratio of ^4N . As described above, when the count signal CS is an 8-bit digital signal and the frequency of the clock signal CCK is 172.8 Khz, the first to fourth pulse width modulation signals PWM1, PWM2, PWM3, and PWM4 The frequency may be 675 Hz, which is a value obtained by dividing the frequency of the clock signal CCK at a division ratio of 2 ⁸ , that is, 256.

The four-channel binary comparison unit 400 receives the count signal CS and the first to fourth program signals PS1, PS2, PS3, and PS4. The four-channel binary comparator 400 compares the count signal CS and the first to fourth program signals PS1, PS2, PS3, and PS4, respectively, so that the first to fourth pulse width modulation signals independent of each other ( Generate a pulse width modulated signal set (PWM) comprising PWM1, PWM2, PWM3, PWM4). That is, the four-channel binary comparison unit 400 compares the count signal CS and the first program signal PS1 to generate the first pulse width modulation signal PWM1, and the count signal CS and the second program signal. Compares PS2 to generate a second pulse width modulated signal PWM2, compares the count signal CS and the third program signal PS3 to generate a third pulse width modulated signal PWM3, and counts the signals The fourth pulse width modulated signal PWM4 is generated by comparing the CS and the fourth program signal PS4. The first to fourth pulse width modulated signals PWM1, PWM2, PWM3, and PWM4 are generated independently of each other, and a change in any one pulse width modulated signal does not affect the remaining pulse width modulated signals.

In example embodiments, when the magnitude of the count signal CS is greater than or equal to the magnitude of the first through fourth program signals PS1, PS2, PS3, and PS4, respectively, the first through fourth pulse width modulation signals PWM1. , Logic levels of PWM2, PWM3, and PWM4 correspond to first logic levels, respectively, and the magnitude of the count signal CS is greater than the magnitude of the first to fourth program signals PS1, PS2, PS3, and PS4. When small, the logic levels of the first to fourth pulse width modulation signals PWM1, PWM2, PWM3, and PWM4 may correspond to the second logic levels, respectively. The first logic level may be a logic low level, and the second logic level may be a logic high level. For example, the logic level of the first pulse width modulation signal PWM1 has the first logic level when the magnitude of the count signal CS is greater than or equal to the magnitude of the first program signal PS1. When the magnitude of the count signal CS is smaller than the magnitude of the first program signal PS1, the count signal CS may have the second logic level.

The four-channel binary comparison unit 400 may continuously compare the count signal CS and the first program signal PS1 to change the logic level of the first pulse width modulation signal PWM1 according to the comparison result. A transition time of the logic level of the first pulse width modulation signal PWM1 may be adjusted. In the embodiments according to the present invention, since the count signal CS is counted up from "00000000", the logic level of the first pulse width modulation signal PWM1 may have the second logic level at the beginning of the count. When the magnitude of the count signal CS is equal to the magnitude of the first program signal PS1, the count signal CS may transition to the first logic level. That is, the four-channel binary comparison unit 400 adjusts the timing at which the magnitude of the count signal CS is equal to the magnitude of the first program signal PS1, thereby adjusting the logic of the first pulse width modulation signal PWM1. The timing at which the level transitions can be adjusted, thus changing the duty cycle of the first pulse width modulation signal PWM1 and generating pulse width modulation signals having a desired duty cycle. In addition, the duty cycle may be changed through the similar operation with respect to the second to fourth pulse width modulation signals PWM2, PWM3, and PWM4. At this time, the duty cycle of the first to fourth pulse width modulation signals PWM1, PWM2, PWM3, and PWM4 are independently changed.

The output buffer unit 500 receives and stores the pulse width modulation signal set PWM including the first to fourth pulse width modulation signals PWM1, PWM2, PWM3, and PWM4, and stores the first to fourth pulse widths. Output the modulation signals PWM1, PWM2, PWM3, PWM4.

FIG. 2 is a block diagram illustrating an example of a programmable logic unit 200a included in the four-channel pulse width modulated signal generating apparatus 100 of FIG. 1.

Referring to FIG. 2, the programmable logic unit 200a may include a first programmable logic 210, a second programmable logic 220, a third programmable logic 230, and a fourth programmable logic 240.

The first programmable logic 210 receives the first bit S1 of the digital input signal D and the select signal S. The first programmable logic 210 is programmed to perform a logic operation on the digital input signal D and generate a first program signal PS1 based on the logic level of the first bit S1 of the selection signal S. do. For example, when the first bit S1 of the selection signal S is enabled, the first programmable logic 210 may latch the digital input signal D to generate the first program signal PS1. The generated first program signal PS1 may be stored and output at the same time. That is, the first programmable logic 210 may be programmed in the form of a flip flop. When the first bit S1 of the selection signal S is disabled, the first programmable logic 210 may continuously output the previously generated and stored first program signal PS1. According to an embodiment, the first programmable logic 210 may be implemented in structures such as FPGA, CPLD, and DFA, and may be programmed in languages such as PALASM, ABEL, HDL, AHDL, VHDL, and Verilog.

The second to fourth programmable logics 220, 230, and 240 are each of the first programmable logic 210 except for receiving the second to fourth bits S2, S3, and S4 of the selection signal S, respectively. And may have substantially the same configuration, and may perform substantially the same operation. That is, when the second bit S2 of the selection signal S is enabled, the second programmable logic 220 may generate the second program signal PS2 by latching the digital input signal D. The generated second program signal PS2 may be stored and output at the same time. When the second bit S2 of the selection signal S is disabled, the previously generated second program signal PS2 may be stored. You can print continuously. The third programmable logic 230 may generate the third program signal PS3 by latching the digital input signal D when the third bit S3 of the selection signal S is enabled. The third program signal PS3 may be stored and output at the same time. When the third bit S3 of the selection signal S is disabled, the third program signal PS3 is generated and stored continuously. You can print The fourth programmable logic 240 may generate the fourth program signal PS4 by latching the digital input signal D when the fourth bit S4 of the selection signal S is enabled. The fourth program signal PS4 may be stored and output at the same time. When the fourth bit S4 of the selection signal S is disabled, the fourth program signal PS4 is generated and stored continuously. You can print However, characteristics of a symmetric operation such as latch timing or latch period of the first to fourth programmable logics 210, 220, 230, and 240 may be different according to a user's program method.

In one embodiment, the first to fourth programmable logics 210, 220, 230, 240 are generated when the respective bits S1, S2, S3, S4 of the selection signal S are enabled. Each of the first to fourth program signals PS1, PS2, PS3, and PS4 may include registers. For example, the first programmable logic 210 may include a first register (not shown), and generate a first program signal PS1 when the first bit S1 of the selection signal S is enabled. If the first bit S1 of the selection signal S is disabled, the first program signal PS1 generated and stored in the first register is continuously output. Can be.

When the first to fourth programmable logics 210, 220, 230, and 240 receive only one of each of the bits S1, S2, S3, and S4 of the selection signal S, the received bits are enabled. Each of the first to fourth program signals PS1, PS2, PS3, and PS4 may be updated through a latching operation. Therefore, the selection signal S may be one of the bits S1, S2, S3, and S4. Only bits of may be enabled, or two or more bits may be enabled simultaneously.

FIG. 3 is a circuit diagram illustrating an example of the binary counter unit 300a included in the four-channel pulse width modulated signal generating apparatus 100 of FIG. 1.

Referring to FIG. 3, the binary counter unit 300a may include first to eighth flip-flops FF1 to FF8, first to eighth registers REG1 to REG8, a plurality of inverters INV11 to INV22, It may include a plurality of NAND gates NAND11-NAND27 and a plurality of NOR gates NOR11 -NOR15.

The binary counter unit 300a is based on the clock signal CCK, the clock enable signal CCKEN, the initialization signal CCLR, the register clock signal RCK, and the output enable signal G, and the counter signal CS. Generate first to eighth count bit signals CS0-CS7 corresponding to each bit of S and sequentially updated.

The binary counter unit 300a may be implemented in the form of a ripple counter in which an output of the front end of each of the first to eighth flip-flops FF1 to FF8 is applied to the input of the rear end. For example, the clock enable signal CCKEN may be provided to the input of the first flip-flop FF1 through the inverters INV15 and INV11, and the output of the first flip-flop FF1 is the NAND gate NAND11. It may be provided to the input of the second flip-flop (FF2) through. In addition, outputs of the first to eighth flip-flops FF1-FF8 are provided to the first to eighth registers REG1-REG8, respectively, and the first to eighth registers REG1-REG8 are first to eighth. The eighth count bit signals CS0-CS7 are output. For example, an output of the first flip-flop FF1 is provided to the first register REG1, and the first register REG is a first corresponding to the least significant nit LSB of the count signal CS. The count bit signal CS0 is output.

The clock signal CCK drives the first through eighth flip-flops FF1-FF8, and the register clock signal RCK drives the first through eighth registers REG1-REG8, and the clock enable signal. The CCKEN controls the clock signal CCK, the output enable signal G controls the output of the first through eighth count bit signals CS0-CS7, and the initialization signal CCLR includes the first through The eighth count bit signals CS0-CS7 are initialized. The ripple carry output signal RCO is a signal provided to improve the resolution of the binary counter unit 300a and may have a logic level as shown in Equation 1 below.

[Equation 1]

4 is a block diagram illustrating an example of a four-channel binary comparison unit 400a included in the four-channel pulse width modulated signal generating apparatus 100 of FIG. 1.

Referring to FIG. 4, the four-channel binary comparator 400a may include a first binary comparator 410, a second binary comparator 420, a third binary comparator 430, and a fourth binary comparator 440. It may include.

The first binary comparison unit 410 compares the count signal CS with the first program signal PS1, and when the magnitude of the count signal CS is greater than or equal to the magnitude of the first program signal PS1. When the magnitude of the count signal CS is smaller than the magnitude of the first program signal PS1 with the first logic level, the first pulse width modulation signal PWM1 having the second logic level is generated. The first logic level may be a logic low level, and the second logic level may be a logic high level.

The second to fourth binary comparison units 420, 430, and 440 are configured substantially the same as the first binary comparison unit 410 except for receiving the second to fourth program signals PS2, PS3, and PS4, respectively. Has substantially the same operation. That is, the second binary comparator 420 compares the count signal CS and the second program signal PS2 so that the magnitude of the count signal CS is greater than or equal to the magnitude of the second program signal PS2. In this case, when the magnitude of the count signal CS is smaller than the magnitude of the second program signal PS2 with the first logic level, the second pulse width modulation signal PWM2 having the second logic level is generated. can do. The third binary comparator 430 compares the count signal CS with the third program signal PS3 and the magnitude of the count signal CS is greater than or equal to the magnitude of the third program signal PS3. When the count signal CS has the first logic level and the magnitude of the count signal CS3 is smaller than the magnitude of the third program signal PS3, the third pulse width modulation signal PWM3 having the second logic level may be generated. have. The fourth binary comparator 440 compares the count signal CS with the fourth program signal PS4, and when the magnitude of the count signal CS is greater than or equal to the magnitude of the fourth program signal PS4. The fourth pulse width modulation signal PWM4 having the second logic level may be generated when the count logic CS has the first logic level and the magnitude of the count signal CS is smaller than that of the fourth program signal PS4. have.

5 is a block diagram illustrating an example of a first binary comparator 410a included in the four-channel binary comparator 400a of FIG. 4.

Referring to FIG. 5, the first binary comparator 410a may include a lower bit comparator 412 and an upper bit comparator 414. The lower bit comparator 412 and the upper bit comparator 414 may each be four bit comparators and may be connected in a cascade form.

The lower bit comparator 412 includes the power supply voltage VDD, the ground voltage GND, the lower four bits CS0, CS1, CS2, and CS3 of the count signal CS, and the lower four bits of the first program signal PS1 ( PS10, PS11, PS12, PS13) are received. The ground voltage GND is provided as a logic low level to the first cascade input terminal CI11 of the lower bit comparator 412, and the power supply voltage VDD is the second and third casings of the lower bit comparator 412. It is provided as a logic high level to the cage input terminals CI12 and CI13.

The lower bit comparator 412 is a lower four of the count signal CS based on the power supply voltage VDD and the ground voltage GND input to the first to third cascade input terminals CI11, CI12, and CI13. By comparing the bits CS0, CS1, CS2, and CS3 with the lower four bits PS10, PS11, PS12, and PS13 of the first program signal PS1, the comparison result is compared with the first through third output terminals CO11 and CO12. Through CO13). In particular, the first comparison signal CA is provided through the first output terminal CO11, and the second comparison signal CB is provided through the second output terminal CO12. For example, in the first comparison signal CA, the lower four bits CS0, CS1, CS2, and CS3 of the count signal CS are the lower four bits PS10, PS11, PS12, and PS13 of the first program signal PS1. If greater than or equal to the first logic level, the lower four bits CS0, CS1, CS2, CS3 of the count signal CS are the lower four bits PS10, PS11, PS12, of the first program signal PS1. PS2) may have a second logic level. The second comparison signal CB has the lower four bits CS0, CS1, CS2, and CS3 of the count signal CS being greater than the lower four bits PS10, PS11, PS12, and PS13 of the first program signal PS1. In the small case, the lower four bits PS0, CS1, CS2, and CS3 of the count signal CS and the lower four bits PS10, PS11, PS12, and PS13 of the count signal CS are provided. May have the second logic level. The first logic level may be a logic low level, and the second logic level may be a logic high level.

The higher bit comparator 414 includes a power supply voltage VDD, a first comparison signal CA, and a second comparison signal CB. The upper four bits CS4, CS5, CS6 and CS7 of the count signal CS and the upper four bits PS14, PS15, PS16 and PS17 of the first program signal PS1 are received. The first comparison voltage CA is provided to the first cascade input terminal CI21 of the upper bit comparator 414, and the second comparison voltage CB is the second cascade input of the upper bit comparator 414. Provided to terminal CI22, a power supply voltage VDD is provided as a logic high level to third cascade input terminal CI23 of higher bit comparator 414.

The upper bit comparator 414 is a first and second comparison signal that is a result of comparing the power supply voltage VDD and the lower four bits, which are input to the first to third cascade input terminals CI21, CI22, and CI23. Based on (CA, CB), the upper four bits (CS4, CS5, CS6, CS7) of the count signal CS are compared with the upper four bits (PS14, PS15, PS16, PS17) of the first program signal PS1. The final comparison result is provided through the first to third output terminals CO21, CO22, and CO23. In particular, the first pulse width modulated signal PWM1 is provided through the first output terminal CO21. For example, the first pulse width modulation signal PWM1 has a first logic level when the count signal CS is greater than or equal to the first program signal PS1, and the count signal CS is the first program signal ( Smaller than PS1), it may have a second logic level.

5 illustrates an example of the first binary comparison unit 410a among the binary comparison units 410, 420, 430, and 440 included in the four-channel binary comparison unit 400a of FIG. 4, according to an embodiment. The second to fourth binary comparison units 420, 430, and 440 may also have the same configuration as the first binary comparison unit 410a of FIG. 5.

FIG. 6 is a circuit diagram illustrating an example of a lower bit comparator 412a included in the first binary comparator 410a of FIG. 5.

Referring to FIG. 6, the lower bit comparator 412a may include a plurality of inverters INV31 -INV55, a plurality of NAND gates NAND31-NAND40, and a plurality of NOR gates NOR31 -NOR39.

The lower bit comparator 412a first compares each bit of the inputs to be compared with each other. For example, the lower bit comparator 412a may compare the least significant bit CS0 of the count signal CS and the least significant bit PS10 of the first program signal PS1 through a plurality of logical operations. The lower bit comparator 412a then performs a logical operation on the comparison results of the respective bits and the cascade input signals provided through the first to third cascade input terminals CI11, CI12, CI13. Therefore, the final comparison result may be provided through the first to third output terminals CO11, CO12, and CO13.

FIG. 7 illustrates output signals CO11 and 11 according to logic levels of input signals CS0, CS1, CS2, CS3, PS10, PS11, PS12, PS13, CI11, CI12, and CI13 of the lower bit comparator 412a of FIG. 6. This table shows the logic levels of CO12 and CO13. In FIG. 7, X represents a don't care state.

Hereinafter, the operation of the lower bit comparator 412a will be described with reference to FIGS. 5 to 7.

CASE1 represents a case where the lower four bits CS0, CS1, CS2, and CS3 of the count signal CS are larger than the lower four bits PS10, PS11, PS12, and PS13 of the first program signal PS1. For example, the most significant bit CS3 of the lower four bits CS0, CS1, CS2, and CS3 of the count signal CS is the lower four bits PS10, PS11, PS12, and PS13 of the first program signal PS1. If it is larger than the most significant bit PS13, the lower four bits CS0, CS1, CS2, and CS3 of the count signal CS are the lower four bits PS10, PS11, and PS12 of the first program signal PS1 without having to compare the remaining bits. , PS13). As described above, the lower four bits CS0, CS1, CS2, and CS3 of the count signal CS are larger than the lower four bits PS10, PS11, PS12, and PS13 of the first program signal PS1, and the third cascade. When the signal provided to the input terminal CI13 has a logic high level, the outputs of the first to third output terminals CO11, CO12, and CO13 of the lower bit comparator 412a are connected to the first and second cascades. Regardless of the logic level of the signals provided to the input terminals CI11 and CI12, they may have a logic low level, a logic low level, and a logic high level, respectively.

CASE2 represents a case where the lower four bits CS0, CS1, CS2, and CS3 of the count signal CS and the lower four bits PS10, PS11, PS12, and PS13 of the first program signal PS1 are the same. In this case, the outputs of the first to third output terminals CO11, CO12, and CO13 of the lower bit comparator 412a differ depending on the logic level of the signals provided to the cascade input terminals CI11, CI12, and CI13. May have a logic level.

CASE3 represents a case where the lower four bits CS0, CS1, CS2, and CS3 of the count signal CS are smaller than the lower four bits PS10, PS11, PS12, and PS13 of the first program signal PS1. In this case, the outputs of the first to third output terminals CO11, CO12, CO13 of the lower bit comparator 412a are related to the logic level of the signals provided to the cascade input terminals CI11, CI12, CI13. Without a logic high level, a logic low level and a logic low level, respectively.

Accordingly, as in the embodiment of FIG. 5, the ground voltage GND is applied to the first cascade input terminal CI11 and the power supply voltage VDD is applied to the second and third cascade input terminals CI12 and CI13. In this case, if the lower four bits CS0, CS1, CS2, CS3 of the count signal CS are larger than the lower four bits PS10, PS11, PS12, PS13 of the first program signal PS1, Only the third output terminal CO13 has a logic high level, and the lower four bits CS0, CS1, CS2 and CS3 of the count signal CS and the lower four bits PS10, PS11 and PS12 of the first program signal PS1. When PS13 is the same, only the second output terminal CO12 has a logic high level, and the lower four bits CS0, CS1, CS2, and CS3 of the count signal CS are the lower four of the first program signal PS1. When the bits are smaller than the bits PS10, PS11, PS12, and PS13, only the first output terminal CO11 has a logic high level. In other words, the first comparison signal CA has the lower four bits CS0, CS1, CS2, and CS3 of the count signal CS than the lower four bits PS10, PS11, PS12, and PS13 of the first program signal PS1. Only when it is small, the second comparison signal CB has the lower four bits CS0, CS1, CS2, and CS3 of the count signal CS and the lower four bits PS10 and the first program signal PS1. Only when PS11, PS12, and PS13 are the same, they have a logic high level, and in other cases, the first and second comparison signals CA and CB each have a logic low level.

6 illustrates an example of the lower bit comparator 412a among the comparators included in the first binary comparator 410a of FIG. 5, the upper bit comparator 414 may also be the lower bit comparator of FIG. 6. It may have the same configuration as 412a. Accordingly, the first pulse width modulation signal PWM1 has a logic low level when the count signal CS is greater than or equal to the first program signal PS1, and the count signal CS is the first program signal PS1. If smaller, it may have a logic high level.

The four-channel pulse width modulated signal generating apparatus 100 according to an embodiment of the present invention generates four independent pulse width modulated signals PWM1, PWM2, PWM3, and PWM4, thereby reducing unnecessary power consumption and generating pulses. The size, manufacturing cost, and complexity of the width modulated signal generating apparatus can be reduced.

Meanwhile, although the four-channel pulse width modulated signal generating apparatus 100 for generating four pulse width modulated signals PWM1, PWM2, PWM3, and PWM4 has been described with reference to FIGS. 1 to 7, the present invention will be described in accordance with embodiments. The apparatus for generating a pulse width modulated signal according to embodiments of the present disclosure may be implemented to generate independent N pulse width modulated signals (N is a natural number of two or more). For example, the programmable logic unit 200 of FIG. 1 may be implemented to include N programmable logics, thereby generating N program signals based on an N-bit selection signal, and the 4-channel binary comparison unit 400. May be implemented in the form of an N-channel binary comparator that generates N pulse width modulated signals by including N binary comparators.

In addition, the pulse width modulated signal generating apparatus according to the embodiments of the present invention may be implemented to generate four independent pulse width modulated signals based on 4N (N is a natural number of 2 or more) bits. For example, the programmable logic unit 200 of FIG. 1 may be implemented to generate first to fourth program signals, each 4N bits, based on the 4N bit digital input signal, and the binary counter unit 300 may be implemented. The 4N binary comparison unit 400 compares the 4N bit count signal with the first through fourth program signals, each of which is 4N bits, to generate 4N bit count signals. It can be implemented to generate pulse width modulated signals PWM1, PWM2, PWM3, PWM4.

8 is a block diagram illustrating an electronic system 1000 including an apparatus for generating a 4-channel pulse width modulated signal, according to an exemplary embodiment.

Referring to FIG. 8, the electronic system 1000 may include a microprocessor 1100, a four-channel pulse width modulated signal generating device 1200, and a driver 1300.

The microprocessor 1100 may provide a clock signal CCK, a control signal CON, a digital input signal D, and a selection signal S. In one embodiment, the microprocessor 1100 may be a processor such as 80C51 or the like. The clock signal CCK may have a frequency (for example, 172.8 Khz) that divides the main clock signal (for example, 11.0592Mhz) of the microprocessor 1100 by a predetermined division ratio (for example, 64). The control signal CON is a signal for controlling the four-channel pulse width modulation signal generating device 1200, the digital input signal D may be 8 bits, and the selection signal S may be 4 bits. According to an embodiment, when the pulse width modulated signal generating apparatus 1200 is implemented to generate independent N pulse width modulated signals (N is a natural number of two or more), the selection signal S may be N bits. In addition, the digital input signal D may be 4N bits.

The four-channel pulse width modulated signal generating apparatus 1200 may be the four-channel pulse width modulated signal generating apparatus 100 of FIG. 1. The four-channel pulse width modulated signal generating apparatus 1200 latches the digital input signal D based on the logic level of each bit of the selection signal S, so that the first to fourth program signals PS1 and PS2, PS3, and PS4 are generated, and an 8-bit count signal CS that is sequentially up counted based on the clock signal CCK and the control signal CON is generated, and the count signal CS and the first through to The fourth program signals PS1, PS2, PS3, and PS4 are compared with each other to generate first to fourth pulse width modulation signals PWM1, PWM2, PWM3, and PWM4 independent of each other. The frequencies of the first to fourth pulse width modulation signals PWM1, PWM2, PWM3, and PWM4 are divided by the frequency of the clock signal CCK (for example, 172.8Khz) at a division ratio of 2 ⁸ , that is, 256 ( For example, 675 Hz). When the magnitude of the count signal CS is greater than or equal to the magnitude of the first to fourth program signals PS1, PS2, PS3, and PS4, respectively, the logic level of the first to fourth pulse width modulation signals is the first logic level. Respectively corresponding to, and when the magnitude of the count signal CS is smaller than the magnitude of the first to fourth program signals PS1, PS2, PS3, and PS4, respectively, the logic of the first to fourth pulse width modulation signals. The levels may correspond respectively to the second logic levels. The first logic level may be a logic low level, and the second logic level may be a logic high level.

The driver 1300 is driven by the first to fourth pulse width modulation signals PWM1, PWM2, PWM3, and PWM4. For example, the driving unit 1300 may be a voltage or current detection circuit that detects a voltage or a current based on the first to fourth pulse width modulation signals PWM1, PWM2, PWM3, and PWM4. In another example, the driver 1300 may be a light emitting diode circuit including light emitting diode elements that emit light based on the first to fourth pulse width modulation signals PWM1, PWM2, PWM3, and PWM4. According to an embodiment, the driver 1300 may be implemented to include any circuit or device driven by the first to fourth pulse width modulation signals PWM1, PWM2, PWM3, PWM4.

According to the present invention, by generating a plurality of independent pulse width modulated signals, it is possible to provide an apparatus for generating a pulse width modulated signal which reduces unnecessary power consumption and reduces size, manufacturing cost and complexity. Therefore, the present invention can be applied to an electronic system including the pulse width modulated signal generating device, and particularly to a system including a voltage, a current detection circuit, a light emitting diode circuit, and the like.

As described above, the present invention has been described with reference to a preferred embodiment of the present invention, but those skilled in the art may vary the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be understood that modifications and changes can be made.

Claims (7)

Receive an 8-bit digital input signal and a 4-bit selection signal and latch the digital input signal based on a logic level of each bit of the selection signal to generate first to fourth program signals each of 8 bits. Programmable logic section;
A binary counter unit which receives a clock signal and a control signal and generates an 8-bit count signal sequentially up counted based on the clock signal and the control signal;
A four-channel binary comparator configured to compare the count signal and the first to fourth program signals, respectively, to generate first to fourth pulse width modulation signals independent of each other; And
An output buffer unit for storing and outputting the first to fourth pulse width modulation signals;
The frequencies of the first to fourth pulse width modulation signals have a value obtained by dividing the frequency of the clock signal by a division ratio of 2 ⁸ , respectively.
When the magnitude of the count signal is greater than or equal to the magnitude of the first to fourth program signals, respectively, the logic level of the first to fourth pulse width modulation signals corresponds to a first logic level, respectively. When the magnitudes are respectively smaller than the magnitudes of the first to fourth program signals, the logic levels of the first to fourth pulse width modulation signals correspond to a second logic level, respectively,
The programmable logic unit,
Receiving the digital input signal and the first bit of the selection signal, and when the first bit of the selection signal is enabled, latches the digital input signal to generate the first program signal and generate the generated first program First programmable logic to store and output a signal and to output the stored first program signal when the first bit of the selection signal is disabled;
Receiving the digital input signal and the second bit of the selection signal, and when the second bit of the selection signal is enabled, latches the digital input signal to generate the second program signal and generate the generated second program Second programmable logic to store and output a signal and to output the stored second program signal when the second bit of the selection signal is disabled;
Receiving the digital input signal and the third bit of the selection signal, and when the third bit of the selection signal is enabled, latches the digital input signal to generate the third program signal and generate the generated third program Third programmable logic to store and output a signal and to output the stored third program signal when the third bit of the selection signal is disabled; And
Receiving the fourth bit of the digital input signal and the selection signal, when the fourth bit of the selection signal is enabled, latches the digital input signal to generate the fourth program signal and the generated fourth program A fourth programmable logic to store and output a signal and to output the stored fourth program signal when the fourth bit of the selection signal is disabled,
The first to fourth programmable logic is programmed by a user in a programming language and has different operating characteristics according to a programming method.
The four channel binary comparison unit,
Comparing the count signal with the first program signal and having the first logic level when the count signal is greater than or equal to the magnitude of the first program signal, and the magnitude of the count signal is greater than that of the first program signal. A first binary comparison unit configured to generate the first pulse width modulated signal having the second logic level when smaller than a magnitude;
Comparing the count signal with the second program signal and having the first logic level when the count signal is greater than or equal to the magnitude of the second program signal and the magnitude of the count signal is greater than that of the second program signal. A second binary comparison unit configured to generate the second pulse width modulated signal having the second logic level when smaller than a magnitude;
Comparing the count signal with the third program signal and having the first logic level when the magnitude of the count signal is greater than or equal to the magnitude of the third program signal and the magnitude of the count signal is greater than that of the third program signal. A third binary comparison unit configured to generate the third pulse width modulated signal having the second logic level when smaller than a magnitude; And
Comparing the count signal with the fourth program signal and having the first logic level when the count signal is greater than or equal to the magnitude of the fourth program signal and the magnitude of the count signal is greater than that of the fourth program signal. A fourth binary comparator for generating the fourth pulse width modulated signal having the second logic level when smaller than magnitude;
The first binary comparison unit,
Receiving a power supply voltage, a ground voltage, a lower 4 bits of the count signal and a lower 4 bits of the first program signal, and based on the power supply voltage and the ground voltage, the lower 4 bits of the count signal and the first program signal. A lower bit comparator that compares the lower four bits of and generates a first comparison signal and a second comparison signal; And
Receive the power supply voltage, the first comparison signal, the second comparison signal, the upper four bits of the count signal, and the upper four bits of the first program signal, and receive the power supply voltage, the first comparison signal, and the second An upper bit comparator that directly generates the first pulse width modulated signal by comparing the upper four bits of the count signal with the upper four bits of the first program signal based on a comparison signal,
The ground voltage is provided to the first cascade input terminal of the lower bit comparator, and the power supply voltage is provided to the second and third cascade input terminals of the lower bit comparator and the third cascade of the upper bit comparator. Provided to an input terminal, the first comparison signal is provided to a first cascade input terminal of the upper bit comparator, the second comparison signal is provided to a second cascade input terminal of the upper bit comparator,
And the second to fourth binary comparison units each have the same configuration as the first binary comparison unit. delete delete delete delete A microprocessor providing a clock signal, a control signal, an 8-bit digital input signal and a 4-bit select signal;
Latching the digital input signal based on a logic level of each bit of the selection signal to generate first to fourth program signals, each of which is eight bits, and sequentially counting up based on the clock signal and the control signal; A four-channel pulse width modulation signal generation device generating a count signal of bits and generating first to fourth pulse width modulation signals independent of each other by comparing the count signal and the first to fourth program signals, respectively; And
A driving unit driven based on the first to fourth pulse width modulation signals,
The frequencies of the first to fourth pulse width modulation signals have a value obtained by dividing the frequency of the clock signal by a division ratio of 2 ⁸ , respectively.
When the magnitude of the count signal is greater than or equal to the magnitude of the first to fourth program signals, respectively, the logic level of the first to fourth pulse width modulation signals corresponds to a first logic level, respectively. When the magnitudes are respectively smaller than the magnitudes of the first to fourth program signals, the logic levels of the first to fourth pulse width modulation signals correspond to a second logic level, respectively,
The four-channel pulse width modulated signal generating device,
A programmable logic section programmed to receive the digital input signal and the selection signal and to generate the first to fourth program signals by latching the digital input signal based on a logic level of each bit of the selection signal;
A binary counter unit configured to receive the clock signal and the control signal and generate an 8-bit count signal sequentially up counted based on the clock signal and the control signal;
A four-channel binary comparator configured to compare the count signal and the first to fourth program signals, respectively, to generate first to fourth pulse width modulation signals independent of each other; And
An output buffer unit for storing and outputting the first to fourth pulse width modulation signals;
The programmable logic unit,
Receiving the digital input signal and the first bit of the selection signal, and when the first bit of the selection signal is enabled, latches the digital input signal to generate the first program signal and generate the generated first program First programmable logic to store and output a signal and to output the stored first program signal when the first bit of the selection signal is disabled;
Receiving the digital input signal and the second bit of the selection signal, and when the second bit of the selection signal is enabled, latches the digital input signal to generate the second program signal and generate the generated second program Second programmable logic to store and output a signal and to output the stored second program signal when the second bit of the selection signal is disabled;
Receiving the digital input signal and the third bit of the selection signal, and when the third bit of the selection signal is enabled, latches the digital input signal to generate the third program signal and generate the generated third program Third programmable logic to store and output a signal and to output the stored third program signal when the third bit of the selection signal is disabled; And
Receiving the fourth bit of the digital input signal and the selection signal, when the fourth bit of the selection signal is enabled, latches the digital input signal to generate the fourth program signal and the generated fourth program A fourth programmable logic to store and output a signal and to output the stored fourth program signal when the fourth bit of the selection signal is disabled,
The first to fourth programmable logic is programmed by a user in a programming language and has different operating characteristics according to a programming method.
The four channel binary comparison unit,
Comparing the count signal with the first program signal and having the first logic level when the count signal is greater than or equal to the magnitude of the first program signal, and the magnitude of the count signal is greater than that of the first program signal. A first binary comparison unit configured to generate the first pulse width modulated signal having the second logic level when smaller than a magnitude;
Comparing the count signal with the second program signal and having the first logic level when the count signal is greater than or equal to the magnitude of the second program signal and the magnitude of the count signal is greater than that of the second program signal. A second binary comparison unit configured to generate the second pulse width modulated signal having the second logic level when smaller than a magnitude;
Comparing the count signal with the third program signal and having the first logic level when the magnitude of the count signal is greater than or equal to the magnitude of the third program signal and the magnitude of the count signal is greater than that of the third program signal. A third binary comparison unit configured to generate the third pulse width modulated signal having the second logic level when smaller than a magnitude; And
Comparing the count signal with the fourth program signal and having the first logic level when the count signal is greater than or equal to the magnitude of the fourth program signal and the magnitude of the count signal is greater than that of the fourth program signal. A fourth binary comparator for generating the fourth pulse width modulated signal having the second logic level when smaller than magnitude;
The first binary comparison unit,
Receiving a power supply voltage, a ground voltage, a lower 4 bits of the count signal and a lower 4 bits of the first program signal, and based on the power supply voltage and the ground voltage, the lower 4 bits of the count signal and the first program signal. A lower bit comparator that compares the lower four bits of and generates a first comparison signal and a second comparison signal; And
Receive the power supply voltage, the first comparison signal, the second comparison signal, the upper four bits of the count signal, and the upper four bits of the first program signal, and receive the power supply voltage, the first comparison signal, and the second An upper bit comparator that directly generates the first pulse width modulated signal by comparing the upper four bits of the count signal with the upper four bits of the first program signal based on a comparison signal,
The ground voltage is provided to the first cascade input terminal of the lower bit comparator, and the power supply voltage is provided to the second and third cascade input terminals of the lower bit comparator and the third cascade of the upper bit comparator. Provided to an input terminal, the first comparison signal is provided to a first cascade input terminal of the upper bit comparator, the second comparison signal is provided to a second cascade input terminal of the upper bit comparator,
The second to fourth binary comparison units each have the same configuration as the first binary comparison unit. delete

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