KR101043199B1 - Multi-core cache circuit using single-core cache controller, cache device and semiconductor device including the same, and method for controlling the cache memory - Google Patents

Abstract

PURPOSE: A multi core cache circuit using a single core cache controller, a cache device and a semiconductor device including the same, and a cache memory control method are provided to simplify a structure and reduce traffic by minimizing a change of the structure and using the existing single core cache controller. CONSTITUTION: A cache memory unit(110) includes cache lines and stores data, tag information and status information of the cache lines. A single core cache controller(120) offers a data request signal based on a request signal of a core connected to a cache circuit and the data of the cache memory unit corresponding to the data request signal to the core connected to the cache circuit. A command processor(130) offers a state modification signal for modifying the status information of the cache lines and the data saved in the cache memory unit to outside.

Description

Multi-core cache circuit using single-core cache controller, cache device and semiconductor device including the same, and method for controlling the cache memory}

The present invention relates to a cache memory control technique, and more particularly, to a cache circuit for a multi-core, a cache device including the same, a semiconductor device and a cache memory control method.

As technology advances, the operating speed of the processor is faster than that of the main memory, and a small but high speed cache memory is used to solve the problem caused by the speed difference between the processor and the main memory. In addition, multi-core processors have been developed in which a plurality of cores are provided in one processor and a plurality of cores share and process tasks. In a multi-core processor system a plurality of cores are each connected to corresponding cache controllers, the corresponding cache controllers respectively controlling cache memories. In addition, the cache controller in a multi-core environment may include a coherence management unit (CMU) to maintain coherence of shared data between cores.

In general, MESI protocols are employed that include line state information between cache memories to maintain consistency. Under the MESI protocol, each line of the cache memory may be represented in four states: modified state (Modified, M), exclusive state (Exclusive, E), shared state (Shared, S), and invalid state (Invalid, I). However, in order to apply the MESI protocol and display line sharing information between cache lines, a complicated control process must be added, thus increasing the complexity of the structure of the cache controller and increasing the manufacturing cost.

In addition, in order to represent and manage line state information between cache memories according to the MESI protocol as described above, a consistency management unit for maintaining consistency among a plurality of cores and a synchronization state for maintaining line state information between cache controllers may be provided. Additional traffic is required.

One object of the present invention for solving the above problems is to provide a cache circuit for multi-core using a single-core cache controller is simple in structure and can reduce traffic.

Another object of the present invention is to provide a cache device and a semiconductor device including a cache circuit for multi-core which is inexpensive, simple in structure, and which can reduce traffic.

It is still another object of the present invention to provide a cache memory control method for multi-cores that is simple in structure and can reduce traffic.

In order to achieve the above object of the present invention, it is included in a multi-core semiconductor device having a plurality of cores according to an embodiment of the present invention, the cache circuit connected to one of the plurality of cores is a cache memory unit, single It includes a core cache controller and a command processor. The cache memory unit includes a plurality of cache lines, and stores data, tag information, and state information of the cache lines. The cache controller for the single core provides a data request signal based on a request signal received from a core connected to the cache circuit among the plurality of cores, and stores the data in the cache memory unit corresponding to the data request signal in the cache circuit. To the core connected with. The command processor provides a state change signal for changing state information of some of the cache lines based on a change signal input from the outside, and provides a portion of the data stored in the cache memory unit to the outside.

In example embodiments, the state information of the cache lines may be encoded regardless of whether the data stored in the cache memory unit is shared.

The method may further include a selector configured to select one of the data request signal and the state change signal and provide the selected one to the cache memory unit. The cache memory unit includes a plurality of cache lines and cache memory for storing the data; And a tag memory configured to store the tag information and state information of the cache lines.

The data request signal may include a first data request signal for requesting the data stored in the cache memory and a second data request signal for controlling the tag memory in response to the first data request signal. The state change signal may include a first state change signal for controlling the cache memory and a second state change signal for controlling the tag memory when changing state information of the cache lines. The selector may include a first selector configured to select one of the first data request signal and the first state change signal to provide to the cache memory; And a second selector for selecting one of the second data request signal and the second state change signal to provide the tag memory.

In order to achieve the above object of the present invention, a cache device included in a multi-core semiconductor device having a plurality of cores according to an embodiment of the present invention includes a plurality of multi-core cache circuits and a consistency management circuit. . The plurality of multi-core cache circuits are respectively connected to one of the plurality of cores and provide stored data to the connected cores based on a request signal received from the connected cores, respectively. The consistency management circuit maintains the consistency of the data stored in the plurality of multi-core cache circuits. Each of the plurality of multi-core cache circuits includes a cache memory unit, a single core cache controller, and a command processor. The cache memory unit includes a plurality of cache lines, and stores data, tag information, and state information of the cache lines. The single core cache controller provides a data request signal based on the request signal, and provides data to the connected core to the cache memory unit corresponding to the data request signal. The command processor provides a state change signal for changing state information of some of the cache lines based on a change signal input from the consistency management circuit, and converts some of the data stored in the cache memory unit into the consistency management circuit. To provide.

In example embodiments, the state information of the cache lines may be encoded regardless of whether the data stored in the cache memory unit is shared.

The method may further include a selector configured to select one of the data request signal and the state change signal and provide the selected one to the cache memory unit.

In an embodiment, the consistency management circuit may include a plurality of tag memories respectively storing copies of the tag information and the state information stored in the cache memory unit of the plurality of multi-core cache circuits. In this case, the state information of the cache lines stored in the cache memory section of the plurality of multi-core cache circuits and the copy of the state information of the cache lines stored in the plurality of tag memories of the consistency management circuit, respectively, are mutually different. It can be encoded differently.

In order to achieve the above object of the present invention, a multi-core semiconductor device having a plurality of cores according to an embodiment of the present invention includes a main memory, a cache device for a multi-core, and a processor. The cache apparatus for the multi-core stores some data among the data of the main memory, and is connected to one of the plurality of cores, respectively, and stores the stored data to the connected core based on a request signal received from the connected core. A plurality of multi-core cache circuits each provided; And a consistency management circuit for maintaining the consistency of the data stored in the plurality of multi-core cache circuits. The processor includes a plurality of cores and exchanges data with the main memory through the cache device for the multi-cores. Each of the plurality of multi-core cache circuits includes a cache memory unit, a single core cache controller, and a command processor. The cache memory unit includes a plurality of cache lines, and stores data, tag information, and state information of the cache lines. The single core cache controller provides a data request signal based on the request signal, and provides data to the connected core to the cache memory unit corresponding to the data request signal. The command processor provides a state change signal for changing state information of some of the cache lines based on a change signal input from the consistency management circuit, and converts some of the data stored in the cache memory unit into the consistency management circuit. To provide.

In order to achieve the above object of the present invention, in a multi-core semiconductor device having a plurality of cores according to an embodiment of the present invention, a cache controller including a plurality of cache lines is controlled using a cache controller for a single core. The method provides a data request signal based on a request signal received from a core in communication with the cache memory among the plurality of cores. Provide data stored in the cache memory and corresponding to the data request signal to the core in communication with the cache memory. A state change signal is provided based on a change signal input from the outside to change state information of some of the cache lines. Some of the data stored in the cache memory are provided to the outside.

In an embodiment, the state information of the cache lines may be encoded regardless of whether the data stored in the cache memory is shared.

The multi-core cache circuit according to the embodiments of the present invention as described above can solve the data sharing problem between cores while minimizing a structural change by using an existing single core cache controller.

In addition, the multi-core cache apparatus according to the embodiments of the present invention may reduce traffic for maintaining state synchronization between the consistency management unit and the respective cache circuits.

1 is a block diagram illustrating a cache circuit included in a multi-core semiconductor device having a plurality of cores according to an exemplary embodiment of the present invention.
2 is a block diagram illustrating a cache circuit included in a multi-core semiconductor device having a plurality of cores according to another exemplary embodiment of the present disclosure.
3 is a block diagram illustrating a cache device included in a multi-core semiconductor device having a plurality of cores according to an embodiment of the present invention.
4 is a block diagram illustrating a multi-core semiconductor device according to an embodiment of the present invention.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for the components.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

On the other hand, when an embodiment is otherwise implemented, a function or operation specified in a specific block may occur out of the order specified in the flowchart. For example, two consecutive blocks may actually be performed substantially simultaneously, and the blocks may be performed upside down depending on the function or operation involved.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. The same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

1 is a block diagram illustrating a cache circuit included in a multi-core semiconductor device having a plurality of cores according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the cache circuit 100 includes a cache memory unit 110, a single core cache controller 120, a command processor 130, and a selector 140. The cache circuit 100 may further include an AND gate 122 for clock gating.

The cache memory unit 110 includes a plurality of cache lines 110-1, 110-2,..., 110-n and includes data 117, tag information 115, and state information of the cache lines. (Hereinafter, referred to as line status information). In one embodiment, the cache memory unit 110 may be implemented as a memory capable of high speed operation, such as SRAM. In addition, the cache memory unit 110 may be implemented by being divided into a cache memory for storing the data 117 and tag information 115 and a tag memory for storing the line state information. A configuration in which the cache memory unit 110 is separated and implemented as described above will be described later with reference to FIG. 2.

The dirty (D) flag 111 includes data whose cache lines 110-1, 110-2,..., 110-n are changed from data stored in main memory included in the multi-core semiconductor device. Valid (V) flag 113 is 1-bit information indicating whether cache lines 110-1, 110-2, ..., 110-n are activated. That is, the dirty flag 111 and the valid flag 113 represent the line state information and store it in the cache memory unit 110.

In one embodiment, the line state information may be encoded regardless of whether the data 117 stored in the cache lines 110-1, 110-2,..., 110-n is shared. That is, the shared (S) flag may not be stored in the cache memory unit 110, and the cache circuit 100 may operate in the same manner as a conventional single core cache controller without considering whether to share the stored data. Can be. In the MESI protocol, cache lines 110-1, 110-2, ..., 110-n are modified state (Modified, M), exclusive state (Exclusive, E), shared state (Shared, S), and invalid state. It can have four states of (Invalid, I). The four states may be expressed according to the values of the dirty flag 111 and the valid flag 113. For example, in one embodiment of the present invention, any cache line has a value of D = 1, V = 1 when in a modified state, and has a value of D = 0, V = 1 when in an exclusive state, and a shared state. In the case of D = 0 and V = 1, D has an arbitrary value and V = 0. That is, the exclusive state and the shared state may be encoded in the same manner. In order to change line state information of respective cache memories in a cache controller of a multi-core environment, a separate communication is required, which is defined as traffic in the present specification. As described above, when the exclusive state and the shared state are encoded in the same manner, unnecessary traffic may be reduced in the multi-core semiconductor device. Detailed description thereof will be described later with reference to FIG. 3.

The single core cache controller 120 may provide a data request signal DREQ based on a request signal REQ received from one of the plurality of cores, and may include a cache memory unit corresponding to the data request signal DREQ. Data RDAT of 110 is output and provided to one of the plurality of cores. That is, the single core cache controller 120 checks whether the data RDAT requested from the core connected to the cache circuit 100 among the plurality of cores is in the cache memory unit 110 to check the cache memory unit 110. If the requested data RDAT is present, the requested data RDAT is read from the cache memory unit 110, and if the requested data RDAT is not present in the cache memory unit 110, the requested data RDAT is read from the main memory. ) And performs the same operation as that of the conventional cache controller which provides the core to the core connected to the cache circuit 100. In an exemplary embodiment, the cache controller 120 for a single core may include a plurality of semiconductor devices such as transistors and a plurality of logic devices such as a comparator, a buffer, and a logic gate.

The request signal REQ and the data request signal DREQ include a plurality of addresses, data in (Din), data out (Dout), chip select (CS), read / write (RW), and bit enable (BE) signals. It may be made in a combination, and it may be checked whether the requested data RDT is present in the cache memory unit 110. In an exemplary embodiment, the operation of the single core cache controller 120 may be controlled according to an internal clock signal gCLK, which will be described later.

The command processor 130 changes the state information of some of the cache lines 110-1, 110-2,..., 110-n based on the change signal CS input from the outside. Provide (SCS). When the data is read from or written to the cache memory 110 by the cache memory 110, the line state information of the cache lines 110-1, 110-2,..., 110-n may be changed. Can be. For example, when reading data of a cache line that is in an invalid state (I), the invalid state (I) may be changed into an exclusive state (E) or a shared state (S).

The change signal CS is a signal provided by the coherence management circuit included in the multi-core semiconductor device to ensure coherence of cache memories included in the multi-core semiconductor device. The state change signal SCS is a signal generated by decoding the change signal CS, and may be composed of a combination of signals for accessing the cache memory unit 110. The change signal CS and the state change signal SCS may be formed by a combination of a plurality of command signals and an address. In one embodiment, the change signal CS may be invalidated lines, read & clean lines, read & invalidate lines, etc. with respect to the cache memory unit 110. You can send a command.

The command processor 130 receives a portion DAT of the data 117 stored in the cache memory 110 and provides it to the external, that is, the consistency management circuit. The data DAT provided to the consistency management circuit may be transferred to another cache memory or main memory included in the multi-core semiconductor device, and the cache memories included in the multi-core semiconductor device may be processed by the consistency management circuit. To ensure consistency.

The selector 140 selects one of the data request signal DREQ and the state change signal SCS, and provides the selected memory 140 to the cache memory 110. That is, the selector 140 may arbitrate and selectively process data requests from one of the plurality of cores and line state change requests from the consistency management circuit. For example, the selector 140 selects the data request signal DREQ and provides the data to the cache memory 110 to store the data RDAT stored in the cache memory 110 and corresponding to the data request signal DREQ. ) May be provided to a core connected to the cache circuit 100. In addition, the selector 140 selects a state change signal SCS to change the line state information of a cache line requiring a state change due to the data provision or writing, and the memory unit 110 to maintain cache coherency. ) May provide some data DAT to the consistency management circuit or write data stored in the main memory to the cache memory unit 110.

The selector 140 may generate a ready signal READY and provide it to the AND gate 122 for clock gating. In one embodiment, the cache controller 120 and the selector 140 for a single core may be implemented as a finite state machine (FSM) to send and receive a response within a predetermined period, the ready signal (READY) is When the selector 140 responds to the request of the single core cache controller 120 within the predetermined period, the selector 140 has an active state, that is, a logic high state, If the selector 140 fails to respond within the predetermined period, the selector 140 has an inactive state, that is, a logic low state, indicating that the selector 140 is not ready to perform the process.

The AND gate 122 for clock gating performs an AND operation on an external clock signal CLK, a clock enable signal CLKEN, and a ready signal READY to generate an internal clock signal gCLK to generate a single core cache controller 120. ) Can be provided. When the ready signal READY is in a logic high state, that is, when the selector 140 responds to the request of the single core cache controller 120 within the predetermined period, the external clock signal CLK as in the general case. ) And the cache controller 120 for a single core are operated based on the clock enable signal CLKEN. On the other hand, when the ready signal READY is in a logic low state, that is, when the selector 140 does not respond to the request of the single core cache controller 120 within the predetermined period, the selector 140 Since it is not ready to perform the process, the internal clock signal gCLK may be inactivated to delay the operation of the single core cache controller 120 until the selector 140 is ready to perform the process.

2 is a block diagram illustrating a cache circuit included in a multi-core semiconductor device having a plurality of cores according to another exemplary embodiment of the present disclosure.

Referring to FIG. 2, the cache circuit 200 includes a cache memory 210, a single core cache controller 220, a command processor 230, and a selector 240. The cache circuit 200 may further include an AND gate 222 for clock gating.

Compared to the cache circuit 100 of FIG. 1, the cache circuit 200 of FIG. 2 has a configuration different from that of the cache memory 210 and the selector 240, and a signal flow according thereto. Have Therefore, description overlapping with the description of the cache circuit 100 of FIG. 1 will be omitted.

The cache memory unit 210 includes a cache memory 211 and a tag memory 215. The cache memory 211 includes a plurality of cache lines 211-1, 211-2,..., 211-n and stores data 212. The tag memory 215 corresponds to the tag lines 215-1, 215-2, ..., 215-n respectively corresponding to the cache lines 211-1, 211-2, ..., 211-n. It includes, and stores the tag information 218 and the line state information. The line state information may be determined according to the values of the dirty flag 216 and the valid flag 217 of the tag memory 215.

The single core cache controller 220 provides the first and second data request signals DREQ1 and DREQ2 based on the request signal REQ received from the core connected to the cache circuit 200 among the plurality of cores. do. The first data request signal DREQ1 requests a portion RDAT of the data 212 stored in the cache memory 211, and the second data request signal DREQ2 tags in response to the first data request signal DREQ1. The memory 215 can be controlled. The single core cache controller 220 may provide the data RDAT of the cache memory 211 corresponding to the first data request signal DREQ1 to the connected core. In one embodiment, the single core cache controller 220 may receive output from both the cache memory 211 and the tag memory 215.

The command processor 230 may determine a portion of the cache lines 211-1, 211-2,..., 211-n based on the change signal CS provided from the consistency management circuit included in the multi-core semiconductor device. First and second state change signals SCS1 and SCS2 are provided to change the line state information. The first state change signal SCS1 controls the cache memory 211 when the line state information is changed, and the second state change signal SCS2 controls the tag memory 215 when the state information is changed. . In addition, the command processor 230 receives a portion (DAT) of the data 212 stored in the cache memory 211 and provides it to the consistency management circuit. In one embodiment, the command processor 230 may receive an output from the cache memory 211.

The selector 240 arbitrates and selectively processes a data request from one of the plurality of cores and a line state change request from the consistency management circuit, and processes the first selector 242 and the second selector 244. Include. The first selector 242 selects one of the first data request signal DREQ1 and the first state change signal SCS1 and provides it to the cache memory 211. The second selector 244 selects one of the second data request signal DREQ2 and the second state change signal SCS2 and provides it to the tag memory 215.

The first and second selectors 242 and 244 may generate first and second ready signals READY1 and READY2 indicating whether the process may be performed and provide them to the AND gate 222. The AND gate 222 generates an internal clock signal gCLK by performing an AND operation on the external clock signal CLK, the clock enable signal CLKEN, and the ready signals READY1 and READY2, and generates an internal clock signal gCLK. The single core cache controller 220 may be provided to control the single core cache controller 220.

The multi-core cache controller included in the conventional multi-core cache circuit performs both a function of reading data from a cache memory and a function of changing state information of cache lines and controlling line sharing information between the cache lines. To this end, many modifications of the conventional single-core cache controller have been modified, thus increasing the complexity and manufacturing cost of the circuit. In contrast, the multi-core cache circuits 100 and 200 according to the embodiments of the present invention illustrated in FIGS. 1 and 2 use the conventional single core cache controllers 120 and 220 as they are, and are relatively simple. The command processor 130 and 230 and the selectors 140 and 240 that can be implemented are added to the present invention. That is, the conventional single core cache controllers 120 and 220 perform a function of reading data from the cache memory according to a request of one of the plurality of cores, and the command processor 130 or 230 of the consistency management circuit Change the state information of cache lines and control line sharing information between the cache lines according to a request, and selectors 140 and 240 selectively process the request of the core and the consistency management circuit. Is implemented. Therefore, the multi-core cache circuits 100 and 200 according to the embodiments of the present invention can solve the line sharing problem while reducing the complexity and manufacturing cost compared to the conventional multi-core cache circuit.

3 is a block diagram illustrating a cache device included in a multi-core semiconductor device having a plurality of cores according to an embodiment of the present invention.

Referring to FIG. 3, the cache apparatus 300 includes a plurality of multi-core cache circuits 310, 320, 330, and 340 and a consistency management circuit 360.

A plurality of multi-core cache circuits 310, 320, 330, and 340 are respectively connected to one of the plurality of cores and provide stored data to the connected core based on a request signal received from the connected core. . Each of the plurality of multi-core cache circuits 310, 320, 330, and 340 may be the multi-core cache circuits 100 and 200 of FIG. 1 or 2. For example, the first multi-core cache circuit 310 may include a first cache memory unit, a first single core cache controller, and a first command processor, and may further include a first selector.

State information of a plurality of cache lines included in a cache memory unit in the plurality of multi-core cache circuits 310, 320, 330, and 340 may be encoded regardless of whether the data stored in the cache lines is shared. That is, the state information of the cache lines in the plurality of multi-core cache circuits 310, 320, 330, and 340 may be encoded in the same manner as the conventional single core cache circuit.

Although FIG. 3 illustrates a multi-core cache device 300 that includes four multi-core cache circuits 310, 320, 330, and 340, the multi-core cache device 300 may be random in accordance with an embodiment. It may include a number of cache circuits for multi-core.

The consistency management circuit 360 maintains the consistency of the data stored in the plurality of multi-core cache circuits 310, 320, 330, and 340. The consistency management circuit 360 may arbitrate data transmission and reception between the cache memory unit and the main memory included in the multi-core semiconductor device. The consistency management circuit 360 may include an arbitration unit 362, a consistency management unit 366, and a plurality of tag memories 367, 368, 369, and 370.

The arbitration unit 362 is configured based on the request signals REQ1, REQ2, REQ3, and REQ4 provided from the plurality of cores through the plurality of multi-core cache circuits 310, 320, 330, and 340, respectively. It arbitrates data transmission and reception between the multi-core cache circuits 310, 320, 330, and 340 and the main memory. That is, the arbitration unit 362 may provide data DAT1, DAT2, and DAT3 provided from the plurality of multi-core cache circuits 310, 320, 330, and 340 based on the request signals REQ1, REQ2, REQ3, and REQ4. , DAT4) may be provided to the consistency management unit 366, and data received from the main memory through the consistency management unit 366 may be stored in the plurality of multi-core cache circuits 310, 320, 330, and 340. Can be provided in one. In one embodiment, the arbitration unit 362 may be implemented including a multiplexer.

The consistency management unit 366 maintains the consistency of data stored in the cache memory unit of the plurality of multi-core cache circuits 310, 320, 330, and 340. The consistency manager 366 may use a snooping protocol to maintain the consistency. In the multi-core system, responsibility for consistency management is distributed to all cache controllers connected to the multi-core, and the consistency management unit 366 includes a plurality of multi-core cache circuits 310, 320, 330, and 340. Snooping to access The consistency management unit 366 copies the tag information and the line state information stored in the cache memory unit to the plurality of multi-core cache circuits 310, 320, 330, and 340, respectively, so that the plurality of tag memories 367, 368, 369 and 370, and when the line state information of the cache memory unit needs to be changed, the plurality of multi-core cache circuits 310 corresponding to one of the change signals CS1, CS2, CS3, and CS4 are stored. It may be provided to one of the 320, 330, 340 to maintain the consistency of the data stored in the cache memory unit.

The plurality of tag memories 367, 368, 369, and 370 store copies of the tag information and the line state information, respectively. As described above, a copy of the tag information and the line state information is stored in the consistency management circuit 360, so that the plurality of multi-core cache circuits 310, 320, 330, and 340 are performed each time the consistency management is performed. By eliminating the need to access the cache memory portion of the cache, the performance degradation of the multi-core cache device 300 is prevented.

The plurality of tag memories 367, 368, 369, and 370 may include a dirty (D) flag and a valid (V) flag, and additionally include a shared (S) flag indicating a shared state of the cache line. have. In addition, a copy of the line state information stored in the plurality of tag memories 367, 368, 369, and 370 may be provided based on a MESI protocol. The copy of the line state information may be encoded in the consistency management unit 366, in which case the line state information stored in the cache memory unit of the plurality of multi-core cache circuits 310, 320, 330, and 340, respectively. And copies of the line state information stored in the plurality of tag memories 367, 368, 369, and 370 may be encoded differently. For example, the line state information stored in the cache memory units of the plurality of multi-core cache circuits 310, 320, 330, and 340, respectively, may be a combination of the dirty flag and the valid flag as described with reference to FIG. 1. Can be encoded, and the exclusive state and the shared state can be encoded equally. On the other hand, the copy of the line state information stored in the plurality of tag memories 367, 368, 369, and 370 has values of S = 0, D = 1, and V = 1 when any cache line is in a modified state. , In the exclusive state, S = 0, D = 0, V = 1, in the shared state S = 1, D = 0, V = 1, in the invalid state, S, D is random It can have a value of V = 0.

In the cache device for a multi-core based MESI protocol, a state change of cache lines according to data read and write requests is shown in Table 1 below.

TABLE 1

When a cache line in an invalid (I) state is read as shown in Table 1 above, the cache line in the invalid (I) state is exclusive depending on whether the same line exists in another cache memory in the cache device (E). ) Or shared (S) state. That is, if it is determined by the coherence management circuit in the cache device that there is a line in which the same data is stored in another cache memory, the state is changed to the shared (S) state. E) The state is changed. Therefore, after waiting for a result of the processing and determination of the consistency management circuit, the cache line in the invalid (I) state may be changed to an exclusive (E) or shared (S) state. In other words, additional traffic is required for state synchronization between the consistency management circuit and the cache line.

However, as in the embodiment of the present invention, when the exclusive (E) state and the shared (S) state are identically encoded in the cache memory unit in the multi-core cache circuits 310, 320, 330, and 340, consistency management is performed. The state of the cache line of the cache memory unit may be changed without waiting for the determination result of the circuit 360. In addition, the determination result of the consistency management circuit 360 may be stored in the plurality of tag memories 367, 368, 369, and 370 including the sharing flag to distinguish the exclusive (E) state from the shared (S) state. . That is, the final state of the cache line may be known regardless of the processing result of the consistency management circuit 360, and the traffic for synchronizing the state of the cache line with the consistency management circuit 360 may be reduced.

4 is a block diagram illustrating a multi-core semiconductor device according to an embodiment of the present invention.

Referring to FIG. 4, the multi-core semiconductor device 400 includes a processor 410, a multi-core cache device 430, and a main memory 450.

When the processor 410 requests data, the main memory 450 provides the requested data through the multi-core cache device 430.

Processor 410 includes a plurality of cores 412, 414, 416, 418. The processor 410 receives data from the multi-core cache device 430 when the requested data is in the cache memory of the multi-core cache device 430, and if the requested data is not in the cache memory, the main memory 450. Data is requested from the main memory 450 to receive data from the multi-core cache device 430.

The multi-core cache device 430 may be the multi-core cache device 300 of FIG. 3. The multi core cache device 430 includes a plurality of multi core cache circuits 432, 434, 436, and 438 and a consistency management circuit 440.

The plurality of multi core cache circuits 432, 434, 436, and 438 may be the multi core cache circuits 100 and 200 of FIG. 1 or 2, respectively. The plurality of multi-core cache circuits 432, 434, 436, 438 store some of the data in the main memory 450 and request received from one of the plurality of cores 412, 414, 416, 418. Provide the requested data based on the signal. For example, the first multi-core cache circuit 432 is connected to the first core 410, and based on the request signal received from the first core 410, the requested data to the first core 410 To provide.

The consistency management circuit 440 maintains the consistency of the data stored in the plurality of multi-core cache circuits 432, 434, 436, and 438.

Although FIG. 4 illustrates a multi-core semiconductor device 400 including four cores 412, 414, 416, 418, the multi-core semiconductor device 400 may include any number of cores in accordance with an embodiment. Can be.

Hereinafter, a method of controlling the cache memory 110 included in the multi-core semiconductor device 400 having a plurality of cores according to an exemplary embodiment will be described with reference to FIGS. 1, 3, and 4.

The single core cache controller 120 may generate a data request signal DREQ based on a request signal REQ received from a core communicating with the cache memory 110 among the plurality of cores 412, 414, 416, and 418. to provide. The request signal REQ and the data request signal DREQ may be a combination of a plurality of addresses, Din, Dout, CS, RW, and BE signals.

The cache memory 110 communicates the data RDAT corresponding to the data request signal DREQ among the stored data 117 with the cache memory 110 among the plurality of cores 412, 414, 416, and 418. To the core.

The command processor 130 provides state change information SCS based on the change signal CS input from the consistency management circuit 360. The change signal CS and the state change signal SCS may be formed by a combination of a plurality of command signals and an address. On the basis of the state change information (SCS), the cache line of the cache line (110-1, 110-2, ..., 110-n) of the cache line that needs to change the state by reading or writing the data 117 Line status information is changed. The line state information may be encoded regardless of whether the data stored in the cache line is shared.

The command processor 130 provides a part DAT of the data 117 stored in the cache memory 110 to the consistency management circuit 360. The consistency management circuit 360 may provide data DAT to another cache memory or main memory to maintain consistency of data of the cache memories included in the multi-core semiconductor device 400.

According to the present invention, it is possible to solve the problem of resource sharing between cores while minimizing the structural change, and to provide the cache circuit for the multi-core which can reduce the traffic, thereby bringing the performance improvement of the multi-core cache device and the semiconductor device, The CPU may be implemented as a core, a processor, and a computer including the same.

As described above, the present invention has been described with reference to a preferred embodiment of the present invention, but those skilled in the art may vary the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be understood that modifications and changes can be made.

Claims (13)

A cache circuit included in a multi-core semiconductor device having a plurality of cores and connected to one of the plurality of cores,
A cache memory unit including a plurality of cache lines and storing data, tag information, and state information of the cache lines;
Providing a data request signal based on a request signal received from a core connected to the cache circuit among the plurality of cores, and providing data of the cache memory unit corresponding to the data request signal to the core connected to the cache circuit; Cache controller for single core; And
A multi-command processing unit configured to provide a state change signal for changing state information of some of the cache lines based on a change signal input from an external device, and provide a portion of the data stored in the cache memory unit to the outside; Cache circuit for the core. The cache circuit of claim 1, wherein the state information of the cache lines is encoded regardless of whether the data stored in the cache memory unit is shared. The cache circuit of claim 1, further comprising: a selector configured to select one of the data request signal and the state change signal and provide the selected one to the cache memory unit. The method of claim 3, wherein the cache memory unit,
A cache memory including the plurality of cache lines and storing the data; And
And a tag memory configured to store the tag information and the state information of the cache lines. The data request signal of claim 4, wherein the data request signal includes a first data request signal for requesting the data stored in the cache memory and a second data request signal for controlling the tag memory in response to the first data request signal. The state change signal may include a first state change signal for controlling the cache memory and a second state change signal for controlling the tag memory when changing state information of the cache lines.
A first selector for selecting one of the first data request signal and the first state change signal to provide to the cache memory; And
And a second selector for selecting one of the second data request signal and the second state change signal to provide to the tag memory. A cache device included in a multi-core semiconductor device having a plurality of cores, the cache device comprising:
A plurality of multi-core cache circuits, each connected to one of the plurality of cores, each of which provides stored data to the connected core based on a request signal received from the connected core; And
A consistency management circuit for maintaining consistency of the data stored in the plurality of multi-core cache circuits,
Each of the plurality of multi-core cache circuits,
A cache memory unit including a plurality of cache lines and storing data, tag information, and state information of the cache lines;
A cache controller for a single core that provides a data request signal based on the request signal, and provides data of the cache memory unit corresponding to the data request signal to the connected core; And
A command for providing a state change signal for changing state information of some of the cache lines based on a change signal input from the consistency management circuit, and providing a portion of the data stored in the cache memory section to the consistency management circuit. Cache device for multi-core including a processing unit. The cache apparatus of claim 6, wherein the state information of the cache lines is encoded regardless of whether the data stored in the cache memory unit is shared. The cache apparatus of claim 6, further comprising a selector configured to select one of the data request signal and the state change signal and provide the selected one to the cache memory. The method of claim 6, wherein the consistency management circuit,
And a plurality of tag memories respectively storing copies of the tag information and the state information stored in the cache memory unit of the plurality of multi-core cache circuits. The method of claim 9, wherein the state information of the cache lines respectively stored in the cache memory unit of the plurality of multi-core cache circuits and the state information of the cache lines stored in the plurality of tag memories of the consistency management circuit, respectively. And the copy is encoded differently. A multi-core semiconductor device having a plurality of cores,
Main memory;
A plurality of multi-cores that store some data among the data of the main memory and are respectively connected to one of the plurality of cores, and respectively provide the stored data to the connected cores based on a request signal received from the connected cores Cache circuits; And a consistency management circuit for maintaining the consistency of the data stored in the plurality of multi-core cache circuits. And
A processor including the plurality of cores and exchanging data with the main memory through the multi-core cache device;
Each of the plurality of multi-core cache circuits,
A cache memory unit including a plurality of cache lines and storing data, tag information, and state information of the cache lines;
A cache controller for a single core that provides a data request signal based on the request signal, and provides data of the cache memory unit corresponding to the data request signal to the connected core; And
A command for providing a state change signal for changing state information of some of the cache lines based on a change signal input from the consistency management circuit, and providing a portion of the data stored in the cache memory section to the consistency management circuit. Multi-core semiconductor device comprising a processing unit. In a multi-core semiconductor device having a plurality of cores, a method for controlling a cache memory including a plurality of cache lines using a cache controller for a single core,
Providing a data request signal based on a request signal received from a core in communication with the cache memory of the plurality of cores;
Providing data stored in the cache memory and corresponding to the data request signal to the core in communication with the cache memory;
Changing state information of some of the cache lines by providing a state change signal based on an externally input change signal; And
And providing some of the data stored in the cache memory to the outside. The method of claim 12, wherein the state information of the cache lines is encoded regardless of whether the data stored in the cache memory is shared.

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