KR101041938B1 - Method for fabricating capacitor - Google Patents

Abstract

The present invention is to provide a method for manufacturing a capacitor that can fundamentally prevent the upper loss of the storage node generated during the capacitor manufacturing process using a support, the capacitor manufacturing method of the present invention is an interlayer insulating film with a storage node contact plug embedded Forming an etch stop film on the substrate; Forming a first mold layer on the etch stop layer; Forming a support pattern on the first mold layer; Forming a second mold layer on the support pattern; Etching the second mold layer and the first mold layer so as to be aligned with an edge of the support pattern to form a plurality of open regions; Forming a cylinder type storage node having sidewalls supported by the support pattern in the open area; And removing the first and second mold layers, and the present invention as described above can prevent the top loss of the storage node by forming the support pattern before the open region. As a result, particles are not induced, collapses and breaks of the storage node do not occur, and capacitance (Cs) can be prevented from being lowered.

Capacitors, NFC, Supports, Deep Out, Storage Nodes

Description

Capacitor Manufacturing Method {METHOD FOR FABRICATING CAPACITOR}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly, to a capacitor manufacturing method.

As the size of the semiconductor memory device is required, the area occupied by the capacitor is decreasing due to the reduction of the cell size. However, a technology for securing a capacitor having a high capacity is required because a capacitor having a high capacity for driving the semiconductor device is required. Is being developed.

In order to obtain a capacitor having a high capacity, there is a method of increasing the surface area of a storage node or applying a dielectric film having a high dielectric constant. In the case of using a dielectric film having a high dielectric constant, there is a problem of stability and reliability with an existing process, and thus there is a limitation in application to a semiconductor process. Therefore, a method of increasing the surface area of a storage node is most preferable.

As described above, the capacitor for expanding the surface area of the storage node has a structure such as a stack, a concave type, a pin type, a cylinder type, and the like.

Recently, a capacitor having a structure in which a support is applied to a cylinder type capacitor has been developed, and it has emerged as a capacitor structure that maximizes the surface area of a storage node. The supporter is a stable structure that can prevent the storage node from falling down due to the surface tension generated by the subsequent dip out process.

A structure using a nitride film as a support is called an NFC (Nitride Floating Capacitor (NFC) capacitor) (hereinafter, referred to as an 'NFC capacitor').

As described above, the capacitor using the support increases the capacitance of the capacitor by increasing the vertical height of the capacitor, thereby increasing the capacitance of the capacitor, and the storage node is collapsed due to the surface tension generated by the subsequent dip out process. It is a stable structure that can prevent (leaning).

1A to 1E illustrate a method of manufacturing a capacitor according to the prior art.

As shown in FIG. 1A, a storage node contact plug 13 embedded in the interlayer insulating layer 12 is formed on the semiconductor substrate 11. After the etch stop layer 14 is formed on the storage node contact plug 13, the first mold layer 15 is formed on the etch stop layer 14. After the nitride film 16 is formed on the first mold film 15, the second mold film 17 is formed on the nitride film 16.

Subsequently, the storage node etching (SN ETCH) is performed to form an open region 18 exposing the surface of the storage node contact plug 13.

As illustrated in FIG. 1B, a conductive film is deposited on the entire surface of the open region 18 and then a storage node separation process is performed to form a storage node 19 having a cylindrical shape.

As shown in FIG. 1C, after forming the third mold layer 20 which blocks the inlet of the open region 18, the NFC mask 21 is formed.

As shown in FIG. 1D, the third mold film 20 is etched using the NFC mask 21 as an etch barrier, and the second mold film 17 and the nitride film 16 are subsequently etched. As a result, a nitride film support 16A capable of fixing the neighboring storage node 19 is formed.

As shown in FIG. 1E, all of the first mold layer 15 is removed through a wet dip out process. At this time, the remaining third mold film and the second mold film are also removed.

However, in the related art, due to the upper loss of the storage node (see reference numeral 'T' of FIG. 1D) accompanying the etching of the nitride layer 16, particles are not only induced during the subsequent deep-out process but also the storage node. It is caused to fall and break itself. In addition, the upper loss portion of the storage node is accompanied by a drop in capacitance (Cs).

Figure 2a is a photograph of the upper loss of the storage node according to the prior art, Figure 2b is a photograph of the collapse and break of the storage node.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems according to the prior art, and an object thereof is to provide a method for manufacturing a capacitor which can fundamentally prevent an upper loss of a storage node generated during a capacitor manufacturing process using a support. .

Capacitor manufacturing method of the present invention for achieving the above object comprises the steps of forming an etch stop film on the interlayer insulating film is embedded with the storage node contact plug; Forming a first mold layer on the etch stop layer; Forming a support pattern on the first mold layer; Forming a second mold layer on the support pattern; Etching the second mold layer and the first mold layer so as to be aligned with an edge of the support pattern to form a plurality of open regions; Forming a cylinder type storage node having sidewalls supported by the support pattern in the open area; And removing the first and second mold layers. The support pattern is characterized in that it comprises a nitride film.

The present invention described above can prevent the top loss of the storage node by forming the support pattern before the open area. As a result, particles are not induced, collapses and breaks of the storage node do not occur, and capacitance (Cs) can be prevented from being lowered.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3A to 3F are cross-sectional views illustrating a method of manufacturing a capacitor according to an embodiment of the present invention.

As shown in FIG. 3A, after forming the interlayer insulating layer 32 on the semiconductor substrate 31, a storage node contact hole penetrating the interlayer insulating layer 32 is formed. A storage node contact plug 33 embedded in the storage node contact hole is formed. Although not shown, a transistor and a bit line process including a word line are typically performed before the interlayer insulating layer 32 is formed. The interlayer insulating film 32 is formed of an oxide film. The storage node contact plug 33 is formed by depositing and etching back a polysilicon film or a metallic conductive film. Although not shown, a barrier metal may be formed on the storage node contact plug 33, and Ti or Ti / TiN may be used as the barrier metal.

Next, an etch stop layer 34 is formed on the interlayer insulating layer 32 in which the storage node contact plug 33 is embedded. Here, the etch stop layer 34 is for use as an etch stop layer during subsequent mold layer etching, and is formed of, for example, a silicon nitride layer (Si ₃ N ₄ ). Although not shown, a buffer oxide layer may be further formed on the etch stop layer 34.

Subsequently, a first mold layer 35 is formed on the etch stop layer 34. In this case, the first mold layer 35 is formed of an insulating film, and in particular, an oxide film is deposited to a thickness capable of securing an area required for a desired dielectric capacity. The first mold layer 35 may use an oxide film such as BPSG, SOD, PSG, LPTEOS, or PETEOS, and the thickness of the first mold layer 35 is 2000 to 20000 mm 3.

After the first mold layer 35 is formed, the planarization process may be performed using a chemical mechanical polishing (CMP) method, a dry etching method or a wet etching method, and thus a subsequent photo process may be easily performed. At this time, the amount removed by planarization may be 50 to 5000 kPa.

Subsequently, a nitride film 36 serving as a support is formed on the first mold layer 35. Here, the nitride layer 36 is a material for preventing the storage node from falling down during the subsequent wet deep-out process. The nitride film 36 is formed to a thickness of 50 to 3000 mm 3. The nitride film used as the support includes a silicon nitride film or a silicon oxynitride film (SiON). The material used as the support may include an amorphous carbon film.

In this case, when the material used for the support is the nitride film 36, the material becomes an NFC capacitor.

As shown in FIG. 3B, the nitride film 36 is etched through the NFC mask 37 and the etching to form the nitride film pattern 36A. In the NFC mask 37 process, i-line, KrF, ArF, or ArF (Immersion) may be used as an exposure source. When the nitride film 36 is etched, gases containing components such as C _x F _y , C _x F _y Cl _z , O ₂ , and O ₃ may be used alone or in combination.

The nitride film pattern 36A may have a structure located between subsequently formed open regions. Therefore, the nitride film pattern 36A is not etched during the etching process for forming the subsequent open region.

As shown in FIG. 3C, after the NFC mask is removed, the second mold layer 38 is formed on the first mold layer 35 including the nitride film pattern 36A. Here, the second mold layer 38 may include an oxide film such as TEOS, BPSG, PSG, USG, and HDP. The second mold layer 38 varies depending on the height for securing the capacitance of the capacitor, but may have a thickness of 100 to 15000 Å.

After the second mold layer 38 is formed, the surface may be planarized using a method such as CMP, dry etch bag, or wet etch bag to remove the step caused by the nitride film pattern.

As shown in FIG. 3D, the storage node is etched to form an open region 39 exposing the surface of the storage node contact plug 33. The storage node etching is performed by etching the second mold layer 38 and the first mold layer 35 using an SN mask (not shown) using a photoresist and then etching the etch stop layer 34. Here, before forming the SN mask, a hard mask film (not shown) such as an amorphous carbon or polysilicon film may be formed in advance, and an anti-reflective coating (not shown) may be formed on the hard mask film. The antireflection film includes a silicon oxynitride film (SiON).

When the open region 39 is formed, the nitride film pattern 36A is not etched. This is possible because the shape of the nitride film pattern 36A is adjusted in advance in consideration of the shape of the open area.

The above-described open area 39 is a hole shape in which a cylinder type storage node is to be formed, and is also called a storage node hole.

As shown in FIG. 3E, a conductive film to be used as a storage node is deposited on the entire surface including the open area 39. Thereafter, the storage node separation process is performed to form a cylinder-type storage node 40 in the open area.

The conductive film to be the storage node 40 includes any one of a metal nitride film, a metal film, or a material in which the metal nitride film and the metal film are combined. For example, it may include at least one selected from TiN, Ru, TaN, WN, Pt, or Ir. The conductive film is deposited by CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition) method, but is deposited to a thickness of 200 ~ 900Å. The storage node separation process uses a dry etchback or chemical mechanical polishing (CMP) process.

As shown in FIG. 3F, both the first and second mold layers 35 and 38 are removed. To this end, a wet deep-out process is performed. Since the first and second mold layers 35 and 38 are oxide films, the wet dipout process may use wet chemical such as hydrofluoric acid or BOE solution.

In the wet deep-out process as described above, the nitride layer pattern 36A is not etched and remains firmly fixed so that the storage node 40 does not fall. In addition, the wet chemical does not penetrate into the substructure by the etch stop layer 34, which is a nitride film. As described above, since the storage node 40 is suspended by the nitride film pattern 36A, it is referred to as an NFC capacitor.

In the wet deep-out process, a chemical having a high selectivity to the oxide layer is used to remove only the first and second mold layers 35 and 38 which are oxide layers and minimize the loss of the nitride layer pattern 36A.

In addition, notch alignment may be performed to minimize the lining and the breakage of the storage node before the deep-out process.

Selectively in-situ the organic material removal chemical and the oxide film removal chemical to suppress the generation of defects generated during the dip-out process of removing the first and second mold layers 35 and 38. Situ or Ex-Situ can be used.

4A and 4B are planar photographs of a nitride film pattern according to an embodiment of the present invention, in which the nitride film pattern 36A is in the form of a hole simultaneously supporting at least four neighboring storage nodes 40 (see FIG. 4A), or It may be a bar open type having a bar that opens all the sidewalls of the plurality of storage nodes 40 while opening between some storage nodes.

According to the above-described embodiment, since the nitride film pattern serving as the support is formed before the open area, the upper loss of the storage node can be prevented. Accordingly, particles are not induced, falling and breaking of the storage node does not occur, and capacitance (Cs) can be prevented from being lowered.

In addition, since the process of depositing the third mold layer, which is conventionally required, is not necessary, there is an effect of simplifying the process.

In addition, since the NFC mask proceeds after deposition of the planarized nitride film as compared with the conventional NFC mask after the third mold layer deposition, the stability of the mask process is also excellent.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

1A to 1E illustrate a method of manufacturing a semiconductor device having an NFC capacitor according to the prior art.

Figure 2a is a photograph of the upper loss of the storage node according to the prior art.

Figure 2b is a photograph taken the collapse and break of the storage node.

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

4A and 4B are planar photographs of a nitride film pattern according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31 semiconductor substrate 32 interlayer insulating film

33: storage node contact plug 34: etch stop

35: first mold layer 36A: nitride film pattern

37: NFC mask 38: the second mold layer

39: open area 40: storage node

Claims (13)

Forming an etch stop layer on the interlayer dielectric layer having the storage node contact plug embedded therein; Forming a first mold layer on the etch stop layer; Forming a support pattern on the first mold layer; Forming a second mold layer on the support pattern; Etching the second mold layer and the first mold layer so as to be aligned with an edge of the support pattern to form a plurality of open regions; Forming a cylinder type storage node having sidewalls supported by the support pattern in the open area; And Removing the first and second mold layers Capacitor manufacturing method comprising a. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, Forming the support pattern, Forming an insulating film to be used as the support pattern on the first mold layer; And Etching the insulating layer using a support pattern mask Capacitor manufacturing method comprising a. Claim 3 was abandoned when the setup registration fee was paid. The method according to claim 1 or 2, The support pattern is a capacitor manufacturing method comprising a nitride film. Claim 4 was abandoned when the registration fee was paid. The method of claim 3, The nitride film includes a silicon nitride film or a silicon oxynitride film (SiON). Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1, The support pattern is a capacitor manufacturing method having a thickness of 50 ~ 3000Å. Claim 6 was abandoned when the registration fee was paid. The method of claim 1, The support pattern is a capacitor manufacturing method of the hole shape for supporting at least four neighboring storage nodes at the same time. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 1, Claim 8 was abandoned when the registration fee was paid. The method of claim 1, The second mold layer is formed by depositing an oxide film and planarization method. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 1, The first and second mold layers include an oxide film, and the support pattern includes a nitride film. Claim 10 was abandoned upon payment of a setup registration fee. 10. The method of claim 9, Removing the first and second mold layer is a capacitor manufacturing method applying a wet deep out. delete Claim 12 was abandoned upon payment of a registration fee. The method of claim 10, Before the wet deep out, the notch alignment is performed capacitor manufacturing method. Claim 13 was abandoned upon payment of a registration fee. The method of claim 10, The method of manufacturing a capacitor using the organic material removal chemical and the oxide film removal chemical in-situ or exsitu during the wet deep out.

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