KR101041567B1 - MAC controller for fast ethernet - Google Patents

Abstract

A MAC controller for fast Ethernet processing is disclosed. In a media access control (MAC) controller in which a media independent interface (MII) is adopted in an Ethernet transmission structure of more than 40 gigabytes, the reconciliation sublayer (RS) included in the MAC controller is a preamble. Preamble generation unit for generating a; And a downlink data matching processor for adding the generated preamble to the data frame received from the layer, generating a control signal according to the MII standard from the data frame, and reconstructing the data frame according to the MII standard. This enables high speed processing of Ethernet frames between RS and MAC.

Description

MAC controller for fast ethernet processing

TECHNICAL FIELD The present invention relates to an Ethernet passive optical network, and more particularly, to a media access control (MAC) sublayer and a reception sublayer (RS) in an Ethernet transmission structure.

This study is derived from the research conducted as part of the IT source technology development project of the Ministry of Knowledge Economy and the Ministry of Information and Telecommunication Research and Development. [Task Management No .: 2008-F-017-01, Development of 100Gbps Ethernet and Optical Transmission Technology]

For high speed Ethernet processing in the Ethernet transport structure, 40 Gigabit Media Independent Interface (XLGMII) and 100 Gigabit Media Independent Interface (CGMII) are standardized as interfaces between the Reconciliation Sublayer (RS) and the Physical Coding Sublayer (PCS). Therefore, it is not easy to present a special structure for the component device. However, the upper components RS and MAC require a new configuration scheme for processing high-speed Ethernet frames compared to the processing capabilities of existing field programmable gate arrays (FPGAs) and application specific integrated circuits (ASICs).

For the high-speed processing of Ethernet frames between RS and MAC, we propose a technical scheme that can process 8-bit data, which is the standard of Ethernet frame processing, as 128-bit or 256-bit, and propose processing techniques for the components.

In order to achieve the above-described technical problem, a media access control (MAC) controller implemented with a media independent interface (MII) adopted in an Ethernet transport structure of more than 40 gigabytes according to an aspect of the present invention. The RS included in the MAC controller may include: a preamble generator configured to generate a preamble; And a downlink data matching processor that adds the generated preamble to a data frame received from an upper layer, generates a control signal according to the MII standard from the data frame, and reconstructs the data frame according to the MII standard.

MII according to an aspect of the present invention is 40 Gigabit Media Independent Interface (XLGMII) or 100 Gigabit Media Independent Interface (CGMII).

According to an aspect of the present invention, when the MAC clock is 312.5 MHz and the data width is 128 bits, the data frame is converted into 8 bits using a 16-bit data byte enable signal to generate a control signal, Reconstruct the data frame to 64-bit.

According to an aspect of the present invention, when the MAC clock is 156.25 MHz and the data width is 256 bits, the downlink data matching processor generates a control signal by converting the data frame into 8 bits using a 32-bit data byte enable signal, Reconstruct the data frame to 64-bit.

In designing MAC sublayer and RS in 40GE or 100GE system, which is a fast Ethernet system, designing with FPGA or ASIC according to the specification of XLGMII or CGMII given as the interface between RS and PCS is not easy due to the limitation of operating frequency. It is possible to provide a system configuration device of 40GE and 100GE that can be manufactured by suggesting a method of processing 16-32 data frames composed of 8 lanes.

The foregoing and further aspects of the present invention will become more apparent through the preferred embodiments described with reference to the accompanying drawings. Hereinafter, the present invention will be described in detail to enable those skilled in the art to easily understand and reproduce the present invention.

1 is a general hierarchical structure diagram of 40GE / 100GE.

The location of MAC sublayer and RS processing unit is located between MAC Control and PCS in a typical 40GE or 100GE structure.

2 is an XL / CGMII structure diagram defined in IEEE802.3ba.

This part corresponds to the input / output of RS. Below the RS, it is connected to the PCS. The interface specification between RS and PCS is XLGMII for 40GE and CGMII for 100GE. The standard consists of 8 bits for TXC and 64 bits for TXD, whereas the conventional XGMII signals used for 10 Gigabit Ethernet systems consisted of 4 bits for TXC and 32 bits for TXD. Similarly, RXC and RXD have the same bit configuration. In this case, detailed configuration descriptions of TXD and TXC are given in the IEEE802.3ba standard as shown in Table 1 below.

3 is a diagram illustrating a normal input of an XL / CGMII transmitter defined in IEEE802.3ba.

The frame is input according to the TXC and TXD formats given in [Table 1]. When 8 bits are regarded as one lane for the TXD, all eight lanes are configured. Among them, the condition that the Start Control Character can come only in TXD <7: 0> corresponding to the first lane is defined to facilitate lane alignment. In the case of RXC and RXD as receiving terminals, the same bit configuration is processed. The considerations here are 625MHz for 40GE and 1.5625GHz for 100GE for clock TX_CLK and RX_CLK of the transceiver. In the case of RX_CLK at the receiving end, the same frequency clock is used at 40GE / 100GE.

4 is an internal block diagram of a MAS / RS in a 40G / 100G Ethernet system according to an embodiment of the present invention.

As shown, it is divided into RS 200 and MAC Sublayer 300. First, a block corresponding to the RS 200 will be described. The preamble generator 210 is used only when a preamble having a specific purpose is required, such as in an EPIN system. In one embodiment, the preamble generator 210 generates an 8-byte preamble including a Logical Link ID (LLID) field. In one embodiment, the preamble generator 210 calculates and attaches an 8-bit CRC (CRC-8) to a position corresponding to an end of 8 bytes. As an example, the preamble generator 210 calculates CRC-8 using x8 + x4 + x2 + x1 as a CRC polynomial equation. If the preambles are always the same, the CRC-8 may be calculated in advance.

The downlink data matching processor 220 inserts the 8-byte preamble generated by the preamble generator 210 before the data frame received from the MAC sublayer 300. The TXC signal, which is a standard of XL / CMGII for the entire frame, is generated and transmitted to the PCS 500. In this case, if 128 or 256 bits are used instead of the same 64-bit data format as XL / CGMII, the TXD and TXC conforming to the standard should be converted. A solution for this is shown in FIG. 5. When 128-bit data is received, it should be converted into TXC 8-bit using 16 bits corresponding to DATA_BE, and reconfigured to 64-bit corresponding to TXD for 128-bit data. Likewise, when 256-bit data is received, the 32-bit data corresponding to DATA_BE should be converted into TXC 8-bit and the 256-bit data should be reconfigured to 64-bit corresponding to TXD.

The uplink data matching processor 230 performs data conversion for sending the RXD and RXC input from the PCS 500 to the MAC sublayer 300. If the data width is 64 bits, RXD goes up to the upper layer. In addition, the RXC may be converted into DATA_EN (Data Enable) and DATA_BE (Data Byte Enable) signals as shown in FIG. It may take the form of a bitwise reverse. For example, '1' is displayed only for normal data and '0' for no data. When the data required by the MAC sublayer 300 is 128 bits or 256 bits, the upstream data matching processor 230 may generate and send DATA_BE and DATA_EN as shown in FIG. 5.

The RS receiver 240 removes the first 8 bytes of data corresponding to the preamble among the received frames. This is to transmit a received frame to the MAC sublayer (300). And if the value of the preamble changes like the EPON system, the error check for CRC-8 should be performed. If a CRC error occurs, the frame can be deleted immediately.

The RS data controller 250 may generate a control signal and a PMA loopback control signal related to generation of a test frame for a test of a physical layer through a control register that is read / write by the CPU 400. Provides necessary control functions.

Next, a block corresponding to the MAC sublayer 300 will be described. The FCS / Length error checker 310 is a block for detecting an Ethernet frame received from a lower layer when it is damaged during the reception process. In one embodiment, the FCS / Length error check unit 310 performs an error check using the CRC-32 from the DA field of the received frame to the last FCS field. The polynomial using CRC-32 is equivalent to [X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1].

In the checking process, if the CRC shift register is initialized to '1' before processing the first data byte and the calculation is performed for both Data and FCS, the remaining value is equal to “C704DD7B”. In this case, it is determined that the result of the received frame has been received without damage. If there is an FCS error, the contents to be output after being written to the RX FIFO unit 320 are discarded unconditionally, and the discarded state is stored in the reception MIB counter 330. At the same time, it also checks the Ethernet frame length.The Ethernet frame that needs to be received is at least 64 bytes up to 1518 bytes (up to 24 bytes can be added if a frame such as encryption is included, and the maximum bytes can be adjusted by the CPU). The standard is set as), and frames that deviate between the values are determined as an error and the error state is stored in the corresponding MIB counter.

The RX FIFO unit 320 secures the memory as much as the maximum allowable byte in preparation for determining the FCS error, and stores a new frame therein. And when CRC error results, it provides the function to make the final decision on whether to upload the corresponding frame or discard it.

The reception MIB counter 330 is responsible for collecting and placing error information checked by the FCS / Length error checker 310. The total number of frames and the number of bytes passing through the received data are counted. The CPU 400 may periodically check the system status by collecting corresponding data from the reception MIB counter 330.

Since the FCS generation processing unit 340 may not attach the FCS when the Ethernet frame received from the upper layer is a Control message in the upper MAC Control function unit, the FCS generation processing unit 340 is configured for the processing thereof. In the case of data of a control frame without an FCS, the FCS generation processor 340 generates a 32-bit FCS value and adds it to the received control frame. In one embodiment, the FCS generation processor 340 generates the FCS value using the CRC-32. The CRC-32 polynomial may be the same as that given in the FCS / Length error checker 310. The verification process initializes all CRC shift registers to '1' before processing the first data byte. After the FCS value generated by this process is processed to the last data byte, the process of adding 4 bytes is performed.

The transmission MIB counter 350 counts and accumulates the total number of frames and the number of bytes passing for the transmission data to be transmitted from the upper level to the lower level. The CPU 400 may periodically collect corresponding data from the transmission MIB counter 350 to check the status of the system.

The MAC data controller 360 maintains a Control / Status register for read / write operations by the CPU 400 and provides status reporting and control functions for key functions including whether the CPU check function and the length check function are applied. do.

5 illustrates an example of MAC / RS internal data processing for Fast Ethernet processing according to an embodiment of the present invention.

The configuration of the Ethernet frame transmitted and received from the PCS 500 is shown in FIG. 2 as XL / CGMI. When used in an internal block such as MAC and RS, there is a need for lowering the internal system clock due to the limitation of the operating frequency. At this time, if MAC_CK is the same as TL_CLK and RX_CLK depending on the clock state, it is used as it is. When MAC_CK is two divisions of TL_CLK and RX_CLK, 128 bits of internal data should be used, and 16 bits of DATA_BE should be used to determine whether data is present. When MAC_CK is the 4th division of TL_CLK and RX_CLK, 256 bits of internal data should be used, and 16 bits of DATA_BE should be used to determine the presence or absence of data.

So far I looked at the center of the preferred embodiment for the present invention. Those skilled in the art will appreciate that the present invention can be implemented in a modified form without departing from the essential features of the present invention. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is shown in the claims rather than the foregoing description, and all differences within the scope will be construed as being included in the present invention.

1 is a general hierarchical view of 40GE / 100GE.

2 is an XL / CGMII structure diagram defined in IEEE802.3ba.

3 is a diagram illustrating normal input of an XL / CGMII transmitter defined in IEEE802.3ba.

4 is an internal block diagram of a MAS / RS in a 40G / 100G Ethernet system in accordance with an embodiment of the present invention.

5 illustrates an example of MAC / RS internal data processing for Fast Ethernet processing according to an embodiment of the present invention.

Claims (8)

delete In a media access control (MAC) controller in which a media independent interface (MII) is implemented, a reconciliation sublayer (RS) included in the MAC controller is: A preamble generating unit generating a preamble; And a downlink data matching processor configured to add the generated preamble to a data frame received from an upper layer, generate a control signal according to the MII standard from the data frame, and reconstruct the data frame according to the MII standard. The MII is a 40 Gigabit Media Independent Interface (XLGMII) or 100 Gigabit Media Independent Interface (CGMII) MAC controller. The method of claim 2, When the MAC clock is 312.5 MHz and the data width is 128 bits, the downlink data matching processor generates a control signal by converting the data frame into 8 bits using a 16-bit data byte enable signal, and converts the data frame into 64 bits. MAC controller, characterized in that reconstruction with bits. The method of claim 2, The downlink data matching processor generates a control signal by converting the data frame into 8 bits using a 32-bit data byte enable signal when the MAC clock is 156.25 MHz and the data width is 256 bits, and converts the data frame to 64 bits. MAC controller, characterized in that reconstruction with bits. The method of claim 2, An upstream data matching processor for receiving a data frame and a control signal from a lower layer and converting the control signal into a data enable signal and a data byte enable signal to process the data frame according to the number of data bits required by the upper layer ; And An RS receiver for outputting a data frame, a data enable signal, and a data byte enable signal output from the uplink data matching processor to the upper layer; The MAC controller further comprises. The method of claim 5, The MII is characterized in that the XLGMII or CGMII MAC controller. The method of claim 6, The uplink data matching processor generates a 16-bit data byte enable signal when the MAC clock is 312.5 MHz and the data width is 128 bits. The method of claim 6, The uplink data matching processor generates a 32-bit data byte enable signal when the MAC clock is 156.25 MHz and the data width is 256 bits.

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