KR101040264B1 - Ethernet-based ad-hoc network verification system and verification method thereof - Google Patents

Abstract

PURPOSE: A system and method for verifying an ad hoc network based on Ethernet is provided to previously verify software of an ad hoc network even in a point where development of hardware is not completed. CONSTITUTION: A network stack(10) includes an interface module(10e) and an IP processing module(10g). The network stack drives a communication unit(40) using an ad hoc network. The control unit(20) realizes physical layer influencing a network among a physical layer of the communication unit to a imitation physical layer module(10f) through an Ethernet. The control unit simulates driving of the communication unit.

Description

Ethernet-based ad hoc network verification system and verification method {ETHERNET-BASED AD-HOC NETWORK VERIFICATION SYSTEM AND VERIFICATION METHOD THEREOF}

The present invention relates to an Ethernet-based ad hoc network verification system and a verification method thereof. More specifically, the present invention relates to an Ethernet-based ad hoc network verification system for verifying the performance of actual software code before the development of hardware of a network system and a verification method thereof.

Ad-hoc network system is characterized by autonomous wireless communication between nodes without an infrastructure (Infra-Structure), such as an access point (Access Point). To this end, the ad hoc network system has a protocol that operates in each layer, and each layer in which the protocol operates includes the physical layer, the MAC layer, the network layer, the transport layer, the application layer, and the wired routing method. In a number of ad hoc networks, it is divided into ad hoc routing modules that update the route table of the network layer by a routing method reflecting the ad hoc network characteristics.

The application layer is the highest application layer, and the lower layer of the application layer is a transport layer in which the Transmission Control Protocol (TCP) or the User Datagram Protocol (UDP) operates, and the ad hoc routing module is supported. A network layer that provides a functional and procedural means for determining a transmission path and providing a quality of service (QoS) required by the transport layer, and a medium access control (MAC) sublayer that controls access to each medium. A data link layer including a data layer, a physical layer that receives a packet output from the MAC layer or outputs a packet received through an RF / antenna, etc. to the MAC layer, and transmits and receives a periodic routing control message in advance to pre-optimize an optimal path. Route request (RREQ) message transmission and route at the time of pre-routing or data transmission Routing Reply (RREP) can be classified into an ad hoc routing module that updates the routing table of the network layer by a method of determining the routing of a message (Reactive Routing).

Meanwhile, in order to develop an ad hoc network system, an application layer, an ad hoc routing module, a data link layer (MAC layer), and a physical layer except for a transport layer and a network layer compliant with standards are required to be implemented and verified in advance. Do.

Typically, this verification is done using network M & S (Modeling & Simulation) tools. By the way, verification work based on network M & S can verify the network algorithm itself, but it is not easy to test reflecting the characteristics of hardware.

Therefore, it is difficult to conduct high fidelity tests on the implemented software before the development of the hardware is completed, resulting in a long integration time between the hardware and the software, and consequently, the development time of ad hoc network software and the cost of developing it. There is.

Accordingly, the present invention provides an Ethernet-based ad hoc network verification system and a method of verifying the ad hoc network which can be pre-verified even when hardware development is not completed, thereby reducing development time and reducing development costs. It aims to do it.

In addition, an object of the present invention is to provide an Ethernet-based ad hoc network verification system and a verification method thereof, which can easily grasp in advance the characteristics of hardware affecting the network by implementing a simulation physical layer through Ethernet.

In addition, an object of the present invention is to provide an Ethernet-based ad hoc network verification system and its verification method that can improve the accuracy of the verification process by simulating various functions in the simulation physical layer.

The object is a network stack for driving a communication unit using an ad hoc network; Among the lower modules of the network stack, the lower module operating regardless of the type of the communication unit and the physical layer elements affecting the network among the physical layers of the communication unit are implemented as simulated physical layer modules through Ethernet to drive the communication unit. It is achieved by an Ethernet-based ad hoc network verification system, characterized in that it comprises a control unit for simulating.

The simulation physical layer module may simulate at least one of a transmission processing time delay and a reception processing time delay simulation function, a report simulation function of channel usage, and a BER quality simulation function of an actually designed physical layer under the control of the controller. Can be.

The lower module may include an interface commonly used in the communication unit, and an interface module configured to determine whether to transfer a data link frame to the simulated physical layer module or the actual physical layer at the completion of the implementation; In the transmission of data, an IP header is added to a frame generated in the network stack, and in the added IP header, the data of the data to be transmitted is reflected to reflect a characteristic of wireless communication in which all nodes within one hop communication distance receive packets. IP processing module for setting the destination IP address may be included.

The control unit may be configured to delete the data so that a node located within a predetermined communication communication distance from a source node transmitting the data and whose node does not match the destination IP address among the nodes receiving the data is deleted. You can control the node.

The control unit, via the intermediate node is located within a predetermined communication communication distance from the source node and stored routing information to transmit the data to a destination node located outside the predetermined distance from the transmitting node for transmitting the data. Control each node to transmit the data.

On the other hand, receiving a datalink frame; Transmitting the data link frame to a simulated physical layer module; Generating an IP header in an IP processing module and generating a new IP datagram by adding to the data link frame; Delivering the generated IP datagram to an Ethernet device via an IP stack; And the simulation physical layer module transmits the IP datagram to the IP processing module after a delay time as long as the time reflecting the physical layer transmission processing delay time of the designed communication unit is passed to the IP processing module. The above object is also achieved.

The IP processing module receiving the processed IP datagram from the IP stack; Parsing, by the IP processing module, an IP header of the received IP datagram; Checking, by the IP processing module, whether the IP address included in the IP datagram is a broadcast address; Removing the IP header when the verification result matches the IP address; Transmitting the data link frame from which the IP header has been removed to the simulated physical layer module; And transmitting, by the simulation physical layer module, the data link frame to the interface module after a delay time as long as the reception processing time has elapsed.

In addition, the IP processing module receiving the processed IP datagram from the IP stack; Parsing, by the IP processing module, an IP header of the received IP datagram; Checking, by the IP processing module, whether the IP address included in the IP datagram is a broadcast address; Removing the IP header when the verification result matches the IP address; Transmitting the data link frame from which the IP header has been removed to the simulated physical layer module; And the above object is achieved by the Ethernet-based ad hoc network verification method, characterized in that the simulated physical layer module includes transmitting the data link frame to the interface module after a delay time as long as the reception processing time.

When the physical layer frame is composed of a preamble and a data slot, the simulated physical layer module delays the preamble reception processing delay time in the physical layer frame to the interface module, and then reports to the upper layer that the channel is in use. Making; And transmitting a data link frame to an interface module after delaying the physical layer data slot reception processing time of the actual physical layer, and reporting that the channel is not in use.

According to the Ethernet-based ad hoc network verification system and the verification method according to the present invention, it is possible to pre-verify the software of the ad hoc network even when the development of hardware is not completed, thereby shortening the development period and reducing the development cost.

In addition, according to the Ethernet-based ad hoc network verification system and the verification method according to the present invention, it is possible to easily determine the characteristics of the hardware affecting the network in advance by implementing a simulation physical layer through Ethernet.

In addition, according to the Ethernet-based ad hoc network verification system and the verification method according to the present invention, it is possible to increase the accuracy of the verification process by simulating various functions in the simulation physical layer.

1 is a block diagram showing the configuration of an Ethernet-based ad hoc network verification system according to the present invention,
2 is a diagram illustrating a process of transmitting data in an actual wireless environment.
3 is a view showing the structure of a packet processed by the IP processing module according to the present invention,
FIG. 4 is a diagram illustrating a process of transmitting a packet to a destination node through a intermediate node, which is within two hop distances in an actual wireless network environment.
5 is a flowchart illustrating a packet transmission process of an interface module, a simulated physical layer module, and an IP processing module in an Ethernet-based ad hoc network verification system according to the present invention.
6 is a flowchart illustrating a packet reception process of an interface module, a simulated physical layer module, and an IP processing module in an Ethernet-based ad hoc network verification system according to the present invention.

Hereinafter, an Ethernet-based ad hoc network verification system and a verification method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing the configuration of an Ethernet-based ad hoc network verification system according to the present invention. As shown in FIG. 1, the Ethernet-based ad hoc network verification system according to the present invention includes a network stack 10, a control unit 20, and an Ethernet device 30, and includes a user in a non-simulation mode and a simulation mode. According to the selection of the communication unit 40 may be selectively included.

The network stack 10 drives the IP stack 10a, the ad hoc routing module 10b, the Ethernet driver 10c including the routing processing unit, and the communication unit 40 using the ad hoc network, such as the network driver 10d. It includes a known submodule that performs each function.

Here, the Ethernet-based ad hoc network verification system according to the present invention includes an interface module 10e, a simulated physical layer module 10f, and an IP processing module 10g.

The interface module 10e includes an interface commonly used for the communication unit 40.

In addition, the simulated physical module layer 10f simulates the physical layer affecting the network among the physical layers of the communication unit 40 through the Ethernet.

The IP processing module 10g adds an IP header to the frame generated by the driver 10 at the time of data transmission, and sets a destination IP address of the data to be transmitted in the added IP header.

The control unit 20 simulates the operation of the communication unit 40 through the simulated physical layer module 10f, packet transmission success rate, packet transmission delay, ad hoc routing performance, overhead, packet transmission quality, and MAC performance. At least one of can be measured. The control unit 20 according to the present invention should be able to perform not only an application but also a function of firmware including hardware information such as a kernel of an operating system. Thus, before the development of a communication unit such as a modem or an RF / antenna, which is hardware, the pre-verification of network software is possible even before the communication unit 40 is actually integrated into the system.

Hereinafter, a process of transmitting data in an actual wireless environment and a process of transmitting data by the simulated physical layer module 10f according to the present invention will be described with reference to FIG. 2.

2 is a diagram illustrating a process of transmitting data in an actual wireless environment. As shown in FIG. 2, in a real wireless environment, nodes within one hop from the source node SN receive data first, and the destination node RN receives the datalink header and IP in the transmitted packet. If the destination address in the header matches its own address, the packet is finally received. If the destination header in the DL header and the IP address in the packet is different from the address, the packet is deleted.

This data transmission process is performed as follows in the Ethernet-based ad hoc network verification system according to the present invention.

When data belonging to a node belonging to an ad hoc network network is generated from the application layer and requests transmission to the network stack 10 (typically by a socket), the packet is packetized through the transport layer and the network (IP) layer. At the IP layer, the packet is forwarded to the ad hoc network driver by referencing the routing table. The ad hoc network layer in the ad hoc network driver generates a datalink frame, the sublayer MAC first checks if the channel is in use, waits for a randomly determined back-off time if the channel is not in use, and then forwards the packet to the lower layer. It is usually delivered to the physical layer.

In an Ethernet-based ad hoc network verification system aimed at verifying ad hoc network software when the physical layer is not implemented, an interface module (waiting to receive a data link frame generated at an ad hoc data link layer (ad hoc network driver)) 10e). The interface module 10e determines whether to deliver to the simulated physical layer module 10f or to the actual physical layer when the implementation is completed under the control of the controller 20, and may be implemented in an ad hoc network driver.

When the interface module 10e receives the datalink frame from the ad hoc datalink layer, the packet is delivered to the simulated physical layer module 10f set by the controller 20.

Next, the simulation physical layer module 10f delays the time by the difference between the transmission transmission time of the Ethernet and the transmission processing time of the simulation physical layer module 10f, and then delivers the packet to the IP processing module 10g. After delivery, the packet complete message is transmitted to the upper module.

The IP processing module 10g receives the ad hoc data link packet from the simulated physical layer module 10f, adds an IP header to the received packet, generates the packet, and transmits the packet to the transport module of the generated IP layer. At this time, the source IP address of the IP header is set to the IP of the Ethernet network, and the IP address of the destination is set to the broadcast address of the Ethernet network to reflect the characteristics of wireless communication in which all nodes within one hop distance are receiving packets. do.

Next, the IP stack 10a transmits the packet generated by the IP processing module 10g in the same manner as the packet transmitted from the IP upper layer. Then, the Ethernet header and the trailer are added normally to generate an Ethernet frame, which is transmitted to the Ethernet network device and transmitted.

At this time, since the destination IP address is a broadcast address, the destination Ethernet MAC address is also set as the broadcast address.

Meanwhile, the network stack 10 at the destination node RN performs the following operation.

First, since the destination Ethernet MAC address is a broadcast address, the destination node RN receives the packet and delivers it to the IP stack 10a.

The IP stack 10a checks the simulated IP header presence field (using the reserved field of the IP header) in the IP header of the received IP datagram. As a result of the inspection, in the case of the IP processing header, the IP processing datagram is transmitted to the IP processing module 10g without removing the IP processing header. (If the packet is not the simulated IP header, the IP stack 10a processes normally. ). After receiving the packet (the ad hoc network simulation packet) from the IP stack 10a, the IP processing module 10g returns the received IP packet to its original state when the destination address of the IP processing header is the broadcast address of the ad hoc network. After the release, transfer to the simulated physical layer module (10f).

When receiving the packet from the IP processing module 10g, the simulated physical layer module 10f reports whether the channel is in use (CCA; Clear Channel Assessment) and the packet reception processing time delay and the Bit Error Rate (BER). It reflects the quality simulation. That is, when receiving the packet, the simulated physical layer module 10f first delays the preamble reception processing time in the actually designed physical layer frame, and then reports to the upper layer that the channel is in use. The interface module 10e delivers the report received from the simulated physical layer module 10f to the ad hoc network driver. Here, the report transmitted to the ad hoc network driver is used as information for avoiding a data transmission collision in the MAC sublayer in the ad hoc data link layer.

Thereafter, the network is delayed by the reception processing time of the data slot in the physical layer frame, and then the packet is delivered to the interface module 10e. At this time, for more accurate delay, delay the data reception processing delay time of the actually designed physical layer module by the difference between the reception processing time of Ethernet. Thereafter, while delaying the reception time of the data slot, an error is generated in an arbitrary bit for the entire received packet based on the BER of the designed communication unit 40, and then the packet is delivered to the interface module 10e. As an example of generating an error, when BER is 10 ⁻⁵ , a 1 bit error is generated at a random bit position within a 100000 bit unit.

Next, the interface module 10e delivers the packet received from the simulated physical layer module 10f to the network driver 10d.

Thus, the ad hoc network data link header in the network driver 10d is parsed and forwarded to the IP layer, which is a higher layer because the destination data link address of the header matches its own address.

Meanwhile, the network stack 10 at the node TN other than the destination node performs the following operation.

First, the node TN, not the destination node, receives a packet and transmits the packet to the IP stack 10a since the destination Ethernet MAC address is a broadcast address.

Like the destination node RN, the IP stack 10a checks the IP header status field (using the reserved field of the IP header) in the IP header of the received packet. In the case of the inspection result of the IP processing header, the packet is transmitted to the IP processing module 10g without removing the IP processing header. Here, if the packet is not the simulated IP header, the IP stack 10a processes normally. After receiving the packet (the ad hoc network simulation packet) from the IP stack 10a, the IP processing module 10g returns the received IP packet to its original state when the destination address of the IP processing header is the broadcast address of the ad hoc network. After the release, transfer to the simulated physical layer module (10f).

And, when receiving the packet from the IP processing module 10g, the simulated physical layer module 10f reports whether the channel is in use (Clear Channel Assessment), the packet reception processing time delay, and the quality based on the Bit Error Rate (BER). To reflect the simulation. That is, when receiving the packet, the simulation physical layer module 10f first delays the preamble reception processing time in the actually designed physical layer frame, and then reports to the upper layer that the channel is in use. The interface module 10e delivers the report received from the simulated physical layer module 10f to the ad hoc network driver. Here, the report transmitted to the ad hoc network driver is used as information for avoiding a data transmission collision with another node in the MAC sublayer in the ad hoc data link layer.

Thereafter, the network is delayed by the reception processing time of the data slot in the physical layer frame, and then the packet is delivered to the interface module 10e. At this time, for more accurate delay, delay the data reception processing delay time of the actually designed physical layer module by the difference between the reception processing time of Ethernet. While delaying the data slot by the reception processing time, an error occurs in an arbitrary bit for the entire received packet based on the BER of the physical layer, and then the packet is delivered to the interface module 10e.

Next, the interface module 10e transfers the packet received from the simulated physical layer module 10f to the network driver 10d.

Finally, the network driver 10d parses the header for the received ad hoc network data link frame, and discards the packet without forwarding it to the IP layer, which is higher because the header destination data link address does not match its own address. .

3 is a diagram illustrating a structure of a packet processed by the IP processing module 10g according to the present invention. The DL header (DH) contains the destination's DL address, the IP header (IH) contains the destination's IP address, and the Ethernet header (EH) contains the destination's Ethernet broadcast DL address.

FIG. 4 is a diagram illustrating a process of transmitting a packet to a destination node RN via a middle node MN, which is within two hop distances in an actual wireless network environment. Here, when the intermediate node MN receives the packet from the source node SN, the intermediate node MN transmits the packet to the destination node RN using routing information.

In the Ethernet-based ad hoc network verification system according to the present invention, in the data transmission process of FIG. 4, the intermediate node MN receives the IP processing module 10g via the Ethernet driver as described above. ), The IP processing header field check in the IP header in the IP stack 10a, the physical layer module 10f, the interface module 10e, and the network driver 10d are delivered to the IP stack 10a. Since the destination IP address is not its own address, the IP stack 10a retrieves the routing information collected by the ad hoc routing module 10b for relay transmission, and transmits the routing information to the destination node RN according to the routing information. Here, the transmission method is the same as that of the transmission destination node SN. It is also impossible for a packet to be sent directly from a source node SN to a destination node RN.

5 is a flowchart illustrating a packet transmission process of the interface module 10e, the simulated physical layer module 10f, and the IP processing module 10g in the Ethernet-based ad hoc network verification system according to the present invention.

First, the interface module 10e waits for reception of a data link frame from the network driver 10d (S501).

When the data link frame is received in step S501, the interface setting is checked (S502).

When the non-simulation mode in which the actual hardware operates is set by checking the interface setting in step S502, the step S504 is performed. When the simulation mode in which the simulation physical layer module 10g is executed is set in step S507 (S503). ).

In the non-simulation mode, the data link frame is transmitted to the physical layer module in the communication unit 40 (S504).

In step S504, the physical layer module receives the data link frame, generates the physical layer frame, transmits data wirelessly through the communication unit 40, and then informs that the data transmission is completed to the interface module 10e (S505). .

The interface module 10e receives the message sent in step S505 (S506).

When the simulation physical layer module 10e is executed before the development of the communication unit 40, which is actual hardware, is completed, the data is transmitted to the simulation physical layer module 10e (S507).

The simulated physical layer module 10e transmits the received data link frame to the IP processing module 10f (S508).

Next, the IP processing module 10g generates an IP processing header, assigns a source IP address in the IP header to its Ethernet IP address, assigns a destination IP address to its Ethernet broadcast address, and IP processing header. The reserved field in the header is used to set an IP header. (S509).

The IP processing module 10g generates a new IP processing datagram by combining the IP processing header generated in step S509 with the received data link frame (S510).

Next, the IP processing datagram generated in step S510 is transferred to the IP stack 10a (S511). Here, it is delivered back to the Ethernet device 30 by the forwarding function of the IP stack 10a. At this time, the routing table is set directly or the reserved field in the IP header is checked and forwarded to the Ethernet device driver 10c for forwarding.

The IP processing module 10g notifies that the transmission of the IP datagram is completed to the simulated physical layer module 10f (S512).

After receiving the completion of the transmission in step S512, the simulation physical layer module 10f reports the completion of transmission to the interface module (S513).

The interface module 10e receives that transmission is completed from the simulation physical layer module 10f (S514).

The interface module 10e receives that the transmission is completed from step S506 or step S514, and notifies the network driver 10d of the upper module that the transmission is completed (S515).

Here, the control unit 20 according to the present invention may further perform a function of measuring the success rate of transmission to the actual physical layer.

Hereinafter, a data transmission process in the IP stack 10a will be described. Here, the address set in the ad hoc network driver 10e of the source node SM is 192.168.0.1, and the address of the source node SM is 192.168.1.1 as an example of the address set in the Ethernet network driver 10c. For example, the address set in the ad hoc network driver 10d of the destination node RM is 192.168.0.2, and the address set in the Ethernet network driver 10c of the destination node RM is 192.168.1.2.

When traffic having a destination address of 192.168.0.2 is generated at the destination node SM, the routing processing module included in the IP stack may be configured in the routing table or the same network check set by the ad hoc routing module 10b, for example, the destination IP address. Is 192.168.0.2, the IP datagram is transmitted to the ad hoc network driver 10d by the network address 192.168.0.0.

The interface module 10e receives the data link frame from the ad hoc network driver 10d and transfers it to the simulated physical layer module 10f. The simulation physical layer module 10f simulates the transmission processing delay of the designed actual simulation physical layer, and then transfers the data link frame to the IP processing module 10g. The IP processing module 10g transfers the processed IP processing datagram to the IP stack 10a by adding the IP processing header to the data link frame. At this time, the sender address of the IP header is set to the Ethernet address of the sender node SM, and the destination IP address is set to the Ethernet network broadcast address of the destination node RM. Here, if the Ethernet network driver address of the destination node is 192.168.1.1, the broadcast address is 192.168.1.255.

Finally, the IP stack 10a performs a routing table or the same network check set by the ad hoc routing module 10b in the routing processing module included in the IP stack 10a again with respect to the received IP processing datagram. The IP processing datagram is transmitted to the Ethernet driver 10c, which is an Ethernet interface of the node SM. Then, it is transmitted to the Ethernet driver 10c of the destination node RM via Ethernet.

Hereinafter, a packet receiving process of the interface module 10e, the simulated physical layer module 10f, and the IP processing module 10g in the Ethernet-based ad hoc network verification system according to the present invention will be described with reference to FIG.

First, the IP processing module 10g waits to receive the processed IP datagram from the IP stack 10a (S601).

Next, when the IP processing module 10g receives the processed IP processing datagram from the IP stack 10a (S602), the IP processing module 10g receives the IP processing header of the IP processing datagram received in step S602. Parse (S603).

The IP processing module 10g checks whether the IP address is a broadcast address, and removes the IP processing header (S604).

The IP processing module 10g transmits the data link frame from which the IP processing header has been removed to the simulation physical layer module 10f (S605).

The simulated physical layer module 10f receives a data link frame (S606).

The simulation physical layer module 10f reports that the channel is in use to the interface module after a delay by the preamble reception processing time of the physical communication unit 40 physical layer (S607). Here, the interface module 10e transmits the received report to the ad hoc network driver 10d.

The simulation physical layer module 10f generates an error in an arbitrary bit of the received frame based on the Bit Error Rate (BER) of the actual communication unit 40 physical layer (S608).

The simulated physical layer module 10f transmits a data link frame to the interface module 10e after delaying the data slot reception processing time of the physical communication unit 40 physical layer, and reports that the channel is not in use (S609). .

The interface module 10e transmits the data link frame and channel unused report to the network driver 10d (S610).

Through the above-described process, the control unit 20 according to the present invention can perform the function of measuring the success rate of transmission according to the actual physical layer transmission quality, as in the case of data transmission, and simulates the CCA function by the channel usage and unused reporting By doing so, MAC performance can be evaluated.

Hereinafter, a process of receiving data in the IP stack 10a will be described. Here, the address set in the ad hoc network driver 10d of the destination node SM is 192.168.0.1, and the address of the destination node SM is 192.168.1.1 as an example of the address set in the Ethernet network driver. The address set in the ad hoc network driver 10e of the RM is 192.168.0.2, and the address set in the Ethernet network driver 10d of the destination node RM is 192.168.1.2 as an example.

First, IP stack 10a receives an IP datagram from Ethernet driver 10c. In addition, the IP stack 10a examines an IP processed header field (using a reserved field) in the IP header to distinguish whether an IP processed datagram or a general IP datagram. If the received IP datagram is an IP processing datagram, the received IP datagram is transferred to the IP processing module 10g. As described above, the physical layer module 10f, the interface module 10e, and the network driver ( After performing each function of 10d), the IP datagram is finally transferred from the network driver 10d to the IP stack 10a.

When the destination IP address of the IP header is 192.168.0.2, which is its own IP address, the IP stack 10a delivers a TCP or UDP datagram to a higher layer by parsing and removing the IP header.

As mentioned above, the present invention has been described in detail through preferred embodiments, but the present invention is not limited thereto and may be variously implemented within the scope of the claims.

The present invention proposes a method for performing performance verification of ad hoc network software by simulating a physical layer based on Ethernet when the development of hardware such as a modem, RF, and antenna is not completed in ad hoc network software verification. do. The present invention can be applied to USN and SDR radios available for military use, and can be used for verification of ad hoc network software before system integration of software and hardware in ad hoc network waveform development.

10a: IP stack, 10b: ad hoc routing module
10c: ethernet driver, 10d: network driver
10e: interface module, 10f: simulated physical layer module
10g: IP processing module, 10: network stack
20: control unit, 30: Ethernet device
40: communication unit, SN: source node
MN: intermediate node, RN: destination node
TN: node other than destination, DH: DL header
IH: IP header, EH: Ethernet header

Claims (10)

A network stack 10 for driving the communication unit 40 using the ad hoc network; And
The module provided in the network stack 10 and the physical layer affecting the network among the physical layers of the communication unit 40 are implemented as a simulated physical layer module 10f through Ethernet to drive the communication unit 40. Control unit 20 to simulate
Including;
The network stack 10 is a lower module,
An interface module (10e) including an interface commonly used in the communication unit (40), and determining whether to transfer a data link frame to the simulated physical layer module (10f) or the actual physical layer at the time of implementation completion; And
Add an IP header (IH) to the datalink frame generated by the network stack 10 at the time of data transmission, and reflect the characteristics of the wireless communication in which all nodes within one hop distance receive packets. IP processing module (10g) to set the address to the broadcast address of the Ethernet network
Ethernet-based ad hoc network verification system comprising a. The method of claim 1,
The simulated physical layer module (10f),
Simulating at least one of a physical layer transmission processing time delay and a receiving processing time delay simulation function of the communication unit 40, a report simulation function of channel usage, and a BER quality simulation function by the control of the control unit 20. An Ethernet-based ad hoc network verification system. delete The method of claim 1,
The control unit 20,
The one-hop communication is performed so that a node located within a predetermined communication communication distance from a transmitting node (SN) that transmits the data and whose node does not match the destination IP address among the nodes receiving the data deletes the data. Ethernet-based ad hoc network verification system characterized by controlling all nodes within distance. The method of claim 1,
The control unit 20,
An intermediate location located within a predetermined distance from the source node SN and storing routing information for transmitting the data to a destination node RN located outside a predetermined distance from the source node SN transmitting the data. Ethernet-based ad hoc network verification system, characterized in that all nodes within the one-hop communication distance are controlled to transmit the data via a node (MN). Receiving a datalink frame;
Transmitting the data link frame to a simulated physical layer module (10f);
Generating an IP header IH in the IP processing module 10g and adding the data header to the data link frame to generate a new IP processing datagram;
Delivering the generated IP processed datagram to an Ethernet device (30) via an IP stack (10a); And
The simulation physical layer module (10f) is an Ethernet-based ad hoc network verification method comprising the step of delaying the time reflecting the transmission processing time of the actual physical layer. The method according to claim 6,
The IP processing module (10g) receiving the processed IP datagram from the IP stack (10a);
Parsing, by the IP processing module (10g), an IP header of the received IP datagram;
Confirming, by the IP processing module (10g), whether the IP address included in the IP datagram is a broadcast address;
Removing the IP header (IH) if the IP address matches the broadcast address as a result of the checking;
Transmitting the data link frame from which the IP header (IH) has been removed to the simulation physical layer module (10f); And
The simulation physical layer module (10f) is characterized in that the Ethernet-based ad hoc network verification method comprising the step of transmitting the data link frame to the interface module (10e) after the delay time as long as reflecting the reception processing time. Receiving, by the IP processing module 10g, the processed IP datagram from the IP stack 10a;
Parsing, by the IP processing module 10g, an IP header IH of the received IP datagram;
Confirming, by the IP processing module (10g), whether the IP address included in the IP datagram is a broadcast address;
Removing the IP header (IH) if the IP address matches the broadcast address as a result of the checking;
Transmitting the data link frame from which the IP header (IH) has been removed to the simulation physical layer module (10f); And
The simulation physical layer module (10f) is characterized in that the Ethernet-based ad hoc network verification method comprising the step of transmitting the data link frame to the interface module (10e) after the delay time as long as reflecting the processing time. The method of claim 8,
The simulation physical layer module (10f) delaying the preamble reception processing delay time in the physical layer frame designed as the interface module (10e), and then notifying the IP processing module that the channel is in use; And
And delaying the data slot reception processing time of the physical layer, forwarding a data link frame to an interface module, and reporting that the channel is not in use. The method of claim 8,
The simulation physical layer module 10f is an Ethernet-based ad hoc network verification, which generates an error in an arbitrary bit for the entire received packet based on the BER of the communication layer physical layer 40 designed as the interface module 10e. Way.

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