KR101033370B1 - Image Sensor and Method for Manufacturing Thereof - Google Patents

Abstract

An image sensor according to an embodiment includes a semiconductor substrate including a wiring and an interlayer insulating layer; A lower electrode formed on the interlayer insulating layer to be electrically connected to the wiring; A silicide layer formed on a surface of the lower electrode; A silicon layer formed on the interlayer insulating layer including the lower electrode and the silicide layer; And an image sensing unit formed on the silicon layer.

Semiconductor device, photodiode, bonding

Description

Image Sensor and Method for Manufacturing Thereof}

Embodiments relate to an image sensor and a manufacturing method thereof.

An image sensor is a semiconductor device that converts an optical image into an electrical signal, and is classified into a charge coupled device (CCD) image sensor and a complementary metal oxide silicon (CMOS) image sensor (CIS). do

CMOS image sensors are manufactured by forming MOS transistors as many as the number of pixels, forming a light sensing portion for sensing light at each light collecting portion of the transistor, and having a circuit for processing the detected light as an electrical signal as a peripheral circuit. It is becoming.

The image sensor has a structure in which a photo diode region for converting a light signal into an electrical signal and a transistor region for processing the electrical signal are horizontally disposed.

Such a horizontal image sensor is limited in that the photodiode region and the transistor region are horizontally disposed on the semiconductor substrate to extend the light sensing portion (commonly referred to as "Fill Factor") under a limited area.

As an alternative to overcome this problem, the circuitry is formed on a silicon substrate by depositing a photodiode with amorphous silicon or by using wafer-to-wafer bonding. Attempts have been made to form photodiodes on the lead-out circuit (hereinafter referred to as "three-dimensional image sensor"). The photodiode and the circuit area are connected through a metal line.

However, in the case of wafer-to-wafer bonding, the bonding surface of the wafer is not uniform, and thus the bonding force may be lowered. This is because the wiring for connecting the photodiode and the circuit region is exposed to the surface of the interlayer insulating layer. That is, since the interlayer insulating layer has a non-uniform surface profile, the adhesive force between the wiring and the wafer is weak, which may cause de-bonding of the wafer in an area where the wiring is exposed.

The embodiment provides an image sensor having excellent electrical and physical contact force when bonding the image sensing unit by forming a silicide layer on a substrate on which a readout circuit is formed while employing a vertical image sensing unit, and a method of manufacturing the same.

An image sensor according to an embodiment includes a semiconductor substrate including a wiring and an interlayer insulating layer; A lower electrode formed on the interlayer insulating layer to be electrically connected to the wiring; A silicide layer formed on a surface of the lower electrode; A silicon layer formed on the interlayer insulating layer including the lower electrode and the silicide layer; And an image sensing unit formed on the silicon layer.

A method of manufacturing an image sensor according to an embodiment includes forming a wiring and an interlayer insulating layer on a semiconductor substrate; Forming a lower electrode on the interlayer insulating layer to be electrically connected to the wiring; Forming a silicon layer on the interlayer insulating layer including the lower electrode; Forming a silicide layer on a surface of the lower electrode; And bonding an image sensing unit on the silicon layer.

According to the image sensor and the method of manufacturing the same, the silicon layer formed of the lower electrode and the amorphous silicon is formed on the semiconductor substrate on which the readout circuit is formed, thereby improving bonding characteristics with the image sensing unit.

In addition, a silicide layer is formed on the surface of the lower electrode, thereby reducing the contact resistance of the lower electrode, thereby improving the liquid current characteristics.

A method of manufacturing an image sensor according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where described as being formed "on / over" of each layer, the on / over may be directly or through another layer ( indirectly) includes everything formed.

In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not necessarily reflect the actual size.

The embodiment is not limited to the CMOS image sensor, and may be applied to all image sensors requiring a photodiode such as a CCD image sensor.

10 is a cross-sectional view illustrating an image sensor according to an embodiment.

An image sensor according to an embodiment includes a semiconductor substrate 100 including a wiring 150 and an interlayer insulating layer 160; A lower electrode 175 formed on the interlayer insulating layer 160 to be electrically connected to the wiring 150; A silicide layer 177 formed on a surface of the lower electrode 175; A silicon layer 185 formed on the interlayer insulating layer 160 including the lower electrode 175 and the silicide layer 177; And an image sensing unit 200 formed on the silicon layer 185.

For example, the lower electrode 175 may be formed of metals such as Cr, Ti, TiW, and Ta. In addition, the silicon layer 185 may be formed of an intrinsic layer or an n-type amorphous silicon. In addition, the silicide layer 177 may be formed of chromium silicide (Cr-silicide).

The silicon layer 185 including the lower electrode 175 may be formed on the wiring 150 to improve the bonding property between the image sensing unit 200 and the semiconductor substrate 100. In addition, a silicide layer 177 may be formed on the surface of the lower electrode 175 to reduce contact resistance of the lower electrode 175, thereby improving leakage current characteristics.

The silicon layer 185 may be formed at the same height as the silicide layer 177 so that the silicide layer 177 is exposed. Since the silicide layer 177 and the image sensing unit 200 are electrically connected directly, photocharge transfer characteristics may be improved.

Unexplained reference numerals among the reference numerals of FIG. 10 will be described in the following manufacturing method.

Unexplained reference numerals among the reference numerals of FIG. 10 will be described in the following manufacturing method.

Hereinafter, a method of manufacturing an image sensor according to an embodiment will be described with reference to FIGS. 1 to 10.

Referring to FIG. 1, a wiring 150 and an interlayer insulating layer 160 are formed on a semiconductor substrate 100 including a readout circuit 120.

The semiconductor substrate 100 may be a single crystal or polycrystalline silicon substrate, and may be a substrate doped with p-type impurities or n-type impurities. An isolation region 110 is formed on the semiconductor substrate 100 to define an active region, and a readout circuit 120 including a transistor is formed in the active region.

2 is a detailed view of a readout circuit corresponding to a unit pixel.

For example, the readout circuit 120 may include a transfer transistor (Tx) 121, a reset transistor (Rx) 123, a drive transistor (Dx) 125, and a select transistor (Sx) 127. can do. Thereafter, an ion implantation region 130 including a floating diffusion region (FD) 131 and source / drain regions 133, 135, and 137 for each transistor may be formed. Meanwhile, the readout circuit 120 may be applied to a 3Tr or 5Tr structure.

The forming of the lead-out circuit 120 on the semiconductor substrate 100 may include forming an electrical junction region 140 on the semiconductor substrate 100 and the wiring 150 on the electrical junction region 140. The method may include forming a first conductivity type connection region 147 connected to the first conductive connection region 147.

For example, the electrical junction region 140 may be a PN junction 140, but is not limited thereto. For example, the electrical junction region 140 may include a first conductive ion implantation layer 143 and a first conductive ion implantation layer (143) formed on the second conductive well 141 or the second conductive epitaxial layer. 143 may include a second conductivity type ion implantation layer 145. For example, the PN junction 140 may be a P0 145 / N- 143 / P-141 junction as shown in FIG. 1, but is not limited thereto. In addition, the semiconductor substrate 100 may be conductive in a second conductivity type, but is not limited thereto.

According to the embodiment, the device can be designed such that there is a voltage difference between the source / drain across the transfer transistor Tx, thereby enabling full dumping of the photo charge. Accordingly, as the photo charge generated in the photodiode is dumped into the floating diffusion region, the output image sensitivity may be increased.

That is, by forming an electrical junction region 140 in the semiconductor substrate 100 on which the readout circuit 120 is formed, there is a voltage difference between the source / drain across the transfer transistor (Tx) 121 so as to completely dump the photocharge. This can be made possible.

Hereinafter, the dumping structure of the photocharge of the embodiment will be described in detail with reference to FIGS. 2 and 3.

Unlike the floating diffusion (FD) 131 node, which is an N + function in the embodiment, the P / N / P section 140, which is an electrical junction region 140, does not transmit all of the applied voltage and pinches at a constant voltage. It is off (Pinch-off). This voltage is called a pinning voltage and the pinning voltage depends on the P0 145 and N- (143) doping concentrations.

Specifically, the electrons generated by the photodiode 205 are moved to the PNP caption 140 and are transferred to the FD 131 node when the transfer transistor (Tx) 121 is turned on and converted into voltage.

Since the maximum voltage value of the P0 / N- / P- caption 140 becomes pinning voltage and the maximum voltage value of the FD 131 node becomes Vdd-Rx Vth, as shown in FIG. Due to this, electrons generated from the photodiode on the chip may be completely dumped to the FD 131 node without charge sharing.

That is, in the embodiment, the reason why the P0 / N- / Pwell junction is formed instead of the N + / Pwell junction in the silicon sub, which is the semiconductor substrate 100, is P0 / N- / Pwell during the 4-Tr APS Reset operation. In the junction, + voltage is applied to N- (143) and ground voltage is applied to P0 (145) and Pwell (141). Therefore, P0 / N- / Pwell double junction is more than Pinch-Off as in BJT structure. Will occur. This is called pinning voltage. Therefore, a voltage difference is generated in the source / drain at both ends of the Tx 121, and thus the photocharge is completely dumped from the N-well to the FD through the Tx at the Tx On / Off operation to prevent the charge sharing phenomenon.

Therefore, unlike the case where the photodiode is simply connected with N + junction in the technology of a general image sensor, according to the embodiment, problems such as degradation of saturation and degradation of sensitivity can be avoided.

Next, according to the embodiment, the first conductive connection region 147 is formed between the photodiode and the lead-out circuit 120 to minimize the dark current source by creating a smooth movement path of the photo charge. Deterioration of saturation and degradation of sensitivity can be prevented.

To this end, the embodiment may form an N + doped region as the first conductive connection region 147 for ohmic contact on the surface of the P0 / N− / P− junction 140. The N + region 147 may be formed to contact the N− 143 through the P0 145.

Meanwhile, in order to minimize the first conductive connection region 147 from becoming a leakage source, the width of the first conductive connection region 147 may be minimized.

To this end, the embodiment may proceed with a plug implant after etching the second metal contact 151a, but is not limited thereto. For example, the first conductive connection region 147 may be formed by forming an ion implantation pattern (not shown) and using the ion implantation mask as an ion implantation mask.

That is, the reason for N + doping locally only in the contact forming part as in the embodiment is to facilitate the formation of ohmic contact while minimizing the dark signal. As in the prior art, when N + Doping the entire Tx Source part, the dark signal may increase due to the substrate surface dangling bond.

4 shows another structure for the readout circuit. As shown in FIG. 4, a first conductive connection region 148 may be formed on one side of the electrical junction region 140.

Referring to FIG. 4, an N + connection region 148 for ohmic contacts may be formed in the P0 / N− / P− junction 140, wherein the process of forming the N + connection region 148 and the M1C contact 151a is performed. It can be a Leakage Source. This is because the electric field EF may be generated on the Si surface of the substrate because the reverse bias is applied to the P0 / N− / P− junction 140. Crystal defects that occur during the contact formation process inside these electric fields become a source of liquidity.

In addition, when the N + connection region 148 is formed on the surface of the P0 / N- / P- junction 140, an E-Field by the N + / P0 junction 148/145 is added, which is also a leakage source. Can be

That is, the first contact plug 151a is formed in an active region formed of the N + connection region 148 without being doped with the P0 layer, and a layout for connecting the first contact plug 151a with the N-junction 143 is presented. .

Then, the E-Field of the surface of the semiconductor substrate 100 does not occur, which may contribute to the reduction of dark current of the 3-D integrated CIS.

Referring back to FIGS. 1 and 2, the wiring 150 includes a first metal contact 151a, a first metal M1 151, a second metal M2 152, and a third metal M3. 153 and the fourth metal contact 154a may be included, but are not limited thereto. In an embodiment, after forming the fourth metal contact 154a, a CMP process may be performed to expose the surfaces of the fourth metal contact 154a and the interlayer insulating layer 160. The wiring 150 may be formed for each pixel and connected to the readout circuit 120, respectively. Meanwhile, the pad P may be formed when the third metal 153 is formed.

Referring to FIG. 5, the lower electrode layer 170 is formed on the interlayer insulating layer 160 including the wiring 150. The lower electrode layer 170 may be entirely formed on the wiring 150 and the interlayer insulating layer 160 to be electrically connected to the wiring 150. For example, the lower electrode layer 170 may be formed of chromium (Cr) and formed to a thickness of 500 to 1000 Å. The lower electrode layer 170 may be formed of not only chromium (Cr) but also metals such as Ti, TiW, and Ta.

Referring to FIG. 6, a lower electrode 175 is formed to be connected to the wiring 150, respectively. The lower electrode 175 may be formed by forming a photoresist pattern (not shown) on the lower electrode layer 170 corresponding to the wiring 150 and then performing an etching process. Accordingly, the lower electrode 175 may be formed on the fourth metal contact 154a and separated for each unit pixel.

Referring to FIG. 7, a first silicon layer 180 is formed on the interlayer insulating layer 160 including the lower electrode 175. The first silicon layer 180 may be formed of amorphous silicon. For example, the first silicon layer 180 may be formed of intrinsic amorphous silicon or n-type amorphous silicon.

For example, the first silicon layer 180 may be formed of amorphous silicon using silane gas or the like by chemical vapor deposition, in particular, a PECVD process. The first silicon layer 180 may be formed to a thickness of about 1500 ~ 2000Å. Meanwhile, when the first silicon layer 180 is n-type amorphous silicon, the first silicon layer 180 may be formed by mixing PH ₃ , P ₂ H _5, or the like with silane gas (SiH ₄ ).

Referring to FIG. 8, a second silicon layer 185 is formed by performing a CMP process on the first silicon layer 180. Since the first silicon layer 180 is formed on the interlayer insulating layer 160 including the lower electrode 175 to have a step, a planarization process for the first silicon layer 185 is required.

Accordingly, the planarized second silicon layer 185 may be formed by performing a CMP process on the first silicon layer 180. The second silicon layer 185 may be formed to a thickness of 500 ~ 1000Å. That is, the second silicon layer 185 may be formed to have the same or thicker thickness as the lower electrode 175. 8 illustrates that the thickness of the second silicon layer 185 is greater than that of the lower electrode 175.

9, a silicide layer 177 is formed on a surface of the lower electrode 175. The silicide layer 177 may be formed by performing an annealing process on the second silicon layer 185. That is, when the annealing process is performed, chromium silicide may be formed at an interface between the second silicon layer 185 formed of amorphous silicon and the lower electrode 175 formed of chromium, thereby forming the silicide layer 177. For example, the annealing process may be performed at a temperature of 250 to 350 ° C., a time of 30 to 60 minutes, and an N ₂ gas atmosphere.

Accordingly, the silicide layer 177 is formed on the surface of the lower electrode 175 by the reaction with the second silicon layer 185, and thus the semiconductor substrate 100 and the image sensing unit on which the readout circuit 120 is formed. Bonding characteristics of the 200 can be improved. That is, since the lower electrode 175, the silicide 177, and the second silicon layer 185 are formed on the fourth metal contact 154a, bonding characteristics with the image sensing unit 200 formed of crystalline silicon may be improved. have.

Referring to FIG. 10, the image sensing unit 200 is bonded onto the second silicon layer 185 including the lower electrode 175 and the silicide layer 177. The image sensing unit 200 may be formed of an n-type doped layer (n−) and a p-type doped layer (p +) to have a photodiode structure of a PN junction.

For example, the image sensing unit 200 may be formed by ion implantation of n-type impurities and p-type impurities in order inside a p-type carrier substrate (not shown) having a crystalline structure. The carrier substrate (not shown) and the semiconductor may be formed by placing the n-type doping layer (n−) of the image sensing unit 200 on the second silicon layer 185 so as to face each other. The substrate 100 may be bonded. Thereafter, the carrier substrate (not shown) is removed to expose the p-type doping layer p + of the image sensing unit 200 bonded to the second silicon layer 185.

According to the exemplary embodiment, the image sensing unit 200 may prevent the defect of the image sensing unit 200 while increasing the fill factor by employing a 3D image sensor positioned above the readout circuit 120.

In addition, the second silicon layer 185, which is a bonding surface of the semiconductor substrate 100, may be formed of amorphous silicon to improve bonding characteristics with the image sensing unit 200. That is, the lower electrode 175 and the second silicon layer 185 are formed on the interlayer insulating layer 160 so that the wiring 150 as the signal transmission means of the readout circuit 120 is not exposed. Since bonding with the unit 200, it is possible to improve the bonding characteristics.

In addition, a silicide layer 177 may be formed on the lower electrode 175 to reduce contact resistance of the lower electrode 175, thereby improving leakage current characteristics.

FIG. 11 illustrates that the silicide layer 177 and the third silicon layer 187 of the lower electrode 175 are formed at the same height.

Referring to FIG. 11, the silicide layer 177 formed on the lower electrode 175 is exposed. For example, after the silicide layer 177 is formed, the third silicon layer 187 may be formed by performing a CMP process on the second silicon layer 185. In the CMP process, the silicide layer 177 may be used as an end point of polishing so that the silicide layer 177 and the third silicon layer 187 may have the same height. Therefore, the silicide layer 177 of the lower electrode 175 may be exposed.

Referring to FIG. 12, the image sensing unit 200 is bonded on the silicide layer 177 and the third silicon layer 187. Since the bonding process of the image sensing unit 200 and the semiconductor substrate 100 is the same as the process described with reference to FIG. 10, a description thereof will be omitted.

The image sensing unit 200 may be bonded to the silicide layer 177 of the lower electrode 175 to further improve the transfer efficiency of the photocharges generated by the image sensing unit 200. That is, since the image sensing unit 200 and the silicide layer 177 of the lower electrode 175 are in contact with each other, the charge transfer characteristic may be shaped. In addition, since the silicide layer 177 is formed between the lower electrode 175 and the image sensing unit 200, the contact resistance may be reduced to improve the leakage characteristics.

Thereafter, a pixel separation layer 210 penetrating through the image sensing unit 200 and the third silicon layer 187 is formed so that the image sensing unit 200 is separated by unit pixels. For example, the pixel isolation layer 210 may be formed through an ion implantation process or an STI process between the image sensing unit 200 and the silicon layer 185 corresponding to the lower electrode 175. have.

Therefore, the image sensing unit 200 may be separated by unit pixels, and photoelectric charges generated by each image sensing unit 200 may be transferred to the corresponding readout circuit 120 to operate. Meanwhile, when the image sensing unit 200 is separated by unit pixels, the image sensing unit 200 and the third silicon layer 187 corresponding to the pad P are removed to remove the interlayer insulating layer 160. The surface may be exposed.

Although not shown, an upper electrode, a color filter, and a microlens may be formed on the image detector 200.

The above-described embodiments are not limited to the above-described embodiments and drawings, and it is common in the technical field to which the present embodiments belong that various changes, modifications, and changes can be made without departing from the technical spirit of the present embodiments. It will be apparent to those who have

1 to 12 are views illustrating a manufacturing process of an image sensor according to an embodiment.

Claims (11)

A semiconductor substrate including a wiring and an interlayer insulating layer; A lower electrode formed on the interlayer insulating layer to be electrically connected to the wiring; A silicide layer formed on at least a portion of the surface of the lower electrode; A silicon layer formed on the interlayer insulating layer including the lower electrode and the silicide layer; And And an image sensing unit formed on the silicon layer, wherein the silicon layer is formed at the same height as that of the silicide layer formed on the lower electrode and the lower electrode. The method of claim 1, The silicide layer is formed of chromium silicide (Cr-silicide), characterized in that the image sensor. The method of claim 1, The silicon layer is an image sensor, characterized in that formed of an intrinsic layer or n-type amorphous silicon (n-type amorphous silicon). delete Forming a wiring and an interlayer insulating layer on the semiconductor substrate; Forming a lower electrode on the interlayer insulating layer to be electrically connected to the wiring; Forming a silicon layer on the interlayer insulating layer including the lower electrode; Forming a silicide layer on at least a portion of a surface of the lower electrode; And Bonding an image sensing unit on the silicon layer; The silicide layer is formed by performing an annealing process on the silicon layer formed on the lower electrode. delete The method of claim 5, Forming the silicon layer is, Forming an amorphous silicon layer on the interlayer insulating layer including the lower electrode; And The manufacturing method of the image sensor comprising the step of performing a CMP process for the amorphous silicon layer. The method of claim 5, The silicon layer is a method of manufacturing an image sensor, characterized in that formed of an intrinsic layer or n-type amorphous silicon (n-type amorphous silicon). The method of claim 5, And forming a silicide layer to expose the surface of the silicide layer by performing a CMP process on the silicon layer. The method of claim 5, The silicide layer is formed of chromium silicide (Cr-silicide) characterized in that the manufacturing method of the image sensor. The method of claim 5, And forming a pixel separation layer penetrating the image sensing unit and the silicon layer so that the image sensing unit is separated for each unit pixel.

Images