KR101032000B1 - Self-repairing electronic circuit system and self-repairing method by mimicking cell differentiation - Google Patents

Abstract

PURPOSE: A self-failure recovery circuit system and self-failure recovery method are provided to increase the operational reliability of an electronic circuit and to search for the location of failure by dividing an electronic circuit by unit. CONSTITUTION: A failure determining and differentiating unit(120) recognizes the location and failure of a sub module. A recovery management unit(110) determines a partition area of a sub module. The failure determining and differentiating unit differentiates the sub module having failure. A semiconductor circuit unit includes four intrinsic differentiating areas of the sub module.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0002] The present invention relates to a self-repairing electronic circuit system and a self-repairing method,

The present invention relates to a self-repairing electronic circuit system and a self-failure recovery method that simulate a cell differentiation function. More particularly, when a failure occurs in a semiconductor unit of a programmable device, for example, an FPGA, The present invention relates to an electronic circuit system having a self-failure recovery function capable of diagnosing and repairing such faults by utilizing the concept of a stem cell, which is an inherent characteristic, and a self-failure recovery method.

Various techniques for detecting and repairing faulty portions of semiconductor electronic circuits have been studied. One of these techniques is disclosed in European Patent No. EP1170666A3, in which a hardware structure to be implemented is formed on one side, and a region for diagnosing a fault in the horizontal and vertical directions is set on the outside of the area. Using this technique, the fault area can be recovered by using the fault diagnosis area on the outer side. However, this technique is limited to complex circuitry and scalability, as far as hardware is concerned, including fault diagnosis areas. Therefore, there is a disadvantage in that it can not be designed in a fluid manner. In order to solve such a problem, there is a disadvantage that it is difficult to design a complicated circuit although the circuit to be implemented is divided into two parts.

According to Korean Patent No. 10-0354437 for failure recovery, this is an "integrated circuit semiconductor device having a magnetic recovery circuit for internal memory and a memory recovery method ", which uses row and column redundancy to generate And recovery of rows and columns of defective cells is performed. However, this structure is an inefficient failure recovery method in that even if only one bad cell occurs in one row or column, all the rows or columns are replaced.

The cell-based self-healing method that solves this problem is described in P.K. Quot; on self-healing digital system design "published by Lala et al. In the ELSEVIER Microelectronics Journal. In this method, four functional cells surround one extra cell in the east, west, south, and north directions. For the functional cell in which the error occurs, the neighboring spare cell performs the function of the failed functional cell do. However, this structure has a disadvantage in that the self-failure recovery is performed only once for a specific functional cell. Also, P.K. Lala's technique implements the functions of each functional cell in a truth table format. Therefore, although the combinational circuit can be easily implemented, the sequential circuit has a disadvantage that it is difficult to implement.

A technique for differentiating a faulty circuit into a new area among other techniques for self-failure recovery is disclosed in Gianluca Tempesti et al., &Quot; The BioWall: an Electronic Tissue for Prototyping Bio-inspired systems ", IEEE NANA / DOD Conference on Evolvable Hardware will be. The method proposed by Tempesti et al. Uses a single processor based on a single cell to design a digital clock, and a new processor on the side of the error causes the new processor to perform this function. This technique allows the hardware structure design to instantaneously verify that the simulation of the error part is programmable.

However, this technique has a disadvantage in that it requires many complex processors for one implementation circuit.

Therefore, there is a desperate need for a self-recovery method that can repair failures repeatedly for several faults while ensuring various applicability, rather than using fixed hardware.

It is another object of the present invention to provide a method and apparatus for dividing an entire circuit of an implemented digital circuit into detailed functional units to accurately locate a fault occurring in an arbitrary portion of the digital circuit, I will.

Another object of the present invention is to determine whether a temporary failure or a permanent failure has occurred after testing a faulty portion of a digital circuit and to use the fault portion judged as a temporary failure as a redundancy of an originally implemented circuit, Lt; RTI ID = 0.0 > failure. ≪ / RTI >

It is still another object of the present invention to provide a semiconductor circuit which can prevent the output of a faulty circuit from being broken and divide a circuit having the same function into a different area to perform the function, Thereby improving operation stability.

According to an aspect of the present invention, there is provided a programmable electronic circuit system including a semiconductor circuit unit designed in a double modular redundancy (DMR) structure, wherein a failure occurs in a plurality of submodules constituting a semiconductor circuit unit And the position of the sub-module in which the failure has occurred, and a position of the sub-module in which the failure has occurred from the failure determination / And a recovery management unit for determining the area and delivering it to the failure determination / differentiation unit.

According to still another aspect of the present invention, there is provided a programmable electronic circuit system including a semiconductor circuit portion designed with a double modular redundancy (DMR) structure, wherein the semiconductor module includes a plurality of sub- A failure determination and classification unit for determining a location of a sub module where a failure occurs; And a recovery management unit that receives the location of the sub module where the failure has occurred from the failure determination and differentiation unit, determines a differentiation area for differentiating the sub module where the failure has occurred, and transmits the determination result to the failure determination and differentiation unit, Wherein the judging and erecting unit differentiates the submodule in which the failure has occurred to the differentiation region received from the recovery management unit, the semiconductor circuit unit includes four unique differentiation regions and four common differentiation regions for each submodule, Wherein the common failure region is shared by 16 submodules, wherein the failure determination and differentiation unit includes four management modules that commonly manage respective operation modules including 16 submodules, , Comparing the two outputs of the sub-module having the DMR structure to detect a failure, A failure detection unit for determining a position of a sub module in which a failure occurs when a failure is detected; A self test unit for comparing the output results after applying the same input to the sub module in which the failure occurs and judging the result as a permanent failure if a discrepancy result is repeated; And a differentiation unit for differentiating an original pattern of the sub-module in which the failure has occurred from the failure determination and differentiation unit to the differentiation area received from the failure determination and differentiation unit.

In particular, the current status information of the sixteen sub-modules is commonly transmitted to the four management modules, and one of the four management modules is a dominant management module, Is determined. Preferably, when the current state information of the sixteen sub-modules is commonly transmitted to the four management modules, the management modules deliver current state information and their own addresses to the recovery management unit, respectively, If the information does not match the current status information received from the other management module, the recovery management unit determines that a failure has occurred in the main management module and sets the other management module among the four management modules as a new main management module. In addition, the self-test unit may permanently suspend operation of the sub-modules determined to be a permanent failure among the sub-modules in which the failure has occurred, set the sub-module determined to be not a permanent failure back as a normal sub- redundancy module). In addition, the recovery management unit divides the failed submodule into any one of the four distinctive divisional areas, and if all of the distinctive divisional areas are not available, the restoration management unit allocates the failed submodule to any one of the common divisional areas And the failure judgment / differentiation unit is controlled so as to be differentiated. In particular, in the semiconductor circuit, the sub-module is the minimum unit for diagnosing and repairing faults, and four operation blocks, each consisting of four sub-modules, each have (1, 1), (1, 3) ), And (3, 3), and each of the five differentiation blocks, each of which is made up of four differentiation regions, is disposed at each of the remaining element positions of the matrix, and the differentiation blocks arranged at the (2, 2) Is operated as a common differentiation region.

According to another aspect of the present invention, there is provided a method for repairing a failure of a programmable electronic circuit system including a semiconductor circuit portion designed in a dual modularity (DMR) structure, Determining whether a failure occurs in a plurality of submodules constituting the semiconductor circuit portion including four different division regions and four common division regions shared by the sixteen submodules; A failure location determination step of determining a location of a sub module in which a failure occurs if a failure occurs; Determining a differentiation region for differentiating the submodule in which a failure has occurred; And a differentiating step of differentiating an original pattern of the submodule in which the failure has occurred in the determined differentiation area, wherein the step of determining the differentiation area determines whether there is redundancy of the module and then preferentially uses the redundancy, And if there is no redundancy, differentiates the submodule into the unique differentiation region, and if the available unique differentiation region does not exist, differentiates into the common differentiation region.

Determining whether the failure occurs by comparing two outputs of the submodule having a DMR structure to detect a failure; Comparing the output result after applying the same input to the sub module where the failure occurs; And a self test step of determining the submodule in which the failure has occurred as a permanent failure when the output result is inconsistent with one or more inputs.

The failure determination step may include detecting a failure by comparing two outputs of a submodule having a DMR structure, comparing output results after applying the same input to the failed submodule, Further comprising a self-testing step of determining that the submodule in which the failure has occurred is a permanent failure if the mismatch occurs in one or more inputs. In addition, the step of determining whether or not the failure is caused includes the steps of: transferring current status information of the 16 sub modules to the four management modules in common; and, if one of the four management modules is the main management module, And determining the position of the generated sub-module. Preferably, when the current state information of the sixteen sub-modules is commonly transmitted to the four management modules, the failure determination step may include the steps of the management modules transmitting the current state information and the own address to the recovery management module, Comparing current state information received from the module with current state information received from another management module; and determining that a failure has occurred in the main management module if the comparison result does not match, As a new main management module. In particular, the self-test step may include permanently blocking the operation of the sub-modules determined to be permanent failures among the failed sub-modules, setting the sub-module determined not to be a permanent failure as a normal sub- And operating as a module. Further, in the step of determining the differentiation region, the sub-module in which the failure occurs is differentiated into one of the four high-density differentiation regions, and when all of the unique differentiation regions are not available, the sub- And determining the differentiation region so as to differentiate into one which is usable.

According to another aspect of the present invention, there is provided a semiconductor circuit unit capable of implementing a self-failure recovery method of the electronic circuit system.

According to the present invention, since the faulty portion of the semiconductor circuit can be grasped by detailed functional units, the faulty portion can be quickly recovered.

Also, according to the present invention, it is possible to compare a temporary failure with a permanent failure, and use a failure portion judged as a temporary failure as a redundancy of an originally implemented circuit, thereby reducing a hardware area required for a failure, Can cope.

Further, according to the present invention, it is possible to improve the reliability of the circuit operation by replicating the original pattern of the circuit region in which the failure occurs in the differentiation region, instead of cutting off the output by the circuit region in which the permanent failure has occurred.

In order to fully understand the present invention, operational advantages of the present invention, and objects achieved by the practice of the present invention, reference should be made to the accompanying drawings and the accompanying drawings which illustrate preferred embodiments of the present invention.

Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. However, the present invention can be implemented in various different forms, and is not limited to the embodiments described. In order to clearly describe the present invention, parts that are not related to the description are omitted, and the same reference numerals in the drawings denote the same members.

Throughout the specification, when an element is referred to as " including " an element, it does not exclude other elements unless specifically stated to the contrary. The terms "part", "unit", "module", "block", and the like described in the specification mean units for processing at least one function or operation, And a combination of software.

1 is a view conceptually showing the structure of an electronic circuit system according to one aspect of the present invention.

As shown in FIG. 1, the electronic circuit system according to the present invention can be divided into three conceptual layers 110, 120, and 130. 1, recovery management unit 110 is illustrated as being responsible for 16 operation areas (operation 1 to operation 16) and 16 management areas (management 1 to management 16). However, it goes without saying that the number of management areas and operation areas included in one electronic circuit system may be more or less. The reason why only the subscripts 1 to 16 are attached to the 25 management areas in FIG. 1 is that the management areas can be arranged cyclically.

Referring to FIG. 1, referring to the failure determination / differentiation unit 120, it can be seen that one operation area can be managed in common by four management areas. For example, 'Action 1' may be managed by four management areas 'Management 1', 'Management 4', 'Management 15', and 'Management 16'. When one of the management areas operates as a main management area and a failure occurs in the main management area, another management area can operate as a main management area.

1, each of the operating regions may be divided into a 3x3 matrix 130, one matrix 130 having four sub-modules (circuit 0 through circuit 3) and five Differentiation regions (differentiation 4 to differentiation 8) are included. Among these, 'differentiation 4' to 'differentiation 7' are the differentiation region and 'differentiation 8' is the common differentiation region, which will be described later in detail in the corresponding part.

The failure determination / classification unit 120 is responsible for management of the lower digital circuit 130 and a differentiation function for differentiating the circuit into a new area for the failed circuit. In addition, the recovery management unit 110 controls the failure determination / The failure determination / classification unit 120 detects a failed part of various lower digital circuits and determines whether the circuit is a temporary failure or a permanent failure. The recovery management unit 110 performs a function of managing the entire flow of the self-failure recovery in the self-failure recovery method.

With respect to the digital circuit, the semiconductor circuit unit 130 divides the semiconductor circuit into modules each of which can be detached first, and divides the modules into the detailed functions. When the semiconductor circuit unit 130 is not separated by the detailed function, if a failure occurs in the circuit, the functioning part is replaced or the whole system is changed. Therefore, in the semiconductor circuit unit 130, do.

In order to judge whether a circuit divided by the detailed function is operating normally, a double modular redundancy (DMR) structure for comparing the outputs of the same circuits is designed and the failure judgment / One management area may be allocated to each of the operation areas included in the failure determination / erasure part 120, and three management areas may simultaneously perform the same management function on the same operation area.

In Figure 1, the DMR outputs of a submodule (e.g., circuits 0 through 3 of 130) are assigned to management areas (e.g., management 9, management 10, management 14, and management 15) It is delivered simultaneously. Then, the failure determining / dividing unit 120 analyzes the received output values to determine the location of the failed sub-module, and transfers the information of the failed circuit 130 to the recovery management unit 110.

The recovery management unit 110 receives information on one failed circuit through the management area of the failure determination / The recovery management unit 110 compares the value delivered by the main management area with the value delivered by the neighboring three management areas to determine whether the current main management area is faulty. In order to determine whether a failure has occurred, a value occupying many of the four received values is regarded as true, and a decimal value can be determined as an error. If the value of the main management area and the values of other management areas are the same, proceed without changing the main management area. On the other hand, when the value of the main management area is different from the value of the neighboring management area, it is determined that a failure occurs in the main management area and one of the other management areas is set as the main management area. At this time, the management area newly set as the main management area performs the management function originally in charge and the management function previously performed in the main management area.

2 is a view conceptually showing a structure of a semiconductor circuit part of an electronic circuit system according to one aspect of the present invention.

As shown in FIG. 2, the semiconductor circuit portion can be divided into 16 sub-modules according to detailed functions. As described above, when a failure occurs by dividing the semiconductor circuit part, it can cope with it promptly and effectively.

The overall structure to be implemented is divided into an input unit 210, an output unit 230, and an implementation circuit 220.

The implementation circuit 220 is divided into four areas (A (240), B (250), C (260), D (270) in FIG. Here, the number of regions is divided into four regions, but the number of regions is increased if the functions are divided into more functions according to complexity in the implementation digital circuit 220.

A 240 divided into functions in the implementation circuit 220 is again divided into four regions 240a, 240b, 240c, and 240d according to the detailed functions. The B 250 is divided into four regions 250a, 250b, 250c and 250d according to the detailed functions. The C 260 is divided into four regions 260a and 260b ), (260c), (260d). Finally, D 270 is divided into four areas 270a, 270b, 270c, and 270d for each detailed function.

The 16 areas that are divided in detail are the parts where the implementation circuit operates. If a failure occurs in this part, the circuit breaks down into the new five differentiation areas. For example, when a failure occurs in A11 (240a), for example, a failure occurs in A12 (240b), and a failure occurs in A12 (240b) (240 h), and when a failure occurs in A 22 (240 d), it is differentiated into (240 g). If there is no further differentiation region in this region, it is differentiated into the common differentiation region 240i. That is, the new differentiation region is 240e, 240f, 240g, 240h, and 240i in the case of the A region, and 250e, 250f, 250g, 260h, 260h and 260i in the case of the C region and 270e, 270f and 270g in the case of the D region, , (270h), and (270i). As described later in FIG. 4, among these differentiation regions, (240i), (250i), (260i), and (270i) are common differentiation regions and the remaining differentiation regions are unique differentiation regions.

In addition, regions (for example, 240a) divided by detailed functions may be divided again and divided into 16 regions. A block in which four final minimum units are bundled is shown at the bottom of Fig. That is, (240a-1), (240a-2), 240a-3, and 240a-4 in FIG. 2 correspond to 410 (0-3) in FIG. To explain this in more detail, referring to FIG. 2 and FIG. 4, A11 240a of FIG. 2 is further divided into a macroblock 410 of FIG. The macroblock 400 shown in FIG. 4 shows squares divided into a 6x6 matrix. Numbers written in each of the divided squares illustrate addresses of corresponding squares. 4, reference numerals 410, 420, 430, and 440 respectively denote an operation area 0, an operation area 1, an operation area 2, and an operation area 3, and reference numerals 450, 460, 470, 480, The differentiation region 5, the differentiation region 6, the differentiation region 7, and the differentiation region 8, respectively. The process of differentiating the operation region of FIG. 4 into the differentiation region will be described later in detail with reference to FIG.

3 is a diagram conceptually illustrating a process of dividing a sub module in which a failure occurs in an electronic circuit system according to an embodiment of the present invention. In Fig. 3, one line consisting of 6 bits indicates an address. That is, the first row of the A differentiation area 310a means the address 16, and the first row of the A operation area 310 means the address 0. Similarly, the first row of the B differentiation region 320a refers to the address 24 and the first row of the B operation region 320 refers to the address 8.

The basic procedure for the self-failure recovery method includes a first step (S360), a second step (S370), and a third step (S380).

First, if a failure occurs in a digital circuit, it is first checked whether there is redundancy for the own module, and if there is no redundancy, the differentiation region must be searched to differentiate. The order of finding the differentiation region will be described later in detail in the corresponding section. It is checked whether there exists a redundancy area for each of the A circuit implementation area 310, the B circuit implementation area 320, the C circuit implementation area 330 and the D circuit implementation area 340 in step S360. The implemented digital circuit includes an A circuit implementation area 310, a B circuit implementation area 320, a C circuit implementation area 330, and a D circuit implementation area 340. If there is no redundancy after the occurrence of a failure in each of these areas, the A circuit implementation area circuit is divided into the A circuit differentiation area 310a, the B circuit implementation area circuit is divided into the B circuit differentiation area 320a, Are differentiated into the C circuit differentiation region 330a and the D circuit implementation region circuit into the D circuit differentiation region 340a, respectively (S370). Here, 310a, 320a, 330a, and 340a correspond to the unique differentiation regions of 310, 320, 330, and 340, respectively. That is, when a failure occurs in the operation area, it is first checked whether there is redundancy in the operation area and it is differentiated into a unique unique division area. The failure to the current operation circuit is preferentially sought in the operation region, the differentiation region, and the common division region, which are different depending on the current operation position.

When a failure occurs in the digital implementation circuit to differentiate into a new differentiated region, a failure occurs again in this new region, and when there is no more available differentiated region, it is differentiated into a common differentiated region 350 (S380). That is, the common differentiation region is used when the available differentiation region no longer exists among the respective distinctive regions for the four operation regions.

Figure 4 is a diagram illustrating the placement of an operating block and a differentiating block. One application is divided into four blocks, and the operation module is 0-3, which corresponds to the operating block. Blocks 4-8 are blocks for differentiating against a failed circuit. The block of the basic application is divided into 2x2 array for one module, the direction of the division is clockwise, and the division process is controlled by the recovery management section.

If a failure occurs in the address 0 of the operation area 0, it first checks whether there is a redundancy area of its own. If there is no redundancy area, it is differentiated into the address 16 of the differentiation area 4. If the 16th address fails or the 16th address is not available, this time it will be differentiated into 17th address. Thus, all four distinct regions (address 16, 17, 18, 19) in which address 0 can be differentiated. If all of the unique differentiation regions are not available, they are further differentiated into the 32rd address of the differentiation region, 8, which is a common differentiation region. If address 32 is not available, this time it can be differentiated into address 33 of the common division. That is, the number of common differentiation regions in which address 0 can be different is four (addresses 32, 33, 34, and 35). Therefore, when a failure occurs, there are eight different kinds of differentiation regions that can be differentiated for one operation submodule. Therefore, the present invention has an advantage of being able to recover many times against repeated faults.

FIG. 5 is a flowchart conceptually illustrating a self-failure recovery method of an electronic circuit system according to another aspect of the present invention.

When the circuit divided by the detailed function operates normally, the output value is received from the circuit implemented by the DMR structure. Then, the received output value is compared with each other to determine whether the failure has occurred (S510). At this time, it is as described above that the failure can be determined by the failure determination and differentiation unit shown in FIG.

If a failure occurs in the circuit divided by the detailed function, it is determined whether it has occurred in the differentiation region or in the operation region (S520). As a result of the determination, if a failure occurs in the operation area, first, the output portion of the output stage is blocked (S530) with respect to the failure circuit. In addition, in order to perform a circuit function normally, a differentiation process (S540) is performed to recover a module that performs an original function in a new differentiation region for a failed circuit.

Then, the output of the failed circuit is cut off, and a process of determining whether it is a temporary error or a permanent error through the self-diagnostic test circuit implemented in the circuit (S550) is performed. In this case, the circuit determined to be normal is redundant to perform the function of the originally implemented circuit, and is prevented from performing the function for the permanent failure.

Confirmation of the failed information (S520) If the result of the check is a management area in which the failure occurs, the management area is firstly blocked (S560). The other management module neighboring to the lower implementation unit in which the management area is responsible for the blocked management area replaces this function (S570). If the four management areas continue to fail and there is no management area to replace them, then the system will stop and a hardware replacement process will be required.

FIGS. 6 to 12 are flowcharts for explaining each configuration step of the self-failure recovery method shown in FIG. 5 in detail.

First, FIG. 6 shows a failure detection step for self-recovery indicated by '1' in FIG. In order to detect the failure, it is determined whether the data values of the digital circuit outputs divided by the detailed functions are the same or not (S610). If the output values of the DMR are the same, it means that the failure does not occur. Therefore, it is judged as a normal operation and the DMR value is compared again. If another comparison result is found, the process proceeds to the second step S620 for fault circuit processing.

FIG. 7 illustrates details of the fault location determination step (S520) indicated by '2' in FIG. As described above, one management area is responsible for four operation areas. Further, information on one operation area is simultaneously transmitted to four management areas.

Referring to FIG. 7, if it is determined that a failure has occurred, the location information of the current failure is received to determine where the failure occurred (S710). In step S720, it is determined whether a failure of the digital circuit divided by the detailed function or a failure in the part responsible for the differentiation function is detected. In S720, information received from the four management areas is compared to determine whether they are identical to each other. As a result of the determination, if all pieces of information match, it is determined that a failure has not occurred in the management area, so that it is determined that a failure occurs in the operation area (S730). On the other hand, if all pieces of information do not match, it can be determined that a failure has occurred in the management area (S740).

If the failure occurs in the operation area, the process moves to the operation area process step (S730). If a failure occurs in the management area, the process moves to the management area process step (S740).

FIG. 8 is a detailed circuit diagram of the fault circuit blocking process indicated by '3' in FIG.

First, it is necessary to grasp the accurate positional information on the information of the broken circuit (S810). The failed circuit first goes through a step S820 of interrupting the output (S820), and then proceeds to a failure recovery process (S830) of the failed circuit to determine whether it is a temporary failure or a permanent failure for the implementation circuit.

FIG. 9 illustrates a self-failure recovery for a fault circuit that differentiates a faulty area circuit into a new area for a self-fault repair, as shown in FIG.

First, the malfunction determining and distinguishing unit responsible for the malfunctioning function confirms the malfunctioning precise position information (S910) for the digital circuit divided by the detailed function. Then, a differentiation operation for differentiating the original function of the failed region into the new region of the lower implementation unit is started (S920). Also, when information indicating that a failure has occurred in the operation area is received, a self test operation (S930) is performed to determine whether the failure is temporary or permanent.

FIG. 10 illustrates a result process after the self-failure recovery of the failed circuit (S1010) is performed for the self-failure recovery as indicated by '5th step' in FIG.

When the information of a circuit which is faulty is confirmed, the output is cut off and a self-diagnosis test step S1010 is performed. If it is judged normal after the test, it means that it is a temporary failure. Therefore, a normal operating region is set as a normal circuit (S1020). The operation area newly set as the normal circuit can serve as a redundancy for the failure of the same continuous circuit, so that the self-failure recovery function can be performed more quickly.

If it is determined as a permanent failure as a result of the self-diagnostic test, it is regarded as an abnormal circuit and a blocking operation (S1030) is performed to exclude it from the circuit functioning area.

FIG. 11 shows a case where a failure occurs in the management area for the self-failure recovery.

FIG. 11 shows a failure determination / differentiation unit which is responsible for a differentiation function, not a failure of a digital circuit divided into detailed functions in the self-failure diagnosis method, as indicated by "6th step" in FIG.

First, when a failure occurs in the digital circuit divided by detailed functions, the failure information is transferred to the failure determination / differentiation unit that performs the differentiation function, and the changed state information is transferred to the recovery management unit responsible for the overall management function (S1130).

As described above, in the digital circuit divided into detailed functions, the information of the four neighboring management areas which are responsible for the position information and the differentiation function for differentiating into the new area according to the temporary failure and the permanent failure are reported to the recovery management unit. Then, the recovery management unit determines a management area in which a failure has occurred by a plurality of decision methods (Majority). That is, if the output value of the main differentiated area currently in charge differs from the output value of the other management area, it is determined that a failure occurs in the main management area. If such a failure occurs, the management area in which the failure occurs is replaced (S1120).

FIG. 12 shows a result of processing a result of a change in the role of the management area and successive failures in the self-failure recovery, as indicated by '7 step' in FIG.

First, if it is determined that the value of the management area is different, the management area that is currently in charge is blocked. At this time, since three neighboring management areas perform the same function at the same time, a role is changed to an adjacent management area (S1210).

The order of roles is four in the management area when there are four operation areas. Management area # 1 is mainly responsible for operation area # 1, and functions to manage operation areas # 2, # 3, and # 4 at the same time. Management area # 2 is mainly responsible for operation area # 2, and manages areas # 3, # 4, and # 1 simultaneously. Management area # 3 is mainly responsible for operation area # 3, and manages the operation areas # 4, # 1, and # 2 at the same time. In addition, the management area No. 4 mainly manages the operation area No. 4 and manages the operation areas No. 1, No. 2, and No. 3 at the same time. The role change for the management area failure can be performed in this clockwise direction.

Referring again to FIG. 12, it is determined whether the function of the other management area is normally operated (S1220). If it is determined that the function of the other management area is normal, the management area is classified into the management area and the management area is informed to the recovery management part S1230). If all four management areas fail, a system error (S1240) and a hardware replacement must be performed.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

The present invention can be applied to all programmable electronic circuits because the implemented digital circuit can be divided into functions in detail to locate the position of the fault portion quickly and accurately.

Also, according to the present invention, a faulty circuit is divided into a new area for a faulty circuit, a malfunctioning circuit performs a self-diagnosis process, and if the circuit is found to be a temporary fault, redundancy is generated, It can be directly recovered without going through the process, so that it can be applied to improve the operation reliability of the electronic circuit.

1 is a view conceptually showing the structure of an electronic circuit system according to one aspect of the present invention.

2 is a view conceptually showing a structure of a semiconductor circuit part of an electronic circuit system according to one aspect of the present invention.

3 is a diagram conceptually illustrating a process of dividing a sub module in which a failure occurs in an electronic circuit system according to an embodiment of the present invention.

Figure 4 is a diagram illustrating the placement of an operating block and a differentiating block.

FIG. 5 is a flowchart conceptually illustrating a self-failure recovery method of an electronic circuit system according to another aspect of the present invention.

FIGS. 6 to 12 are flowcharts for explaining each configuration step of the self-failure recovery method shown in FIG. 5 in detail.

Claims (15)

In a programmable electronic circuit system including a semiconductor circuit portion designed with a double modular redundancy (DMR) structure, A failure determination and classification unit for determining whether a failure occurs in a plurality of submodules constituting the semiconductor circuit unit and a position of a submodule in which a failure occurs; And And a recovery management unit for receiving the location of the sub-module in which the failure has occurred from the failure determination and differentiation unit, determining a differentiation area for differentiating the sub-module in which the failure has occurred, and transmitting the determination result to the failure determination and differentiation unit, Wherein the failure determination and division unit divides the sub-module in which the failure has occurred into the differentiation area received from the recovery management unit, Wherein the semiconductor circuit portion includes four intrinsic differentiation regions and four common differentiation regions for each submodule, Wherein the four common division regions are shared by 16 submodules. ≪ RTI ID = 0.0 > 15. < / RTI > In a programmable electronic circuit system including a semiconductor circuit portion designed with a double modular redundancy (DMR) structure, A failure determination and classification unit for determining whether a failure occurs in a plurality of submodules constituting the semiconductor circuit unit and a position of a submodule in which a failure occurs; And And a recovery management unit for receiving the location of the sub-module in which the failure has occurred from the failure determination and differentiation unit, determining a differentiation area for differentiating the sub-module in which the failure has occurred, and transmitting the determination result to the failure determination and differentiation unit, Wherein the failure determination and division unit divides the sub-module in which the failure has occurred into the differentiation area received from the recovery management unit, Wherein the semiconductor circuit portion includes four intrinsic differentiation regions and four common differentiation regions for each submodule, Wherein the four common differentiation regions are shared by 16 submodules, wherein the failure determination and differentiation unit comprises: The management module includes four management modules that commonly manage respective operation modules including 16 submodules, A failure detector for detecting a failure by comparing two outputs of the submodule having the DMR structure and determining a position of the submodule in which a failure occurs when the failure is detected; A self test unit for comparing the output results after applying the same input to the sub module in which the failure occurs and judging the result as a permanent failure if a discrepancy result is repeated; And And a differentiator for differentiating an original pattern of the submodule in which the failure has occurred in the differentiation region received from the failure determination and differentiation unit. 3. The method of claim 2, The current state information of the 16 sub-modules is commonly transmitted to the four management modules, Wherein one of the four management modules determines a failure of the submodules and a position of a submodule in which the failure occurs as a main management module. The method of claim 3, When the current state information of the 16 submodules is commonly transmitted to the four management modules, the management modules transmit the current state information and the address of the current state to the recovery management unit, If the current status information received from the main management module does not match the current status information received from the other management module, the recovery manager determines that a failure has occurred in the main management module, And the new main management module is set as a new main management module. 3. The apparatus of claim 2, wherein the self- The submodules judged to be permanently out of the submodules in which the failure has occurred are permanently shut down and the submodule determined not to be a permanent failure is set again as a normal submodule so that it can be used as a redundancy module Wherein the electronic circuit system has a self-failure recovery function. The information processing apparatus according to claim 1, The sub-module in which the failure has occurred is classified into any one of the four unique differentiation regions available, Wherein the control unit controls the failure determination and differentiation unit to differentiate the sub-module in which the failure has occurred if any of the unique differentiation areas is not available, into any one of the common differentiation areas. Circuit system. 2. The semiconductor device according to claim 1, The sub-module is the minimum unit of failure diagnosis and recovery, Four operation blocks each consisting of four submodules are arranged at element positions of (1, 1), (1, 3), (3, 1) and (3, 3) Five differentiation blocks each consisting of four differentiation regions are arranged at the remaining element positions of the matrix, Wherein the differentiating block disposed at the (2, 2) element position of the matrix operates as the common division region. A method for self-recovery of a programmable electronic circuit system including a semiconductor circuit portion designed with a dual modularity (DMR) structure, Determining whether a failure occurs in a plurality of submodules constituting the semiconductor circuit portion including four distinct division regions and four common division regions for each submodule and four common division regions shared by the sixteen submodules A step of judging whether or not a failure occurs; A failure location determination step of determining a location of a sub module in which a failure occurs if a failure occurs; Determining a differentiation region for differentiating the submodule in which a failure has occurred; And And a differentiating step of dividing the original pattern of the submodule in which the failure has occurred into the determined differentiation area, Determining whether there is redundancy of the module, and if it is determined that there is no redundancy of the module, dividing the sub-module into the unique differentiation region, if the available unique differentiation region does not exist And if it is different from the common differentiation region, differentiates it into the common differentiation region. 9. The method according to claim 8, Detecting a failure by comparing two outputs of the sub-module having a DMR structure; Comparing the output result after applying the same input to the sub module where the failure occurs; And Further comprising a self-test step of determining that the sub-module in which the failure has occurred is a permanent failure if the output result is inconsistent in one or more inputs. 10. The method according to claim 9, Communicating current state information of the 16 sub-modules to the four management modules in common; And Wherein one of the four management modules is a main management module to determine whether the sub-modules are faulty or not, and determining a location of the sub-module where the fault has occurred. 11. The method of claim 10, When the current state information of the 16 submodules is commonly transmitted to the four management modules, the management modules transmit the current state information and the address of the current state to the recovery management module, respectively; Comparing current status information received from the main management module with current status information received from another management module; Determining that a failure has occurred in the main management module if the comparison result does not match; And Further comprising setting another management module among the four management modules as a new main management module. 10. The method of claim 9, wherein the self- Permanently blocking operations of sub-modules determined to be permanent failures among the failed sub-modules; And Further comprising the step of setting the submodule determined not to be a permanent failure as a normal submodule so as to operate as a redundancy module. 9. The method according to claim 8, Wherein the failure diagnosis unit divides the submodule in which the failure has occurred into one of the four distinctive divisional areas, and if all of the unique divisional areas are not available, differentiates the submodule in which the failure has occurred into any one of the common divisional areas And determining the differentiation region so as to make the differentiated region. 9. The semiconductor device according to claim 8, The sub-module is the minimum unit of failure diagnosis and recovery, Four operation blocks each consisting of four submodules are arranged at element positions of (1, 1), (1, 3), (3, 1) and (3, 3) Five differentiation blocks each consisting of four differentiation regions are arranged at the remaining element positions of the matrix, And the differentiating block disposed at the (2, 2) element position of the matrix operates as the common division area. delete

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