KR101028428B1 - Arithmetic operating apparatus and method for performing arithmetic operation - Google Patents

Abstract

The present invention realizes, for example, various combinations of operations in SIMD floating-point multiplication operations and the like with a small number of instruction type codes.

In the register 11 and the calculators 12b and 12e, the arithmetic unit 1 sends one or more unused bits in one instruction to execute an expansion process that is different from the normal processing executed by the one instruction. And a setting unit 20 for setting extended instruction information to be performed on at least one side.

Description

Calculation device and method of operation {ARITHMETIC OPERATING APPARATUS AND METHOD FOR PERFORMING ARITHMETIC OPERATION}

TECHNICAL FIELD This invention relates to the technique suitable for use when performing calculations, such as a complex matrix product operation using a floating-point multiplication operator, for example.

In general, a matrix multiplication operation using a complex number as an element is realized by the following equation (1).

X + Yi ← X + Yi + (A + Bi) * (C + Di)

= X + A * C-B * D + (Y + A * D + B * C) i (1)

When performing this matrix multiplication operation using one floating point multiplication operator, four operations by the following formulas (1-1) to (1-4) are performed. In other words, when performing a complex matrix multiplication operation using one floating point multiplication operator, four instructions must be issued to the operator.

X ← X + A * C (1-1)

Y ← Y + A * D (1-2)

X ← X-B * D (1-3)

Y ← Y + B * C (1-4)

On the other hand, in general, a multiplication operation by the SIMD (Single Instruction stream Multiple Data stream) method, which processes a plurality of data streams with one instruction, is known as a method of efficiently performing a multiplication operation with a smaller number of instructions. . The arithmetic unit employing this SIMD system is provided with a register and two floating point multiplication operators that perform the same operation based on the data (register values) stored in this register. These two floating point multiply operators are commonly called floating point multiply operators (normal operators) and extended floating point multiply operators (extended operators), respectively.

In the normal calculator, the register value in the designated register number of the register first half area is input as the calculation target data, and the register value in the designated register number in the late register region is input as the calculation target data to the expansion calculator. Here, the designated register number of the latter half of the register is a number obtained by adding a predetermined offset to the designated register number of the first half of the register. For example, if the number of register numbers is 128, 64 is set as the predetermined offset.

With this configuration, it is necessary to indicate a register number specifying a register value to be output from the register to the expansion operator by simply indicating a register number specifying the register value to be output from the register to the normal operator in one instruction. It becomes possible. That is, a single instruction can execute arithmetic processing instructions for two arithmetic operators, and arithmetic processing that has conventionally been performed by four instructions can be performed by two instructions, thereby doubling the throughput.

[Patent Document 1] Japanese Unexamined Patent Publication No. 2003-16051

However, a complex matrix multiplication operation performed by four operations (that is, four instructions) according to the above formulas (1-1) to (1-4) is directly applied to the computing device employing the SIMD method as described above. Can not be applied and executed with 2 instructions. This is because of the constraints of registers in which the normal operator uses the front register area and the extended operator uses the late register area as described above, and the constraints on the operation contents that the normal operator and the extended operator perform the same operation as described above. .

One of the objects of the present invention is to realize various combinations of operations in, for example, SIMD floating-point multiplication operations and the like with a small number of instruction type codes.

Moreover, it is not limited to the said objective, It is an effect of the action guide | induced by each structure shown by the best form for implementing the below-mentioned invention, It is another thing of this invention to show the action effect which is not obtained by the prior art. Position can be given as one of the objectives.

The computing device includes a register that stores data to be calculated, and one or more calculators that perform calculations based on the data read from the registers. Receiving one instruction consisting of a plurality of bits, indicative of the data to be read from the register and the type of operation to be performed by the operator, wherein the operator is based on the data indicated by the one instruction; Perform the type operation indicated by the command. Expansion instructions in which the arithmetic unit issues, to at least one of the register and the operator, instructions for executing expansion processing different from the normal processing executed by the one instruction to one or more unused bits in the one instruction. It has a setting unit for setting information.

In addition, in the arithmetic method having the above-described register and arithmetic unit, the arithmetic unit receives one instruction consisting of a plurality of bits instructing the type of data to be read from the register and the arithmetic operation to be executed by the arithmetic unit, The calculator executes the type of operation indicated by the one instruction based on the data indicated by the one instruction. This operation method includes an instruction for executing at least one of the registers and the operator to execute an instruction to perform an expansion process different from the normal processing executed by the one instruction to one or more unused bits in the one instruction. A setting step of setting information.

According to the arithmetic unit and the arithmetic method disclosed above, since one or more unused bits in one instruction can be used to give an instruction to execute an extension process different from the normal process, for example, various operations in SIMD floating point multiplication and the like. The combination can be realized with fewer instruction type codes. Therefore, for example, it is possible to execute complex operations such as complex matrix product operations performed by four instructions by two instructions, thereby doubling the throughput.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described with reference to drawings.

[1] computing equipment

Fig. 1 is a block diagram showing the configuration of an arithmetic device as an embodiment of the present invention. The arithmetic device 1 of the present embodiment shown in Fig. 1 includes an arithmetic unit 10 and a command code issuing unit (setting unit). It has 20 and the generation part 30.

The arithmetic unit 10 has a register 11, two sets of ordinary floating point multiplication operators (normal operators or simply arithmetic operators) 12b, and an extended floating point multiplication arithmetic operator (extended operators or simply arithmetic operators) 12e. In the following description, the "normal floating point multiplication operator" is referred to as a "normal multiplication operator", a "normal operator" or simply an "operator", and the "extended floating point multiplication operator" is referred to as an "extended multiplication operator" and an "extension operator". Or it may be described simply as an "operator."

The register 11 is capable of holding register values (data) designated by 2N register numbers 0 to 2N-1 (N = 64 in this embodiment). This register 11 stores the calculation target data and the calculation results by the calculators 12b and 12e.

In the computing device 1 of the present embodiment, as will be described later, the SIMD system employs / disables a plurality of (two in the present embodiment) data streams in one command by an instruction type code (opcode). It is possible to select the adoption (SIMD / non-SIMD). When the SIMD method is adopted, the area of the register 11 is divided into two areas of the first half (register numbers 0 to N-1) and the second half (register numbers N-1 to 2N-1). Basically, they are normally used by the calculator 12b and the expander 12e, respectively.

In the register 11, six output register numbers, two input register numbers, and an input register write control signal are input from the generation unit 30 to be described later. By the six output register numbers, three register values (data to be multiplied) to be output from the register 11 to each of the calculators 12b and 12e are designated. The two input register numbers designate a storage destination (address of the register 11) in which the result of the calculation by each of the calculators 12b and 12e is to be input and recorded as a register value. The input register write control signal selects and controls whether or not the result of calculation by each of the calculators 12b and 12e is recorded in the register 11.

Here, as an input register number for specifying the storage destination of the operation result by the normal operator 12b, a 7-bit value b_rd [6: 0] is input to the register 11. As three output register numbers that designate three register values (data to be multiplied) to be output from the register 11 to the normal operator 12b, each of 7-bit values b_rs1 [6: 0] and b_rs2 [ 6: 0] and b_rs3 [6: 0]) are input to the register 11.

In addition, a 7-bit value (e_rd [6: 0]) is input to the register 11 as an input register number for designating a storage destination of the calculation result by the expansion operator 12e. As three output register numbers that designate three register values (operation target data) that should be output from the register 11 to the expansion operator 12e, each of 7-bit values (e_rs1 [6: 0], e_rs2 [6: 0], e_rs3 [6: 0]) are input to the register 11.

These 7-bit values (b_rd [6: 0], b_rs1 [6: 0], b_rs2 [6: 0], b_rs3 [6: 0], e_rd [6: 0], e_rs1 [6: 0], e_rs2 [ 6: 0] and e_rs3 [6: 0]), an integer in the range of 0 to 127 is set, and the register number used in the multiplication operation by the calculators 12b and 12e is specified. That is, for each of the arithmetic operators 12b and 12e, four register numbers, i.e., two register numbers for the multiplication operation, a register number for the multiplication operation, and a register number for the operation result storage are specified in the range of 0 to 127. . In addition, the range of register numbers 0 to 63 of the register 11 is called the first half area, and the range of register numbers 64 to 127 of the register 11 is called the second half area.

In the present embodiment, the register value in the register number n (n = 0, 1, 2, ..., 127) is represented by% r [n]. For example, register number n = 0, 1,... , The register values stored in 127 are% r [0],% r [1],... ,% R [127].

These register values% r [0],% r [1],... In% r [127], the value of the register number specified by the instruction is expressed as follows. When four register values of the normal operator 12b are represented by% b1,% b2,% b3, and% bd, respectively, for example, when b_rs1 [6: 0] ← 15,% b1 represents% r [15]. Similarly, if four register values of the expansion operator 12e are represented by% e1,% e2,% e3, and% ed, for example, e_rs1 [6: 0] ← 79,% e1 represents% r [79]. Indicates.

In addition, the above-described input register write control signals are represented by b_we and e_we. The control signal b_we is a 1-bit signal for selecting and controlling whether or not the result of the multiplication calculation by the normal operator 12b is recorded in the register 11, and is set to "1" when recording. When not recording, it is set to "0". Similarly, the control signal e_we is a 1-bit signal for selecting and controlling whether or not the result of the multiplication calculation by the expansion operator 12e is recorded in the register 11, and is set to "1" when recording. Is set to " 0 " when no recording is made.

On the other hand, the arithmetic operators 12b and 12e are three-input and one-output floating-point multiplication operators, respectively, and may also be referred to as operation type codes (simply referred to as "operation codes") included in the instruction set from the generation unit 30 described later. As described later, the operation type can be switched.

In the normal arithmetic operator 12b, three register values (% b1,% b2, and% b3) read out from the register 11 are input as input values b_i1, b_i2, and b_i3, respectively, and an output value b_o which is an operation result. Is output to the register 11 as a register value% bd. Similarly, in the expansion operator 12e, three register values (% e1,% e2, and% e3) read out from the register 11 are input as input values e_i1, e_i2, and e_i3, respectively, and the output value ( e_o) is output to the register 11 as a register value% ed.

That is, in the normal operator 12b, the operation code b_op [1: 0] from the generation unit 30 to be described later and the data (% b1,% b2,% b3) from the register 11 are inputted. Based on these data (% b1,% b2,% b3), a calculation according to the operation code b_op [1: 0] is performed to output the calculation result data% bd. Similarly, the arithmetic operation unit 12e inputs an operation code e_op [1: 0] from the generation unit 30 to be described later, and data (% e1,% e2,% e3) from the register 11. Based on these data (% e1,% e2, and% e3), the calculation according to the operation code e_op [1: 0] is performed to output the calculation result data% ed.

Here, in each of the calculators 12b and 12e of the present embodiment, the calculation contents (operation name) designated by the 2-bit operation codes b_op [1: 0] and e_op [1: 0] are as follows. Four types shown in Table 1.

TABLE 1

The command code issuing unit (setting unit) 20 issues a command code to the calculating unit 10 through the generation unit 30 to be described later, and has a function as a setting unit to be described later.

Here, the command code issued by the command code issuing unit 20 is composed of an instruction type code and four register number instructions, for example, as shown in Table 2 and Table 3 below. The instruction type code is 4 bits of data indicated by opcode [3: 0], and can indicate 16 kinds of instructions. The four register number instructions are composed of 7 bits, respectively, as shown in Figs. 5A, 8A, 11A, 18A, and 22A, respectively, and zero. Any one of the register numbers ˜127 can be indicated.

Table 2 below shows an instruction type code corresponding to a state in which the opcode [3: 2] is set to 00 in the arithmetic unit 1 and the non-SIMD method described later with reference to FIGS. 3 to 5 is employed. The instruction description and the operation contents according to the instruction type code are shown. In this state, the arithmetic unit 10 performs the multiplication operation on the register values in all areas of the register 11 using only the normal arithmetic unit 12b without using the extended arithmetic unit 12e.

Table 3 below shows an instruction type code and a command corresponding to a state in which the opcode [3: 2] is set to 01 in the arithmetic unit 1 and the SIMD method described later with reference to FIGS. 6 to 8 is adopted. The calculation contents of the normal operator 12b / extension operator 12e according to the description and the instruction type code thereof are shown.

In this state, in the calculating section 10, the register value in the designated register number of the first half area of the register 11 is input to the normal calculating section 12b as the calculation target data. In addition, the register value in the designated register number of the latter half area of the register 11 is input to the expansion operator 12e as the calculation target data. Here, the designated register number of the latter half area of the register 11 is a number which added predetermined offset (64 in this embodiment) to the designated register number of the first half area of the register 11. The same applies to the register numbers specifying the storage destinations of the calculation results by the calculators 12b and 12e. For this reason, in the case of adopting the SIMD method, as shown in Fig. 8A, each of the four register number instructions has a 7-bit structure (rd [6: 0], rs1 [6: 0], rs2 [6). : 0] and rs3 [6: 0]), but in each number instruction, 6 bits of the 7 bits (rd [5: 0], rs1 [5: 0], rs2 [5: 0], rs3 [5: 0]) is used, and one bit (rd [6], rs1 [6], rs2 [6], rs3 [6]) becomes unused.

TABLE 2

[Table 3]

The function as the setting unit in the command code issuing unit 20 is a function of setting extended instruction information in one or more unused bits in one instruction (instruction set). This extension instruction information is for executing at least one of the register 11 and the calculators 12b and 12e to execute an instruction for executing an extension process that is different from the normal process executed by the instruction.

As the unused bits, as described above, for example, the most significant bits (rd [6], rs1 [6], rs2 [6) of the register number indicating field, which are unused bits, generated when the SIMD method is adopted in the computing device 1, for example. ], part or all of rs3 [6]) is used.

Moreover, the following two types can be mentioned as extended instruction information using an unused bit.

(a1) For example, as described below with reference to FIGS. 9 to 24, data to be output to each of the calculators 12b and 12e is an area other than the area of the register 11 corresponding to each of the calculators 12b and 12e. Extended instruction information for instructing the register 11 to switch to the data in. According to such extended instruction information, each of the calculators 12b and 12e can perform the operation in a state where the register value of the first half region of the register 11 and the register of the second half region are mixed.

(a2) For example, as described below with reference to FIGS. 20, 22 (b), 23, and 24, instructions for switching the type of operation by each of the calculators 12b and 12e are given to each of the calculators 12b and 12e. Extended instruction information for. According to this extended instruction information, it is possible to switch the types of operations executed by the calculators 12b and 12e independently, so that the different types of calculations can be executed by each of the calculator 12b and the calculator 12e.

The generation unit 30 is an instruction set and issued by the command code issuing unit (setting unit) 20 as described later with reference to FIGS. 4, 7, 7, 10, 17, 21, and 25. From the set (instruction code), an instruction set input to the calculating section 10 is generated.

Here, the command codes issued by the command code issuing unit 20 are opcode [3: 0], rd [6: 0], rs1 [6: 0], rs2 [6: 0], rs3 [6: 0] 32 bits of. In addition, the instruction set input to the calculating section 10 generated by the generating section 30 is b_we, e_we, b_rd [6: 0], b_rs1 [6: 0], b_rs2 [6: 0], b_rs3 [6 : 62 bits of: 0], e_rd [6: 0], e_rs1 [6: 0], e_rs2 [6: 0], e_rs3 [6: 0], b_op [1: 0], and e_op [1: 0]. That is, the 32-bit command code from the instruction code issuing unit 20 is converted into a 62-bit instruction set for input to the calculating unit 10 in the generating unit 30.

At this time, the generation unit 30 will be described later with reference to FIGS. 10, 11 (d), 17, 18 (d), 21, 22 (b), 22 (d), and 25. As described above, an instruction is generated based on the extended instruction information set in the unused bit. That is, the generation unit 30 generates an extension instruction based on the extended instruction information set in the unused bit and the information set in the bits other than the unused bit, and the extended instruction is generated in the registers 11 and the operators 12b and 12e. It also performs the function of outputting as at least one command set. Here, the extension command is for executing an extension process execution instruction indicated by extension instruction information such as the items (a1) and (a2).

[2] basic operations

Here, according to the flowchart shown in FIG. 2, the basic operation (process) of the calculating part 10 in the calculating device 1 shown in FIG. 1 is demonstrated.

In addition, although not shown in FIG. 2, in the arithmetic unit 1, a command code issuing unit 20 issues a command code (including a setting step) before executing a process according to the flowchart shown in FIG. 2. And the generation step by the generation unit 30 are executed.

In the setting step, as described above, the extended instruction information is set in one or more unused bits in the instruction set by the function as the setting unit in the command code issuing unit 20. In addition, in the generation step, the generation unit 30 converts the command code from the command code issuing unit 20 into an instruction set for input to the operation unit 10, at which time the extended instruction information set in the unused bit. Is generated based on.

As described above, the instruction sets b_we, e_we, b_rd, b_rs1, b_rs2, b_rs3, e_rd, e_rs1, e_rs2, e_rs3, b_op, and e_op generated by the generation unit 30 (generation step) are input to the operation unit 10. First, a register read is performed (step S10). In this register reading step, the register values (% r [b_rs1],% r [b_rs2],% r [b_rs3],% r [e_rs1],% r [e_rs2], and% r [e_rs3]) are registers 11. ) Are input to the calculators 12b and 12e as input values b_i1, b_i2, b_i3, e_i1, e_i2 and e_i3, respectively (step S11).

Thereafter, based on the register value read in step S10 (S11), calculation execution by the normal calculator 12b (step S20) and calculation execution by the expansion calculator 12e (step S30) are executed.

In step S20, first, a determination is made as to whether or not the operation code b_op is 00 for specifying the operation content of the operation name fmadd (step S21). When the operation code b_op = 00 (Y root of step S21), an operation that results in b_i1 * b_i2 + b_i3 is executed, and the operation result is output as an output value b_o (step S22), and the process proceeds to step S30. .

If the operation code b_op is not 00 (N root of step S21), it is determined whether or not the operation code b_op is 11 specifying the operation content of the operation name fnmadd (step S23). When the operation code b_op = 11 (Y root of step S23), an operation that becomes -b_i1 * b_i2-b_i3 is executed, and the operation result is output as an output value b_o (step S24), and the process shifts to step S30. do.

If the operation code b_op = 11 is not (N root of step S23), it is determined whether the operation code b_op is 01 for specifying the operation content of the operation name fmsub (step S25). If the operation code b_op = 01 (Y root of step S25), an operation that results in b_i1 * b_i2-b_i3 is executed, and the operation result is output as an output value b_o (step S26), and the processing proceeds to step S30. .

If the operation code b_op is not 01 (N root of step S25), it is determined whether or not the operation code b_op is 10 specifying the operation content of the operation name fnmsub (step S27). When the operation code b_op = 10 (Y root of step S27), an operation that becomes -b_i1 * b_i2 + b_i3 is executed, and the result of the operation is output as an output value b_o (step S28), and the process proceeds to step S30. do. Also, when the operation code b_op = 10 is not (N root of step S27), the processing proceeds to step S30.

Similarly, in step S30, first, a determination is made as to whether or not the operation code e_op is 00 for specifying the operation content of the operation name fmadd (step S31). When the operation code e_op = 00 (Y root of step S31), an operation that results in e_i1 * e_i2 + e_i3 is executed, and the operation result is output as an output value e_o (step S32), and the process proceeds to step S40. .

If the operation code e_op is not 00 (N root of step S31), it is determined whether or not the operation code e_op is 11 specifying the operation content of the operation name fnmadd (step S33). When the operation code e_op = 11 (Y root of step S33), an operation of -e_i1 * e_i2-e_i3 is executed, and the operation result is output as an output value e_o (step S34), and the process proceeds to step S40. do.

If the operation code e_op = 11 is not (N root of step S33), it is determined whether or not the operation code e_op is 01 for specifying the operation content of the operation name fmsub (step S35). If the operation code e_op = 01 (Y root of step S35), an operation of e_i1 * e_i2-e_i3 is executed, and the operation result is output as an output value e_o (step S36), and the process proceeds to step S40. .

If the operation code e_op = 01 is not (N root of step S35), it is judged whether or not the operation code e_op is 10 specifying the operation content of the operation name fnmsub (step S37). If the operation code e_op = 10 (Y root of step S37), an operation of -e_i1 * e_i2 + e_i3 is executed, and the operation result is output as an output value e_o (step S38), and the process proceeds to step S40. do. Also, when the operation code e_op = 10 is not (N root of step S37), the processing proceeds to step S40.

In addition, although FIG. 2 describes to perform the process of step S30 after the process of step S20, in practice, the process of step S20 and the process of step S30 are executed in parallel. In addition, the determination process by step S21, S23, S25, S27 and the determination process by step S31, S33, S35, S37 are not limited to the procedure shown in FIG.

In step S40, the recording of the register 11 of the calculation result by the calculators 12b and 12e is controlled based on the control signals b_we and e_we and the designated register numbers b_rd and e_rd.

That is, it is determined whether the control signal b_we is 1 (step S41). When the control signal b_we = 1 (Y root of step S41), the output value b_o of the calculator 12b is written to the register 11 as a register value% r [b_rd] (step S42).

When the control signal b_we = 0 (N route in step S41) or after the recording process in step S42 is finished, it is determined whether the control signal e_we is 1 (step S43). When the control signal e_we = 1 (Y root of step S43), the output value e_o of the calculator 12e is written to the register 11 as a register value% r [e_rd] (step S44). When the control signal e_we = 0 (N route in step S43) or after the recording process in step S44 is finished, the calculation process of the calculation unit 10 ends.

[3] operation of arithmetic unit when using non-SIMD

As described above with reference to Table 2, when the non-SIMD method is adopted in the computing device 1, the upper two bits of the instruction type code issued by the instruction code issuing unit 20 (opcode [3: 2] ) Is set to 00. 3 to 5, the operation of the arithmetic unit 1 when the non-SIMD method is adopted will be described.

FIG. 3 is a diagram for briefly explaining the operation of the computing unit 10 in the computing device 1 shown in FIG. 1 when non-SIMD is employed. FIG. 4 is a diagram for explaining the operation of the instruction code issuing unit 20 and the generating unit 30 in the arithmetic unit 1 shown in FIG. 1 when employing a non-SIMD. 5 (a) to 5 (d) designate an instruction code, an operation code, a register write signal, and a register number in the arithmetic unit 1 shown in FIG. 1 when non-SIMD is employed, respectively (only the most significant bit). Is a diagram specifically illustrating.

As shown in FIG. 3, when the non-SIMD method is adopted, the calculating unit 10 of the computing device 1 uses the normal calculator 12b instead of the extended calculator 12e to perform the registration of the register 11. A multiplication operation is performed on the register values in all areas. That is, the normal operation unit 12b operates in accordance with the instruction type code opcode [1: 0] and the input value from the register 11, and calculates the operation result of the normal operation unit 12b of the control signal b_we. Write to register 11 according to the value.

At this time, as shown in Figs. 4 and 5 (c), the control signal e_we is always set to 0, and the calculation result of the expansion operator 12e is not recorded in the register 11. In addition, four register number instructions (rd [6: 0], rs1 [6: 0], rs2 [6: 0], and rs3 [6: 0]) issued by the instruction code issuing unit 20 are shown in FIG. As shown in (a), seven bits are used in total, and four register values are indicated in all areas of the register 11.

When employing non-SIMD, the instruction code (opcode [3: 0]) issued by the instruction code issuing unit 20 and four register number instructions (rd [6: 0], rs1 [6: 0], rs2 [ 6: 0] and rs3 [6: 0]) are converted in the generation unit 30 as shown in FIG. 4, and the instruction set b_we, e_we, b_rd [6: 0], b_rs1 [6: 0], b_rs2 [6: 0], b_rs3 [6: 0], e_rd [6: 0], e_rs1 [6: 0], e_rs2 [6: 0], e_rs3 [6: 0], b_op [1: 0 ], e_op [1: 0]).

4 and 5 (b), as the operation code b_op [1: 0] for the normal operator 12b, the lower two bits of the instruction type code included in the instruction code (opcode) [1: 0]) is used. At this time, as shown in Figs. 4 and 5 (c), 1 is set as the register write control signal b_we for the normal operator 12b, and the result of the operation by the normal operator 12b is registered in the register 11. ) Is recorded.

On the other hand, as shown in FIG. 4 and FIG. 5 (b), 00 is fixedly input as the operation code e_op [1: 0] for the expansion operator 12e. At this time, as shown in Figs. 4 and 5 (c), 0 is set as the register write control signal b_we for the extension operator 12b, and the result of the calculation by the extension operator 12b is stored in the register 11. Do not write).

4 and 5 (d), 7 bits (rd [6: 0], rs1 [6: 0], rs2 [6: 0] of four register number instructions included in the instruction code. , rs3 [6: 0]) is input as a register number instruction (b_rd [6: 0], b_rs1 [6: 0], b_rs2 [6: 0], b_rs3 [6: 0]) for the normal operator 12b. . On the other hand, as the register number instruction (e_rd [6: 0], e_rs1 [6: 0], e_rs2 [6: 0], e_rs3 [6: 0]) for the expansion operator 12e, Figs. 4 and 5 (d). As shown in the drawing, all zeros are input.

Next, a specific operation example when employing a non-SIMD, for example, a case where the calculation of fnmsub (% f80,% f10,% f20,% f40) is performed will be described.

The operation content is

% F [80] ←-% f [10] *% f [20] +% f [40]

It is shown as.

In this case, the instruction type code (opcode [3: 0]) and the register number instruction (rd [6: 0], rs1 [6: 0], rs2 [6: 0], and rs3 specified by the instruction code shown in Table 4 below. [6: 0]) is the value of the input signal for the normal operator 12b shown in Table 5 below, that is, the operation code b_op [1: 0] and the register number instruction b_rd [6: 0], b_rs1 [6: 0], b_rs2 [6: 0], b_rs3 [6: 0]) are inputted after being converted. Operation code (e_op [1: 0]) and register number instruction (e_rd [6: 0], e_rs1 [6: 0], e_rs2 [6: 0], e_rs3 [6: 0]) for the extended arithmetic unit 12e. As a value of 0, 0 is input as shown in Table 5 below. 1 is input as the register write control signal b_we for the normal operator 12b, and the operation result of the normal operator 12b is written to the register 11 as a register value (% r [80]). 0 is input as the value of the register control write signal e_we for the expansion operator 12e.

[Table 4]

TABLE 5

[4] operation of arithmetic unit when using SIMD

As described above with reference to Table 3, when the SIMD method is adopted in the computing device 1, the upper two bits of the instruction type code issued by the instruction code issuing unit 20 (opcode [3: 2]) 01 is set. 6-8, the operation | movement of the arithmetic unit 1 when the SIMD system is employ | adopted is demonstrated.

FIG. 6 is a diagram for briefly explaining the operation of the computing unit 10 in the computing device 1 shown in FIG. 1 when employing the SIMD. FIG. 7 is a view for explaining the operation of the instruction code issuing unit 20 and the generating unit 30 in the arithmetic unit 1 shown in FIG. 1 when employing the SIMD. 8 (a) to 8 (d) specifically show the instruction code, the operation code, the register write signal, and the register number designation (only the most significant bit) in the arithmetic unit 1 shown in FIG. 1 when employing the SIMD. It is a figure shown.

As shown in FIG. 6, in the case where the SIMD is employed, in the computing unit 10 of the computing device 1, the register value in the designated register number of the first half area of the register 11 is stored in the normal calculator 12b. It is input as calculation target data. In addition, the register value in the designated register number of the latter half area of the register 11 is input to the expansion operator 12e as the calculation target data. Here, the designated register number for the extension operator 12e is a number obtained by adding a predetermined offset N (64 in the present embodiment) to the designated register number for the ordinary operator 12b. That is, in the normal operator 12b and the extended operator 12e, the same type of calculation according to the instruction type code opcode [1: 0] is executed for different input values (register values). The operation result by the normal operator 12b and the operation result by the expansion operator 12e are recorded in the first half region and the second half region of the register 11, respectively.

At this time, in the four register number instructions (rd [6: 0], rs1 [6: 0], rs2 [6: 0], rs3 [6: 0]) issued by the instruction code issuing unit 20, As shown in Fig. 8 (a), the lower six bits (rd [5: 0], rs1 [5: 0], rs2 [5: 0], rs3 [5: 0]) of all seven bits are used. . By such a set of instruction codes, the register number for the normal operator 12b and the register number for the expansion operator 12e are simultaneously indicated. Therefore, when the SIMD method is adopted, as shown in Fig. 8A, the most significant bits rd [6], rs1 [6], rs2 [6], and rs3 [6] are not used.

When employing the SIMD, the instruction code (opcode [3: 0]) issued by the instruction code issuing unit 20 and four register number instructions (rd [6: 0], rs1 [6: 0], rs2 [6) : 0] and rs3 [6: 0]) are converted in the generation unit 30 as shown in FIG. 7 to generate the instruction sets b_we, e_we, b_rd [6: 0], b_rs1 [6: 0]. ], b_rs2 [6: 0], b_rs3 [6: 0], e_rd [6: 0], e_rs1 [6: 0], e_rs2 [6: 0], e_rs3 [6: 0], b_op [1: 0] , e_op [1: 0]) is input to the calculation unit 10.

As shown in Figs. 7 and 8 (b), the operation codes b_op [1: 0] for the normal operator 12b and the operation codes e_op [1: 0] for the extended operator 12e are shown. The value (opcode [1: 0]) of the lower two bits of the instruction type code included in the instruction code is used. Normally, the same operation code is input to the arithmetic operator 12b and the extended arithmetic operator 12e, and these arithmetic operators 12b and 12e perform the same kind of calculation.

At this time, as shown in FIG. 7 and FIG. 8C, as the register write control signal b_we for the normal operator 12b and the register write control signal e_we for the expansion operator 12e, a fixed value. 1 is set. As a result, the result of calculation by the normal operator 12b and the extended operator 12e is always recorded in the first half region and the second half region of the register 11, respectively.

In addition, as shown in Fig. 7, the lower six bits (rd [5: 0], rs1 [5: 0], rs2 [5: 0], rs3 [5 :) of the four register number instructions included in the instruction code. 0]) is input as the register number instructions b_rd [5: 0], b_rs1 [5: 0], b_rs2 [5: 0], and b_rs3 [5: 0] for the normal operator 12b. At the same time, the same rd [5: 0], rs1 [5: 0], rs2 [5: 0], rs3 [5: 0] register register instructions (e_rd [5: 0], e_rs1 [ 5: 0], e_rs2 [5: 0], e_rs3 [5: 0]).

As shown in Figs. 7 and 8 (d), the most significant bits b_rd [6], b_rs1 [6], b_rs2 [6], and b_rs3 [6] in the register number instruction for the normal operator 12b are shown. The fixed value 0 is set, and the fixed value 1 is set in the most significant bits e_rd [6], e_rs1 [6], e_rs2 [6], and e_rs3 [6] of the register number instruction for the expansion operator 12e. As a result, the register value of the first half area (register numbers 0 to 63) of the register 11 is used in the normal operator 12b. In the extended arithmetic operator 12e, the register value of the register number obtained by adding 64 to the register number for the arithmetic operator 12b, that is, the register value of the second half region (register numbers 64 to 127) of the register 11 is used.

Next, the specific operation example at the time of employ | adopting SIMD, for example, the case where calculation of simd-fnmsub% f40,% f10,% f20,% f30 is performed is demonstrated.

In this case, the arithmetic units 12b and 12e of the arithmetic unit 10 execute two arithmetic operations as described below.

Calculation content of the ordinary calculator 12b:% r [40] ←-% r [10] *% r [20] +% r [30]

Calculation contents of the expansion operator 12e:% r [104] ←-% r [74] *% r [84] +% r [94]

In this case, the instruction type code (opcode [3: 0]) and the register number instruction (rd [6: 0], rs1 [6: 0], rs2 [6: 0], and rs3 specified by the instruction code shown in Table 6 below. [6: 0]) is converted into the values of the input signals for the calculators 12b and 12e shown in Table 7 below and input. That is, as the register number instruction for the normal operator 12b and the register number instruction of the extended operator 12e, the same values (rd [5: 0], rs1 [5: 0], rs2 [5: 0] that are equal to the lower 6 bits. , rs3 [5: 0]) is input, and fixed values 0 and 1 are input to the most significant bit, respectively. The same operation code 10 is input as the operation code b_op [1: 0] for the normal operator 12b and the operation code e_op [1: 0] for the extended operator 12e. As a result, since the same operation code and the four input values from the register 11 are input to the normal operator 12b and the extended operator 12e, respectively, in the normal operator 12b and the extended operator 12e, The same kind of calculation is performed for different input values, respectively. Since all 1s are set as the register write control signals b_we and e_we, the calculation result by the normal operator 12b is recorded as the register value% r [40] in the first half area of the register 11. Similarly, the result of the calculation by the expansion operator 12e is recorded as the register value% r [104] in the second half area of the register 11.

TABLE 6

TABLE 7

[5] Operation of arithmetic unit when employing first unused bit usage form

FIG. 9 is a diagram for briefly explaining the operation of the calculation unit 10 in the arithmetic unit 1 shown in FIG. 1 when the first unused bit usage mode is adopted. FIG. 10 is a diagram for explaining the operation of the instruction code issuing unit (setting unit) 20 and the generating unit 30 in the arithmetic unit 1 shown in FIG. 1 when the first unused bit use form is adopted. . 11 (a) to 11 (d) designate command codes, arithmetic codes, register write signals, and register numbers in the arithmetic unit 1 shown in FIG. 1 when employing the first unused bit use form, respectively. It is a figure which shows (most significant bit only) concretely. 12-15 is a figure which shows the specific example of the calculation combination by the calculation part 10 in the arithmetic unit 1 shown in FIG. 1 at the time of employ | adopting the 1st unused bit utilization form.

When the SIMD method is adopted, the normal operator 12b having the input value of the first half area of the register 11 and the extended operator 12e having the input value of the second half area of the register 11 are the same. Simultaneous operation is performed simultaneously. The calculation results by the calculators 12b and 12e are recorded in the first half region and the second half region of the register 11, respectively. Therefore, in the above-described SIMD system, it is impossible to perform a mixed operation in which one of the calculators 12b or 12e uses the value of the first half region and the second half region of the register 11 as input values.

In the embodiments described in this section, the four instruction sets (simd-fmadd, simd-fmsub, simd-fnmsub, simd-fnmadd) described above have four instruction sets (cross-fmadd1, cross-fmadd2, and cross-fmadd3). cross-fmadd4) (see Fig. 11 (a)) is further added. These instruction sets (cross-fmadd1, ..., cross-fmadd4) are expanded by setting three input values to the normal operator 12b as the values in the latter half region of the register 11, as shown in the left example of FIG. It is an instruction to switch the three input values to the calculator 12e to be the values of the first half area of the register 11.

That is, by using these instructions, the value of the first half region of the register 11 and the value of the second half region of the register 11 are crossed and input to the normal operator 12b and the expansion operator 12e, respectively. At this time, it is possible to perform different kinds of calculations in the normal operator 12b and the extended operator 12e. Also in these instruction sets (cross-fmadd1, ..., cross-fmadd4), each register number instruction (rd [6: 0], rs1 [6: 0], rs2 [6: 0) is the same as that of the SIMD type instruction code. ], among the 7 bits of rs3 [6: 0]), the lower 6 bits (rd [5: 0], rs1 [5: 0], rs2 [5: 0], rs3 [5: 0]) are used. The most significant bits (rd [6], rs1 [6], rs2 [6], rs3 [6]) are not used.

In the embodiment (first unused bit usage form) described below, the unused bits rd [6], rs1 [6], rs2 [6], in the instruction set cross-fmadd1, ..., cross-fmadd4. Two of rs3 [6]), specifically rs1 [6] and rs2 [6], are used. The extended instruction information is set to these two unused bits rs1 [6] and rs2 [6] by the function as the setting unit in the instruction code issuing unit 20. This extended instruction information is different from the normal processing by the instruction sets (cross-fmadd1, ..., cross-fmadd4) not using rs1 [6] and rs2 [6] (for example, the calculations in Figs. 12 to 15). Instruction of execution) is given to the register 11 and the calculators 12b and 12e. 10 and 11, the generation unit 30, based on the extended instruction information set in the unused bit and the information set in the bits other than the unused bit, the generator 11 and the calculator 12b. , 12e) generates and outputs an extension command for instructing execution of the extension processing.

As a result, as shown in the right example of FIG. 9, in one calculator 12b or 12e, a calculation in which the value of the first half region and the second half region of the register 11 are input values can be realized. have. In particular, the instruction to execute the expansion process using the unused bits rs1 [6] and rs2 [6] registers the two input values to be subjected to multiplication in each of the calculators 12b and 12e, respectively. It becomes possible to input from the first half region and the second half region of 11). Therefore, it is possible to execute a complex matrix product operation performed by four operations (that is, four instructions) according to the above formulas (1-1) to (1-4) in two instructions, as described later. .

When adopting this first unused bit usage form (i.e., employing processing by the instruction set (cross-fmadd1, ..., cross-fmadd4)), the instruction type code issued by the instruction code issuing unit 20 11 is set in the upper two bits (opcode [3: 2]). Hereinafter, with reference to FIGS. 10-15, the operation | movement of the arithmetic unit 1 in the case of employing this 1st unused bit utilization form is demonstrated.

When employing the first unused bit usage form, the instruction code (opcode [3: 0]) issued by the instruction code issuing unit 20 and four register number instructions (rd [6: 0], rs1 [6: 0) ], rs2 [6: 0], rs3 [6: 0]) are converted in the generation unit 30 as shown in FIG. 10, and the instruction sets b_we, e_we, b_rd [6: 0], b_rs1 [6: 0], b_rs2 [6: 0], b_rs3 [6: 0], e_rd [6: 0], e_rs1 [6: 0], e_rs2 [6: 0], e_rs3 [6: 0], b_op [1: 0] and e_op [1: 0]) are input to the calculation unit 10.

Where cross-fmadd1,... In cross-fmadd4, as shown in FIG. 10, FIG. 11 (b) and Table 8 below, based on the lower two bits of the instruction type code included in the instruction code (opcode [1: 0]), The operation code b_op [1: 0] for the normal operator 12b and the operation code e_op [1: 0] for the extended operator 12e are generated, respectively. Different from the case of the SIMD system described above, the type of the calculation executed in the normal operator 12b and the extended operator 12e is independently controlled and switched. As a result, the normal arithmetic operator 12b and the extended arithmetic operator 12e can perform the same kind of calculation or the different kind of calculation.

[Table 8]

At this time, as shown in Figs. 10 and 11 (c), as the register write control signal b_we for the normal operator 12b and the register write control signal e_we for the expansion operator 12e, fixed values are shown. 1 is set. As a result, the result of calculation by the normal operator 12b and the extended operator 12e is always recorded in the first half region and the second half region of the register 11, respectively.

As shown in Fig. 10, the lower six bits (rd [5: 0], rs1 [5: 0], rs2 [5: 0], rs3 [5 :) of the four register number instructions included in the instruction code. 0]) is input as the register number instructions b_rd [5: 0], b_rs1 [5: 0], b_rs2 [5: 0], and b_rs3 [5: 0] for the normal operator 12b. At the same time, the same rd [5: 0], rs1 [5: 0], rs2 [5: 0], rs3 [5: 0] register register instructions (e_rd [5: 0], e_rs1 [ 5: 0], e_rs2 [5: 0], e_rs3 [5: 0]).

10, 11 (d) and Table 9 below, the fixed value 0 is set in the most significant bits b_rd [6] and b_rs3 [6] of the register number instruction for the normal operator 12b. A fixed value 1 is set in the most significant bits e_rd [6] and e_rs3 [6] of the register number instruction for the expansion operator 12e. On the other hand, the most significant bits (b_rs1 [6], b_rs2 [6]) of the register number instruction for the normal operator 12b and the most significant bits (e_rs1 [6], e_rs2 [6]) of the register number instruction for the extended operator 12e. The calculated and generated values are set based on the instruction type code (opcode [1: 0]) and the values (extended instruction information) of the most significant bits (rs1 [6] and rs2 [6]) of the register number instruction. The value is calculated based on the values of the most significant bits (rs1 [6], rs2 [6]) of the register number instruction, as shown in Figs. 10, 11 (d) and Table 9 below. do. As a result, the two input values to be subjected to the multiplication in each of the calculators 12b and 12e can be input from the first half region and the second half region of the register 11, respectively. That is, the value from the register 11 to each operator 12b, 12e corresponds to each operator 12b, 12e by the extended instruction information set in the unused bits rs1 [6], rs2 [6]. Instructions for switching to values in areas other than the area of the register 11 are given to the register 11. In addition, ^"~ X" represents an inverted value of X.

TABLE 9

Next, a specific operation example when employing the first unused bit usage mode, for example, a case where the calculation of cross-fmadd1% f30,% f10,% f20, and% f30 is performed will be described.

In this case, the arithmetic units 12b and 12e of the arithmetic unit 10 execute two arithmetic operations as described below.

Calculation content of the ordinary calculator 12b:% r [30] ←% r [10] *% r [20] +% r [30]

Calculation contents of the expansion operator 12e:% r [94] ←% r [10] *% r [84] +% r [94]

These two operations correspond to the following complex operations when the value of the real part in the first half region of the register 11 and the value of the imaginary part in the second half region of the register 11 are maintained.

X ← X + A * C (1-1)

Y ← Y + A * D (1-2)

In this case, the instruction type code (opcode [3: 0]) and the register number instruction (rd [6: 0], rs1 [6: 0], rs2 [6: 0], and rs3 specified by the instruction code shown in Table 10 below [6: 0]) is converted into the values of the input signals for the calculators 12b and 12e shown in Table 11 below and input. That is, as shown in Table 10 below, 1100 is set as the command type code opcode [3: 0] by the command code issuing unit 20, and the function as the setting unit of the command code issuing unit 20 is set. 0 and 0 are set in the unused bits rs1 [6] and rs2 [6] (see the upper left example in FIG. 12 described later). According to these values, the generation unit 30 uses the most significant bits b_rd [6] and b_rs1 [6 of the register number instruction for the ordinary operator 12b based on the equations shown in Fig. 11 (d) and Table 9. ], b_rs2 [6], b_rs3 [6]), and 0, 0, 0, 0 are calculated and set (refer Table 11 below). Similarly, 1, 0, 1, 1 are calculated and calculated as the most significant bits (e_rd [6], e_rs1 [6], e_rs2 [6], e_rs3 [6]) of the register number instruction for the extension operator 12e. Is set (see Table 11 below). In addition, in the normal operator 12b and the extended operator 12e, operation codes 00 and 00 determined by the instruction type code opcode [1: 0], as shown in Fig. 11B and Table 8 above, are assigned. Each is input. Therefore, in this specific example, the normal operator 12b and the extended operator 12e perform the same kind of operation fmadd. In addition, the same values (rd [5: 0], rs1 [5: 0], rs2 [5: 0] in the lower 6 bits of the register number instruction for the normal operator 12b and the register number instruction of the extended operator 12e. , rs3 [5: 0]) is input.

Accordingly, as in the upper left example of FIG. 12, the normal operator 12b uses the most significant bits b_rs1 [6], b_rs2 [6], and b_rs3 [6] = 0, 0, 0 selected in the register number indication. Three values A (% r [rs1] =% r [10]), C (% r [rs2] =% r [20]) from the region, and X (% r [rs3] =% r [30]). A calculation is performed based on the above formula (1-1) as the input value. In addition, as shown in the upper left example of FIG. 12, the extended arithmetic unit 12e includes the register first half area selected by the most significant bits e_rs1 [6], e_rs2 [6], e_rs3 [6] = 0, 1, 1 of the register number indication. One value A (% r [rs1] =% r [10]) from and two values D (% r [N + rs2] =% r [84]) from the late register region, and Y (% r [N + rs3] =% r [94]) is used as an input value, and an operation based on Equation (1-2) is performed. Therefore, the arithmetic result by the same kind of calculation using the different input values is output from the normal operator 12b and the extended operator 12e. In addition, a fixed value 1 is set in the register write control signal b_we for the normal operator 12b and the register write signal for the extended operator 12e. For this reason, the operation result by the normal operator 12b is recorded as a register value (% r [rd] =% r [30]) in the first half area of the register 11. Similarly, the result of the calculation by the expansion operator 12e is recorded as a register value (% r [N + rd] =% r [94]) in the latter region of the register 11. That is, two kinds of operations according to the above formulas (1-1) and (1-2) can be executed by one instruction. Similarly, the above formulas (1-3) and (1-4) can also be executed by one instruction. Therefore, the complex arithmetic operation conventionally executed by four instructions can be executed by two instructions.

TABLE 10

TABLE 11

As a specific operation example described above, the case where 1100 is set in the instruction type code opcode [3: 0] and 0 and 0 are set in the unused bits rs1 [6] and rs2 [6] has been described. However, when employing the first unused bit use form, 15 kinds of arithmetic combinations can be realized. 16 kinds of combinations of operations by the calculation unit 10 will be described with reference to FIGS. 12 to 15.

Fig. 12 shows four types of combinations of operations when the instruction type code opcode [3: 0] = 1100. At this time, the arithmetic operators 12b and 12e perform the same kind of arithmetic operation fmadd.

At this time, if the unused bit (most significant bit) (rs1 [6], rs2 [6]) is 0 or 0, the most significant bit b_rs1 [6], b_rs2 [6], b_rs3 [6] = 0, 0 in the register number indication. , 0, and most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 0, 1, 1 of the register number instruction. Therefore, as in the upper left example of FIG. 12, the normal operator 12b uses three values (% r [rs1],% r [rs2], and% r [rs3]) from the first register area as input values. An operation (fmadd) is performed. In addition, the expansion operator 12e inputs one value (% r [rs1]) from the first register area and two values (% r [N + rs2] and% r [N + rs3]) from the late register area. An operation (fmadd) is performed with the value.

If the unused bit (highest bit) (rs1 [6], rs2 [6]) is 0, 1, the most significant bits b_rs1 [6], b_rs2 [6], b_rs3 [6] = 0, 1, 0, Further, the most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 0, 0, 1 of the register number instruction. Therefore, as in the lower left example of FIG. 12, the normal operator 12b has two values (% r [rs1],% r [rs3]) from the first register area and one value (%) from the late register area. An operation (fmadd) is performed using r [N + rs2]) as an input value. In addition, the expansion operator 12e inputs two values (% r [rs1],% r [rs2]) from the first register area and one value (% r [N + rs3]) from the late register area. The operation (fmadd) is performed.

If the unused bit (highest bit) (rs1 [6], rs2 [6]) is 1, 0, the most significant bits b_rs1 [6], b_rs2 [6], b_rs3 [6] = 1, 0, 0, Further, the most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 1, 1, 1 of the register number instruction. Thus, as in the upper right example of FIG. 12, the normal operator 12b has two values (% r [rs2],% r [rs3]) from the first register area and one value (%) from the late register area. An operation (fmadd) is performed using r [N + rs1]) as an input value. In addition, the expansion operator 12e performs an operation (fmadd) using three values (% r [N + rs1],% r [N + rs2], and% r [N + rs3]) from the second half of the register as input values. .

If the unused bit (most significant bit) (rs1 [6], rs2 [6]) is 1, 1, the most significant bits b_rs1 [6], b_rs2 [6], b_rs3 [6] = 1, 1, 0, Further, the most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 1, 0, 1 of the register number indication. Accordingly, as in the lower right example of FIG. 12, the normal operator 12b includes one value (% r [rs3]) from the first register area and two values (% r [N + rs1], The operation (fmadd) is performed using% r [N + rs2]) as an input value. In addition, the expansion operator 12e inputs one value (% r [rs2]) from the first register area and two values (% r [N + rs1] and% r [N + rs3]) from the late register area. An operation (fmadd) is performed with the value.

Fig. 13 shows four types of combinations of operations when the instruction type code opcode [3: 0] = 1101. At this time, the normal operator 12b executes the operation fnmsub, and the expansion operator 12e executes the operation fmadd.

At this time, if the unused bit (highest bit) (rs1 [6], rs2 [6]) is 0 or 0, the most significant bits b_rs1 [6], b_rs2 [6], b_rs3 [6] = 1, 1, 0, and most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 1, 0, 1 of the register number instruction. Therefore, as in the upper left example of FIG. 13, the normal operator 12b includes one value (% r [rs3]) from the first register region and two values (% r [N + rs1], The calculation (fnmsub) is performed using% r [N + rs2]) as an input value. In addition, the expansion operator 12e inputs one value (% r [rs2]) from the first register area and two values (% r [N + rs1] and% r [N + rs3]) from the late register area. An operation (fmadd) is performed with the value.

If the unused bit (highest bit) (rs1 [6], rs2 [6]) is 0, 1, the most significant bits b_rs1 [6], b_rs2 [6], b_rs3 [6] = 1, 0, 0, Further, the most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 1, 1, 1 of the register number instruction. Therefore, as in the lower left example of FIG. 13, the normal operator 12b has two values (% r [rs2],% r [rs3]) from the first half register area and one value (%) from the late register area. Arithmetic (fnmsub) is performed with r [N + rs1]) as the input value. In addition, the expansion operator 12e performs an operation (fmadd) using three values (% r [N + rs1],% r [N + rs2], and% r [N + rs3]) from the second half of the register as input values. .

If the unused bit (highest bit) (rs1 [6], rs2 [6]) is 1, 0, the most significant bits b_rs1 [6], b_rs2 [6], b_rs3 [6] = 0, 1, 0, Further, the most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 0, 0, 1 of the register number instruction. Therefore, as in the upper right example of FIG. 13, the normal operator 12b has two values (% r [rs1],% r [rs3]) from the first register area and one value (%) from the late register area. Arithmetic (fnmsub) is performed using r [N + rs2]) as an input value. In addition, the expansion operator 12e inputs two values (% r [rs1],% r [rs2]) from the first register area and one value (% r [N + rs3]) from the late register area. The operation (fmadd) is performed.

If the unused bit (highest bit) (rs1 [6], rs2 [6]) is 1, 1, the most significant bits b_rs1 [6], b_rs2 [6], b_rs3 [6] = 0, 0, 0, Further, the most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 0, 1, 1 of the register number instruction. Therefore, as in the upper and lower example of FIG. 13, the normal operator 12b uses three values (% r [rs1],% r [rs2], and% r [rs3]) from the register front area as input values. The operation fnmsub is performed. In addition, the expansion operator 12e inputs one value (% r [rs1]) from the first register area and two values (% r [N + rs2] and% r [N + rs3]) from the late register area. An operation (fmadd) is performed with the value.

Fig. 14 shows four types of combinations of operations when the instruction type code opcode [3: 0] = 1110. At this time, the normal operator 12b executes the operation fmadd, and the expansion operator 12e executes the operation fnmsub.

At this time, if the unused bit (most significant bit) (rs1 [6], rs2 [6]) is 0 or 0, the most significant bit b_rs1 [6], b_rs2 [6], b_rs3 [6] = 1, 1 of the register number indication , 0, and most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 1, 0, 1 of the register number instruction. Therefore, as in the upper left example of FIG. 14, the normal operator 12b includes one value (% r [rs3]) from the first register region and two values (% r [N + rs1], The operation (fmadd) is performed using% r [N + rs2]) as an input value. In addition, the expansion operator 12e inputs one value (% r [rs2]) from the first register area and two values (% r [N + rs1] and% r [N + rs3]) from the late register area. An operation (fnmsub) is performed with the value.

If the unused bit (highest bit) (rs1 [6], rs2 [6]) is 0, 1, the most significant bits b_rs1 [6], b_rs2 [6], b_rs3 [6] = 1, 0, 0, Further, the most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 1, 1, 1 of the register number instruction. Thus, as in the lower left example of FIG. 14, the normal operator 12b has two values (% r [rs2]),% r [rs3] from the first half register area, and one value from the second half area register. The operation (fmadd) is performed using% r [N + rs1]) as an input value. In addition, the expansion operator 12e performs calculation (fnmsub) using three values (% r [N + rs1],% r [N + rs2], and% r [N + rs3]) from the second half of the register as input values. .

If the unused bit (highest bit) (rs1 [6], rs2 [6]) is 1, 0, the most significant bits b_rs1 [6], b_rs2 [6], b_rs3 [6] = 0, 1, 0, Further, the most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 0, 0, 1 of the register number instruction. Therefore, as in the upper right example of FIG. 14, the normal operator 12b has two values (% r [rs1],% r [rs3]) from the first register area and one value (%) from the late register area. An operation (fmadd) is performed using r [N + rs2]) as an input value. In addition, the expansion operator 12e inputs two values (% r [rs1],% r [rs2]) from the first register area and one value (% r [N + rs3]) from the late register area. The operation fnmsub is performed.

If the unused bit (highest bit) (rs1 [6], rs2 [6]) is 1, 1, the most significant bits b_rs1 [6], b_rs2 [6], b_rs3 [6] = 0, 0, 0, Further, the most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 0, 1, 1 of the register number instruction. Therefore, as in the lower right example of FIG. 14, the normal operator 12b uses three values (% r [rs1],% r [rs2], and% r [rs3]) from the register front region as input values. An operation (fmadd) is performed. In addition, the expansion operator 12e inputs one value (% r [rs1]) from the first register area and two values (% r [N + rs2] and% r [N + rs3]) from the late register area. An operation (fnmsub) is performed with the value.

Fig. 15 shows four types of combinations of operations when the instruction type code opcode [3: 0] = 1111. At this time, the arithmetic units 12b and 12e perform the same type of operation fnmsub.

At this time, if the unused bit (most significant bit) (rs1 [6], rs2 [6]) is 0 or 0, the most significant bit b_rs1 [6], b_rs2 [6], b_rs3 [6] = 1, 0 in the register number indication. , 0, and most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 1, 1, 1 of the register number indication. Therefore, as in the upper left example of FIG. 15, the normal operator 12b has two values (% r [rs2]),% r [rs3] from the first half register area, and one value from the second half area register. The calculation (fnmsub) is performed using% r [N + rs1]) as an input value. In addition, the expansion operator 12e performs calculation (fnmsub) using three values (% r [N + rs1],% r [N + rs2], and% r [N + rs3]) from the second half of the register as input values. .

If the unused bit (highest bit) (rs1 [6], rs2 [6]) is 0, 1, the most significant bits b_rs1 [6], b_rs2 [6], b_rs3 [6] = 1, 1, 0, Further, the most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 1, 0, 1 of the register number indication. Therefore, as in the lower left example of FIG. 15, the normal operator 12b includes one value (% r [rs3]) from the first register area and two values (% r [N + rs1], The calculation (fnmsub) is performed using% r [N + rs2]) as an input value. In addition, the expansion operator 12e inputs one value (% r [rs2]) from the first register area and two values (% r [N + rs1] and% r [N + rs3]) from the late register area. An operation (fnmsub) is performed with the value.

If the unused bit (highest bit) (rs1 [6], rs2 [6]) is 1, 0, the most significant bits b_rs1 [6], b_rs2 [6], b_rs3 [6] = 0, 0, 0, Further, the most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 0, 1, 1 of the register number instruction. Therefore, as in the upper right example of FIG. 15, the normal operator 12b uses three values (% r [rs1],% r [rs2], and% r [rs3]) from the register front area as input values. The operation fnmsub is performed. In addition, the expansion operator 12e inputs one value (% r [rs1]) from the first register area and two values (% r [N + rs2] and% r [N + rs3]) from the late register area. An operation (fnmsub) is performed with the value.

If the unused bit (highest bit) (rs1 [6], rs2 [6]) is 1, 1, the most significant bits b_rs1 [6], b_rs2 [6], b_rs3 [6] = 0, 1, 0, Further, the most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 0, 0, 1 of the register number instruction. Therefore, as in the lower right example of FIG. 15, the normal operator 12b has two values (% r [rs1],% r [rs3]) from the first half register area and one value (%) from the late register area. Arithmetic (fnmsub) is performed using r [N + rs2]) as an input value. In addition, the expansion operator 12e inputs two values (% r [rs1],% r [rs2]) from the first register area and one value (% r [N + rs3]) from the late register area. The operation fnmsub is performed.

[6] operation of arithmetic unit when employing second unused bit type

FIG. 16 is a diagram for briefly explaining the operation of the arithmetic unit 10 in the arithmetic unit 1 shown in FIG. 1 when the second unused bit use mode is adopted. FIG. 17 is a diagram for explaining the operation of the instruction code issuing unit (setting unit) 20 and the generating unit 30 in the arithmetic unit 1 shown in FIG. 1 when the second unused bit use form is adopted. . 18 (a) to 18 (d) designate command codes, arithmetic codes, register write signals, and register numbers in the arithmetic unit 1 shown in FIG. 1 when employing the second unused bit usage form, respectively. It is a figure which shows (most significant bit only) concretely.

In the above-described first unused bit usage form, the unused bits rs1 [6], rs2 [6] in the instruction sets cross-fmadd1, ..., cross-fmadd4 are used to refer to Figs. The case where execution instruction of the extension processing described above is given is described. In the second unused bit use form described herein, in addition to the first use form, the SIMD instruction set (simd-fmadd, simd-fmsub, simd-fnmsub, simd-fnmadd) described above with reference to FIGS. Unused bits (rd [6], rs1 [6], rs2 [6], and rs3 [6]) are used. In particular, two of these unused bits rd [6], rs1 [6], rs2 [6], rs3 [6], specifically rs1 [6], rs2 [6], are used (Fig. 18 (a). ) Reference].

The extended instruction information is set in these two unused bits rs1 [6] and rs2 [6] by the function as the setting unit in the instruction code issuing unit 20. This extended instruction information is the normal processing by the instruction set (simd-fmadd, simd-fmsub, simd-fnmsub, simd-fnmadd) not using rs1 [6] and rs2 [6] (see the example on the left in FIG. 16). The instruction to execute another extension process different from that is given to the register 11 and the calculators 12b and 12e. And the generation part 30 is based on the expansion instruction information set to the unused bit and the information set to bits other than the unused bit, as mentioned later, referring FIG. 17 and FIG. 18, and the register 11 and the calculator 12b. , 12e) generates and outputs an extension command for instructing execution of the extension processing.

As a result, as shown in the right example of FIG. 16, in one calculator 12b or 12e, a calculation in which the value of the first half region and the second half region of the register 11 are input values can be realized. have. In particular, the instruction to execute the expansion process using the unused bits rs1 [6] and rs2 [6] registers the two input values to be subjected to multiplication in each of the calculators 12b and 12e, respectively. It becomes possible to input from the first half region and the second half region of 11). By such an extension process, the number of register combinations of operations by the SIMD method can be increased, and not only complex operations but also various combinations of values in the first register area and the second register area value can be realized in various operations. Can be.

Issued by the instruction code issuing unit 20 when adopting this second unused bit use form (i.e., processing by the instruction set (simd-fmadd, simd-fmsub, simd-fnmsub, simd-fnmadd)). 01 is set in the upper two bits (opcode [3: 2]) of the instruction type code. Hereinafter, with reference to FIG. 17 and FIG. 18, operation | movement of the arithmetic unit 1 when this 2nd unused bit utilization form is employ | adopted is demonstrated.

When employing the second unused bit usage form, the instruction code (opcode [3: 0]) issued by the instruction code issuing unit 20 and four register number instructions (rd [6: 0], rs1 [6: 0], rs2 [6: 0], rs3 [6: 0]) are converted in the generation unit 30 as shown in FIG. 17, and the instruction set b_we, e_we, b_rd [6: 0] , b_rs1 [6: 0], b_rs2 [6: 0], b_rs3 [6: 0], e_rd [6: 0], e_rs1 [6: 0], e_rs2 [6: 0], e_rs3 [6: 0], b_op [1: 0] and e_op [1: 0]) are input to the calculation unit 10.

As shown in Figs. 17 and 18 (b), the operation codes b_op [1: 0] for the normal operator 12b and the operation codes e_op [1: 0] for the extended operator 12e are shown. The value (opcode [1: 0]) of the lower two bits of the instruction type code included in the instruction code is used. The same operation code is always input to the normal calculator 12b and the extended calculator 12e, and these calculators 12b and 12e execute the same type of calculation.

At this time, as shown in Figs. 17 and 18 (c), as the register write control signal b_we for the normal operator 12b and the register write control signal e_we for the expansion operator 12e, fixed values are shown. 1 is set. As a result, the result of calculation by the normal operator 12b and extended operator 12e is always recorded in the first half region and the second half region of the register 11, respectively.

In addition, as shown in FIG. 17, the lower six bits (rd [5: 0], rs1 [5: 0], rs2 [5: 0], rs3 [5 :) of the four register number instructions included in the instruction code. 0]) is input as the register number instructions b_rd [5: 0], b_rs1 [5: 0], b_rs2 [5: 0], and b_rs3 [5: 0] for the normal operation 12b. At the same time, the same rd [5: 0], rs1 [5: 0], rs2 [5: 0], rs3 [5: 0] register register instructions (e_rd [5: 0], e_rs1 [ 5: 0], e_rs2 [5: 0], e_rs3 [5: 0]).

As shown in Figs. 17 and 18 (d), the fixed value 0 is set in the most significant bits b_rd [6] and b_rs3 [6] of the register number instruction for the normal operator 12b. A fixed value 1 is set in the most significant bits e_rd [6] and e_rs3 [6] of the register number instruction for 12e). On the other hand, the values of rs1 [6] and rs2 [6] are set in the most significant bits b_rs1 [6] and b_rs2 [6] of the register number instruction for the normal operator 12b, respectively. In addition, the most significant bit of the extended arithmetic unit (12e) register number assignments for (e_rs1 [6], e_rs2 [ 6]) , the value of ^~ rs1 [6] value and ^~ rs2 [6] are the respective setting. As a result, the two input values to be subjected to the multiplication in each of the calculators 12b and 12e can be input from the first half region and the second half region of the register 11, respectively. That is, the value from the register 11 to each operator 12b, 12e corresponds to each operator 12b, 12e by the extended instruction information set in the unused bits rs1 [6], rs2 [6]. Instructions for switching to values in areas other than the area of the register 11 are issued to the register 11. In addition, ^"~ X" represents an inverted value of X.

Next, a specific operation example when employing the second unused bit usage mode, for example, the calculation of simd-fnmsub% f40,% f10,% f80, and% f30 will be described.

In this case, the arithmetic units 12b and 12e of the arithmetic unit 10 execute two arithmetic operations as described below.

Calculation content of the ordinary calculator 12b:% r [40] ←% r [10] *% r [80]-% r [30]

Calculation contents of the expansion operator 12e:% r [104] ←% r [74] *% r [16]-% r [94]

In this case, the instruction type code (opcode [3: 0]) and the register number instruction (rd [6: 0], rs1 [6: 0], rs2 [6: 0], and rs3 specified in the instruction code shown in Table 12 below. [6: 0]) is converted into the values of the input signals for the calculators 12b and 12e shown in Table 13 below and input. That is, as shown in Table 12 below, 0101 is set as the command type code opcode [3: 0] by the command code issuing unit 20, and the function as the setting unit of the command code issuing unit 20 is set. 0 and 1 are set in the unused bits rs1 [6] and rs2 [6]. According to these values, the generation unit 30, based on the equation shown in Fig. 18D, most significant bits b_rd [6], b_rs1 [6], of the register number instruction for the normal operator 12b. 0, 0, 1, and 0 are calculated and set as b_rs2 [6] and b_rs3 [6]) (see Table 13 below). Similarly, 1, 1, 0, 1 are calculated and calculated as the most significant bits (e_rd [6], e_rs1 [6], e_rs2 [6], and e_rs3 [6]) of the register number instruction for the expansion operator 12e. Is set (see Table 13 below). The same operation code 01 is input as the operation code b_op [1: 0] for the normal operator 12b and the operation code e_op [1: 0] for the extended operator 12e. Here, the normal operator 12b and the extended operator 12e perform the same kind of calculation. In addition, the same values (rd [5: 0], rs1 [5: 0], rs2 [5: 0] in the lower 6 bits of the register number instruction for the normal operator 12b and the register number instruction of the extended operator 12e. , rs3 [5: 0]) is input.

As a result, the normal operator 12b causes the two values (% r) from the first register region selected by the most significant bits b_rs1 [6], b_rs2 [6], b_rs3 [6] = 0, 1, 0 of the register number indication. [rs1] =% r [10],% r [rs3] =% r [30]) and one value from the late register area (% r [rs2] =% r [80]) as an input value (fnmsub) is performed. In addition, the extension operator 12e is one value (% r [) from the register first half area selected by the most significant bits e_rs1 [6], e_rs2 [6], e_rs3 [6] = 1, 0, 1 of the register number indication. N + rs2] =% r [16]) and two values from the late register area (% r [N + rs1] =% r [74],% r [N + rs3] =% r [94]) as input values. To perform the operation. Therefore, the arithmetic result by the same kind of calculation using a different input value is output from the normal computing unit 12b and the extended computing unit 12e. In addition, a fixed value 1 is set in the register write control signal b_we for the normal operator 12b and the register write signal for the extended operator 12e. For this reason, the arithmetic result by the normal operator 12b is recorded as a register value (% r [40]) in the first half area of the register 11. Similarly, the result of the calculation by the expansion operator 12e is recorded as a register value (% r [104]) in the second half region of the register 11.

TABLE 12

TABLE 13

In the above specific operation example, the case where 0101 is set in the instruction type code opcode [3: 0] and 0 and 1 are set in the unused bits rs1 [6] and rs2 [6] has been described. When employing two unused bit usage forms, other combinations of operations can be realized. Here, four types of operations by the calculators 12b and 12e are selected by opcode [1: 0]. For each operation type, two values (data to be multiplied) which are input to each of the calculators 12b and 12e by the values of the unused bits rs1 [6] and rs2 [6] are registered in the first register area or in the register. Which of the latter areas is to be read and indicated.

For example, if the unused bit (most significant bit) (rs1 [6], rs2 [6]) is 0, 0, the most significant bits b_rs1 [6], b_rs2 [6], b_rs3 [6] = 0, 0, 0, the most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 1, 1, 1 of the register number instruction. Therefore, the normal arithmetic operator 12b performs calculation with three values (% r [rs1],% r [rs2], and% r [rs3]) from the register first half area as input values. In addition, the expansion operator 12e performs calculations using three% r [N + rs1],% r [N + rs2], and% r [N + rs3] from the second half of the register as input values.

If the unused bit (highest bit) (rs1 [6], rs2 [6]) is 0, 1, the most significant bits b_rs1 [6], b_rs2 [6], b_rs3 [6] = 0, 1, 0, Further, the most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 1, 0, 1 of the register number indication. Therefore, the normal operator 12b inputs two values (% r [rs1],% r [rs3]) from the first register area and one value (% r [N + rs2]) from the late register area. The operation is performed. In addition, the expansion operator 12e inputs one value (% r [rs2]) from the first register area and two values (% r [N + rs1] and% r [N + rs3]) from the late register area. The operation is performed with the value.

If the unused bit (highest bit) (rs1 [6], rs2 [6]) is 1, 0, the most significant bits b_rs1 [6], b_rs2 [6], b_rs3 [6] = 1, 0, 0, Further, the most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 0, 1, 1 of the register number instruction. Therefore, the normal operator 12b inputs two values (% r [rs2],% r [rs3]) from the first register area and one value (% r [N + rs1]) from the late register area. The operation is performed. In addition, the expansion operator 12e inputs one value (% r [rs1]) from the first register area and two values (% r [N + rs2] and% r [N + rs3]) from the late register area. The operation is performed with the value.

If the unused bit (highest bit) (rs1 [6], rs2 [6]) is 1, 1, the most significant bits b_rs1 [6], b_rs2 [6], b_rs3 [6] = 1, 1, 0, Further, the most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 0, 0, 1 of the register number instruction. Therefore, the normal operator 12b inputs one value (% r [rs3]) from the first register area and two values (% r [N + rs1] and% r [N + rs2]) from the register late area. The operation is performed with the value. In addition, the expansion operator 12e inputs two values (% r [rs1],% r [rs2]) from the first register area and one value (% r [N + rs3]) from the late register area. The operation is performed.

[7] Operation of arithmetic unit when employing third unused bit type

19 and 20 are diagrams for briefly explaining the operation of the arithmetic unit 10 in the arithmetic unit 1 shown in FIG. 1 when the third unused bit usage mode is adopted. FIG. 21 is a view for explaining the operation of the instruction code issuing unit (setting unit) 20 and the generating unit 30 in the arithmetic unit 1 shown in FIG. 1 when the second unused bit use form is adopted. . 22 (a) to 22 (d) designate command codes, arithmetic codes, register write signals, and register numbers in the arithmetic unit 1 shown in FIG. 1 at the time of employing the third unused bit use form. It is a figure which shows (most significant bit only) concretely. FIG. 23 and FIG. 24 are diagrams showing a specific example of a combination of calculations by the arithmetic unit 10 in the arithmetic unit shown in FIG. 1 when employing the third unused bit usage form. FIG. 25 is a circuit diagram showing a concrete implementation example of the generation unit 30 in the arithmetic unit 1 shown in FIG. 1 when employing the third unused bit usage form.

In the third unused bit usage form described here, as shown in Fig. 22A, the above-described SIMD instruction set (simd-fmadd, simd-fmsub, simd-fnmsub, simd-fnmadd) is used. , All of the unused bits (rd [6], rs1 [6], rs2 [6], rs3 [6]) are used. In the second usage form, the SIMD instruction is extended using the unused bits rs1 [6] and rs2 [6]. In this third usage form, the unused bits rs3 [6] and rd [6] are stored. By using this, the SIMD instruction is further extended.

Here, the value of the unused bit rs3 [6] is used for the selection of the product input register number on the expansion operator 12e side, and the value of the unused bit rd [6] is calculated by the expansion operator 12e. Used for the selection of the code e_op [1: 0]. By this extension, as shown in Figs. 19 and 20, the same operation as that of the new instruction added in the first use mode can be realized by the extension of the SIMD instruction. Therefore, in the third use form, the instructions newly added in the first use form (cross-fmadd1, ..., cross-fmadd4) become unnecessary.

The extended instruction information is set in these four unused bits rd [6], rs1 [6], rs2 [6], and rs3 [6] by a function as a setting unit in the instruction code issuing unit 20. do. This extended instruction information is generated by the instruction set (simd-fmadd, simd-fmsub, simd-fnmsub, simd-fnmadd) that does not use rd [6], rs1 [6], rs2 [6], or rs3 [6]. Instructions for executing expansion processing different from the normal processing (see the left example in FIG. 19) (for example, the combination of operations in FIGS. 23 and 24) are given to the registers 11 and the calculators 12b and 12e. 21 and 22, the generation unit 30, based on the extended instruction information set in the unused bit and the information set in the bits other than the unused bit, the generation unit 30 and the calculator 12b. , 12e) generates and outputs an extension command for instructing execution of the extension processing.

Accordingly, as shown in the right example of FIG. 19 or in FIG. 20, in one calculator 12b or 12e, a calculation is performed in which the first half region and the second half region of the register 11 are mixed as input values. It can be realized. Further, the instruction to switch the type of operation by the expansion calculator 12e is given, and the operation type in the calculator 12e is changed and controlled. Therefore, it is possible to execute a complex matrix multiplication operation performed by four operations (that is, four instructions) according to the above formulas (1-1) to (1-4) in two instructions, as described later. .

In the case of adopting this third unused bit use form, 01 is set in the upper two bits (opcode [3: 2]) of the instruction type code issued by the instruction code issuing unit 20. Hereinafter, with reference to FIGS. 21-25, operation | movement of the arithmetic unit 1 when this 3rd unused bit utilization form is employ | adopted is demonstrated.

When adopting the third unused bit usage form, the instruction code (opcode [3: 0]) issued by the instruction code issuing unit 20 and four register number instructions (rd [6: 0], rs1 [6: 0) ], rs2 [6: 0], rs3 [6: 0]) are converted in the generation unit 30 as shown in FIG. 21, and the instruction sets b_we, e_we, b_rd [6: 0], b_rs1 [6: 0], b_rs2 [6: 0], b_rs3 [6: 0], e_rd [6: 0], e_rs1 [6: 0], e_rs2 [6: 0], e_rs3 [6: 0], b_op [1: 0] and e_op [1: 0]) are input to the calculation unit 10.

Here, as the operation code b_op [1: 0] for the normal operator 12b, the value (opcode [1: 0]) of the lower two bits of the instruction type code included in the instruction code is used. In addition, in the generation unit 30, as shown in Fig. 22B and Table 14 below, the operation code e_op [1 for the extension operator 12e based on the value of the unused bit rd [6]. : 0]) is generated. Unlike the case of the SIMD system described above, the type of the calculation executed in the normal operator 12b and the extended operator 12e is independently controlled and switched. As a result, the normal arithmetic unit 12b and the extended arithmetic unit 12e can perform the same type of calculation or the different type of calculation. In this manner, by combining the SIMD instruction and the value (extension instruction information) set in the unused bit rd [6], the same number of operation combinations as the instructions added in the first use mode can be realized by the SIMD instruction only.

[Table 14]

At this time, as shown in Figs. 21 and 22 (c), as the register write control signal b_we for the normal operator 12b and the register write control signal e_we for the expansion operator 12e, fixed values are shown. 1 is set. As a result, the result of calculation by the normal operator 12b and the extended operator 12e is always recorded in the first half region and the second half region of the register 11, respectively.

In addition, as shown in Fig. 21, the lower six bits (rd [5: 0], rs1 [5: 0], rs2 [5: 0], rs3 [5 :) of the four register number instructions included in the instruction code. 0]) is input as the register number instructions b_rd [5: 0], b_rs1 [5: 0], b_rs2 [5: 0], and b_rs3 [5: 0] for the normal operator 12b. At the same time, the same rd [5: 0], rs1 [5: 0], rs2 [5: 0], rs3 [5: 0] register register instructions (e_rd [5: 0], e_rs1 [ 5: 0], e_rs2 [5: 0], e_rs3 [5: 0]).

21, 22 (d) and Table 15 below, the fixed value 0 is set in the most significant bits b_rd [6] and b_rs3 [6] of the register number instruction for the normal operator 12b. A fixed value 1 is set in the most significant bits e_rd [6] and e_rs3 [6] of the register number instruction for the expansion operator 12e. In addition, the values of rs1 [6] and rs2 [6] are set in the most significant bits b_rs1 [6] and b_rs2 [6] of the register number instruction for the normal operator 12b, respectively. On the other hand, extended operator (12e), the most significant bit (e_rs1 [6], e_rs2 [ 6]) of the register number assignments for each ^{~ rs1 [6] ^ rs3 [} 6] and ^~ value of rs2 [6] are calculated, generated Is set. As a result, the two input values to be subjected to the multiplication in each of the calculators 12b and 12e can be input from the first half region and the second half region of the register 11, respectively. That is, the value from the register 11 to each of the calculators 12b and 12e is determined by the extended instruction information set in the unused bits rs1 [6], rs2 [6], and rs3 [6]. An instruction to switch to a value in an area other than that of the register 11 corresponding to 12e) is given to the register 11. In addition, ^"~ X" represents an inverted value of X. In addition, "A ^ B" represents an exclusive OR of E and A.

The value set in the unused bits (rs1 [6], rs2 [6], rs3 [6]) (extended instruction information) and the most significant bits (b_rs1 [6], b_rs2 [6], e_rs1 [6], The correspondence with the value set in e_rs2 [6]) is shown in Table 15 below.

TABLE 15

As described above, the values (expansion instruction information) set in the unused bits rs1 [6], rs2 [6], and rs3 [6], respectively, function as follows.

rs1 [6]: When 1 is set, the first input value b_i1 of the normal operator 12b is supplied from the late register region.

rs2 [6]: When 1 is set, the second input value b_i2 of the normal operator 12b is supplied from the second half of the register.

rs3 [6]: When 1 is set, the first input value b_i1 of the extended operator 12e is supplied from the same register area as the first input value b_i1 of the normal operator 12b (rs1 copy flag).

rd [6]: Changes the operation code e_op [1: 0] of the expansion operator 12e (multiply the result of the multiplication by -1).

Next, a specific operation example when employing the first unused bit usage mode, for example, the calculation of simd-fmadd% f30,% f10,% f20, and% f {30 + 64} will be described.

In this case, the arithmetic units 12b and 12e of the arithmetic unit 10 execute two arithmetic operations as described below.

Calculation content of the ordinary calculator 12b:% r [30] ←% r [10] *% r [20] +% r [30]

Calculation contents of the expansion operator 12e:% r [94] ←% r [10] *% r [84] +% r [94]

These two operations correspond to the following complex operations when the value of the real part in the first half region of the register 11 and the value of the imaginary part in the second half region of the register 11 are maintained.

X ← X + A * C (1-1)

Y ← Y + A * D (1-2)

In this case, the instruction type code (opcode [3: 0]) and the register number instruction (rd [6: 0], rs1 [6: 0], rs2 [6: 0], and rs3 specified in the instruction code shown in Table 16 below. [6: 0]) is converted into the values of the input signals for the calculators 12b and 12e shown in Table 17 below and input. That is, as shown in Table 16 below, 0100 is set as the command type code (opcode [3: 0]) by the command code issuing unit 20, and the function as the setting unit of the command code issuing unit 20 is set. , 0, 0, 0, 1 are set to four unused bits rd [6], rs1 [6], rs2 [6], and rs3 [6] (third upper example from the left in FIG. 23 to be described later). Reference). According to these values, the generation unit 30 uses the most significant bits b_rd [6] and b_rs1 of the register number instruction for the ordinary operator 12b based on the equation shown in Fig. 22D and Table 15 above. [6], b_rs2 [6], b_rs3 [6]), 0, 0, 0, 0 are calculated and set (see Table 17 below). Similarly, 1, 0, 1, 1 are calculated and calculated as the most significant bits (e_rd [6], e_rs1 [6], e_rs2 [6], e_rs3 [6]) of the register number instruction for the extension operator 12e. Is set (see Table 17 below). The arithmetic code 00 determined by the instruction type code opcode [1: 0] is input to the normal arithmetic operator 12b. The extended arithmetic operator 12e uses the equation shown in Fig. 22B and the value of the unused bit rd [6] and the instruction type code opcode [1: 0] as shown in Table 14 above. The operation code 00 to be determined is input. Therefore, in this specific example, the normal operator 12b and the extended operator 12e perform the same kind of operation fmadd. In addition, the same values (rd [5: 0], rs1 [5: 0], rs2 [5: 0] in the lower 6 bits of the register number instruction for the normal operator 12b and the register number instruction of the extended operator 12e. , rs3 [5: 0]) is input.

Thus, as in the upper third example from the left in FIG. 23, the normal operator 12b is assigned to the most significant bits b_rs1 [6], b_rs2 [6], b_rs3 [6] = 0, 0, 0 of the register number instruction. Three values A (% r [rs1] =% r [10]), C (% r [rs2] =% r [20]), X (% r [rs3] =% r [30] is used as an input value, and an operation based on Equation (1-1) is performed. In addition, as in the upper third example from the left in FIG. 23, the expansion operator 12e uses the most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 0, 1, 1 of the register number instruction. One value A (% r [rs1] =% r [10]) from the selected register front region and two values D (% r [N + rs2] =% r [84]) from the late register region, Y ( The calculation based on Formula (1-2) is performed using% r [N + rs3] =% r [94]) as an input value. Therefore, the arithmetic result by the same kind of calculation using a different input value is output from the normal computing unit 12b and the extended computing unit 12e. In addition, a fixed value 1 is set in the register write control signal b_we for the normal operator 12b and the register write signal for the extended operator 12e. For this reason, the operation result by the normal operator 12b is recorded as a register value (% r [rd] =% r [30]) in the first half area of the register 11. Similarly, the result of the calculation by the expansion operator 12e is recorded as a register value (% r [N + rd] =% r [94]) in the latter region of the register 11. That is, two kinds of operations according to the above formulas (1-1) and (1-2) can be executed by one instruction. Similarly, the above formulas (1-3) and (1-4) can also be executed by one instruction. Therefore, the complex arithmetic operation conventionally executed by four instructions can be executed by two instructions.

TABLE 16

TABLE 17

In the above specific operation example, 0100 (simd-fmadd) is set in the instruction type code opcode [3: 0], and four unused bits rd [6], rs1 [6], rs2 [6], and rs3. [6]) has been described in the case where 0, 0, 0, 1 is set. However, when employing the third unused bit use form, 63 kinds of arithmetic combinations can be realized. 16 types for each of four types of SIMD instructions [command type code opcode [3: 0] = 0100 (simd-fmadd), 0101 (simd-fmsub), 0110 (simd-fnmsub), and 0111 (simd-fnmadd)] A combination of operations can be realized. That is, in the third use mode, 64 types of arithmetic combination patterns can be realized in total. Here, all (16 types) of operation combination patterns for the instruction type code opcode [3: 0] = 0100 (simd-fmadd) among the four types of SIMD instructions will be described with reference to FIGS. 23 and 24. Also, for each of the three other types of SIMD instructions, 16 types of arithmetic combination patterns are realized as shown in FIGS. 23 and 24.

FIG. 23 shows eight types of combinations of operations when the instruction type code opcode [3: 0] = 0100 and when the unused bit rd [6] = 0. FIG. At this time, the arithmetic operators 12b and 12e perform the same kind of arithmetic operation fmadd.

In addition, the left half of FIG. 23 shows four types of arithmetic combinations when unused bits rd [6] = 0 and unused bits rs3 [6] = 0.

At this time, if the unused bit (most significant bit) (rs1 [6], rs2 [6]) is 0 or 0, the most significant bit b_rs1 [6], b_rs2 [6], b_rs3 [6] = 0, 0 in the register number indication. , 0, and most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 1, 1, 1 of the register number indication. Therefore, as in the first upper example from the left in FIG. 23, the normal operator 12b inputs three values (% r [rs1],% r [rs2], and% r [rs3]) from the register front area. An operation (fmadd) is performed with the value. In addition, the expansion operator 12e performs an operation (fmadd) using three values (% r [N + rs1],% r [N + rs2], and% r [N + rs3]) from the second half of the register as input values. .

If the unused bit (highest bit) (rs1 [6], rs2 [6]) is 0, 1, the most significant bits b_rs1 [6], b_rs2 [6], b_rs3 [6] = 0, 1, 0, Further, the most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 1, 0, 1 of the register number indication. Therefore, as in the first lower example from the left in Fig. 23, the normal operator 12b has two values (% r [rs1],% r [rs3]) from the first register area and one from the latter register area. An operation (fmadd) is performed using the value% r [N + rs2] as an input value. In addition, the expansion operator 12e inputs one value (% r [rs2]) from the first register area and two values (% r [N + rs1] and% r [N + rs3]) from the late register area. The calculation (fmadd) is performed with the value.

If the unused bit (highest bit) (rs1 [6], rs2 [6]) is 1, 0, the most significant bits b_rs1 [6], b_rs2 [6], b_rs3 [6] = 1, 0, 0, Further, the most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 0, 1, 1 of the register number instruction. Therefore, as in the second upper example from the left in FIG. 23, the normal operator 12b has two values (% r [rs2],% r [rs3]) from the first register area and one from the second register area. The operation (fmadd) is performed using the value (% r [N + rs1]) as an input value. In addition, the expansion operator 12e inputs one value (% r [rs1]) from the first register area and two values (% r [N + rs2] and% r [N + rs3]) from the late register area. An operation (fmadd) is performed with the value.

If the unused bit (most significant bit) (rs1 [6], rs2 [6]) is 1, 1, the most significant bits b_rs1 [6], b_rs2 [6], b_rs3 [6] = 1, 1, 0, Further, the most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 0, 0, 1 of the register number instruction. Therefore, as in the second lower example from the left in FIG. 23, the normal operator 12b uses one value (% r [rs3]) from the first register area and two values (% r [) from the second register area. N + rs1] and% r [N + rs2]) are used as input values to perform an operation (fmadd). In addition, the expansion operator 12e inputs two values (% r [rs1],% r [rs2]) from the first register area and one value (% r [N + rs3]) from the late register area. The operation (fmadd) is performed.

In addition, the right half of FIG. 23 shows four types of arithmetic combinations when unused bits rd [6] = 0 and unused bits rs3 [6] = 1.

At this time, if the unused bit (most significant bit) (rs1 [6], rs2 [6]) is 0 or 0, the most significant bit b_rs1 [6], b_rs2 [6], b_rs3 [6] = 0, 0 in the register number indication. , 0, and most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 0, 1, 1 of the register number instruction. Accordingly, as in the upper third example from the left in FIG. 23, the normal operator 12b selects three values (% r [rs1],% r [rs2], and% r [rs3]) from the register front area. An operation (fmadd) is performed as an input value. In addition, the expansion operator 12e inputs one value (% r [rs1]) from the first register area and two values (% r [N + rs2] and% r [N + rs3]) from the late register area. An operation (fmadd) is performed with the value.

If the unused bit (highest bit) (rs1 [6], rs2 [6]) is 0, 1, the most significant bits b_rs1 [6], b_rs2 [6], b_rs3 [6] = 0, 1, 0, Further, the most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 0, 0, 1 of the register number instruction. Therefore, as in the lower third example from the left in FIG. 23, the normal operator 12b includes two values (% r [rs1],% r [rs3]) from the first register region and one from the latter register region. The operation (fmadd) is performed using the value (% r [N + rs2]) as an input value. In addition, the expansion operator 12e inputs two values (% r [rs1],% r [rs2]) from the first register area and one value (% r [N + rs3]) from the late register area. The operation (fmadd) is performed.

If the unused bit (highest bit) (rs1 [6], rs2 [6]) is 1, 0, the most significant bits b_rs1 [6], b_rs2 [6], b_rs3 [6] = 1, 0, 0, In addition, the most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 1, 1, 1 of the register number instruction. Therefore, as in the fourth upper example from the left in FIG. 23, the normal operator 12b has two values (% r [rs2],% r [rs3]) from the first register area and one from the late register area. The operation (fmadd) is performed using the value (% r [N + rs1]) as an input value. In addition, the expansion operator 12e performs an operation (fmadd) using three values (% r [N + rs1],% r [N + rs2], and% r [N + rs3]) from the second half of the register as input values. .

If the unused bit (most significant bit) (rs1 [6], rs2 [6]) is 1, 1, the most significant bits b_rs1 [6], b_rs2 [6], b_rs3 [6] = 1, 1, 0, Further, the most significant bits e_rs1 [6], e_rs2 [6], and e_rs3 [6] = 1, 0, 1 of the register number indication. Accordingly, as in the fourth lower example from the left in FIG. 23, the normal operator 12b uses one value (% r [rs3]) from the first register area and two values (% r [) from the second register area. N + rs1] and% r [N + rs2]) are used as input values to perform an operation (fmadd). In addition, the expansion operator 12e inputs one value (% r [rs2]) from the first register area and two values (% r [N + rs1] and% r [N + rs3]) from the late register area. An operation (fmadd) is performed with the value.

Fig. 24 shows eight types of combinations of operations when the instruction type code opcode [3: 0] = 0100 and when unused bits (rd [6] = 1). At this time, the normal operator 12b executes the operation fmadd, and the expansion operator 12e executes the operation fnmsub. In addition, the left half of FIG. 24 shows four types of arithmetic combinations when unused bits rd [6] = 1 and unused bits rs3 [6] = 0, and the right half of FIG. 24 shows unused bits rd [ 6] = 1 and four types of arithmetic combinations when unused bits rs3 [6] = 1 are shown. In the combination of operations shown in FIG. 24, the unused bit rd [6] = 1 means that the extended arithmetic unit 12e is switched to perform a different operation fnmsub from the normal arithmetic operator 12b. Since it is the same as the combination of operations to be performed, detailed description of FIG. 24 is omitted.

Here, with reference to FIG. 25, the specific implementation example of the generation | generation part 30 in the arithmetic unit 1 shown in FIG. 1 at the time of employ | adopting a 3rd unused bit utilization form is demonstrated. The generation unit 30 shown in FIG. 25 includes four AND logic circuits (AND gates) 31, 32, 33, and 34, two exclusive OR circuits (EOR gates) 35, 36, and an inverting circuit. (NOT gate, inverter) 31a, 32a, 34a, 36a. The generation unit 30 is also capable of coping with the non-SIMD system described above with reference to FIGS. 3 to 5 by opcode [2] of the instruction type code. That is, when opcode [2] = 1, the third usage mode described with reference to Figs. 19 to 24 is adopted, while when opcode [2] = 0, the non-SIMD method is described with reference to Figs. Are employed.

The AND circuit 31 calculates the AND of the inverse of rd [6] and opcode [2], and outputs it as a register number instruction b_rd [6]. The inversion value of opcode [2] input to the AND circuit 31 is generated and output by the inversion circuit 31a. That is, when opcode [2] = 0 and the non-SIMD method is adopted, the inverted value 1 of opcode [2] is input to the AND circuit 31, and the value of rd [6] is output as b_rd [6]. . On the other hand, when opcode [2] = 1 and the third usage mode is adopted, the inversion value 0 of opcode [2] is input to the AND circuit 31, so that b_rd [6] is fixed to zero.

The logical product circuit 32 calculates the logical product of rs3 [6] and the inverted value of opcode [2], and outputs it as a register number instruction (b_rs3 [6]). The inversion value of opcode [2] input to the AND circuit 31 is calculated by the inversion circuit 32a. That is, when opcode [2] = 0 and the non-SIMD method is adopted, the inverted value 1 of opcode [2] is input to the AND circuit 32, and the value of rs6 [6] is output as b_rs3 [6]. . On the other hand, when opcode [2] = 1 and the third usage mode is adopted, the inversion value 0 of opcode [2] is input to the AND circuit 31, so that b_rs3 [6] is fixed to zero.

The exclusive OR circuit 36 calculates and outputs an exclusive OR between the inversion values of rs3 [6] and rs1 [6]. The inversion value of rs1 [6] input to the exclusive OR circuit 36 is calculated by the inversion circuit 36a. The exclusive OR calculated by this exclusive OR circuit 36 is a value ( ^˜ rs1 [6] ^ rs3 [6]) described with reference to Tables 15, 21 and 22 (d).

The AND circuit 33 calculates the AND of the output of the exclusive OR circuit 36 and opcode [2], and outputs it as a register number instruction (e_rs1 [6]). That is, when opcode [2] = 0 and the non-SIMD method is employed, e_rs1 [6] is fixed to zero. On the other hand, and opcode [2] = 1 if the third mode ^{employed, ~ rs1 [6] ^ rs3} [6] is output as e_rs1 [6] [Fig. 22 (d), see.

The AND circuit 34 calculates the AND of the inverse value of rs2 [6] and opcode [2], and outputs it as a register number instruction (e_rs2 [6]). inverse of ^{rs2 [6] (~ rs2 [} 6]) is calculated by inverting circuit (34a). That is, when opcode [2] = 0 and the non-SIMD scheme is employed, e_rs2 [6] is fixed to zero. On the other hand, opcode [2] = 1, and when the third mode employed, ^~ rs2 [6] is output as e_rs2 [6] [Fig. 22 (d), see.

The exclusive-OR circuit 35 calculates an exclusive-OR between rd [6] and opcode [1] and outputs it as an operation code e_op [1]. In addition, the generation unit 30 shown in FIG. 25 outputs opcode [1: 0] as it is as an operation code b_op [1: 0] and outputs opcode [0] as an operation code e_op [0]. Output as is. Accordingly, the generation unit 25 outputs the operation codes b_op [1: 0] and e_op [1: 0] as shown in Table 14.

The generator 30 shown in FIG. 25 fixedly outputs 1 as the register write control signal b_we, and assigns the opcode [2] to the register write control signal e_w and the register number (e_rd [6]). , e_rs3 [6]). In addition, the generation unit 30 designates rd [5: 0], rs1 [6: 0], rs2 [6: 0], and rs3 [5: 0] respectively as register numbers (b_rd [5: 0], b_rs1). Output as [6: 0], b_rs2 [6: 0], b_rs3 [5: 0]), rd [5: 0], rs1 [5: 0], rs2 [5: 0], rs3 [5: 0 ] Are output as register number designations (e_rd [5: 0], e_rs1 [5: 0], e_rs2 [5: 0], e_rs3 [5: 0]), respectively.

Accordingly, the generation unit 30 shown in FIG. 25 has the instruction code (opcode [1: 0],) from the instruction code issuing unit 20 when opcode [2] = 1 and the third usage mode is adopted. rd [6: 0], rs1 [6: 0], rs2 [6: 0], rs3 [6: 0]) were described with reference to Table 14, Table 15, FIG. 21 and FIG. b_we, e_we, b_rd [6: 0], b_rs1 [6: 0], b_rs2 [6: 0], b_rs3 [6: 0], e_rd [6: 0], e_rs1 [6: 0], e_rs2 [6: 0], e_rs3 [6: 0], b_op [1: 0], e_op [1: 0]) and output. When opcode [2] = 0 and the non-SIMD method is adopted, the command code from the command code issuing unit 20 is converted into the command set described with reference to Figs. 4 and 5 and output.

[8] Effects of the Embodiment

As described above, according to the arithmetic unit 1 and the arithmetic method as one embodiment of the present invention, one in one instruction by utilizing the functions of the instruction code issuing unit (setting unit) 20 and the generating unit 30. By using the above unused bits rd [6], rs1 [6], rs2 [6], and rs3 [6], execution instructions for extension processing different from the normal processing can be given. Thus, for example, various combinations of operations in the SIMD floating point multiplication operation and the like can be realized with a small number of instruction type codes. Therefore, as described above, for example, complex operations such as complex matrix multiplication operations performed by four instructions can be executed by two instructions, thereby doubling the throughput.

In addition, the arithmetic unit 1 inputs the operation type and input register number instruction with respect to the normal calculator 12b, and the operation type and input register number instruction with respect to the expansion calculator 12e independently. For this reason, in the normal calculator 12b and the extended calculator 12e, it is possible to execute calculations by different input values (register values) or different types of operations. Therefore, in the arithmetic unit 1, by using the unused bits rd [6], rs1 [6], rs2 [6], and rs3 [6], not only the complex matrix multiplication operation described above, but also FIGS. It is possible to easily perform calculations by various calculation combination patterns described with reference to FIGS. 15, 23, and 24.

[9] others

In addition, this invention is not limited to embodiment mentioned above, It can variously deform and implement in the range which does not deviate from the meaning of this invention.

For example, in the above-described embodiment, the case in which two calculators are normally provided as the calculator and the extended calculator is described. However, the present invention is not limited thereto, and the present invention is similarly applied to the case where three or more calculators are provided. The same effect as that of one embodiment can be obtained.

In addition, although the bit unused by employing the SIMD method is used as the unused bit, the present invention is not limited thereto, and the above-described information is also set by setting the extended processing information in the unused bit generated by the adoption of various methods. The same effect as that of one embodiment can be obtained.

In addition, the functions (all or part of the functions) as the setting unit 20 (setting step) and the generation unit 30 (creation step) described above are predetermined by a computer (including a CPU, an information processing apparatus, and various terminals). This is realized by executing the application program.

The program is, for example, a flexible disk, a CD (CD-ROM, CD-R, CD-RW, etc.), a DVD (DVD-ROM, DVD-RAM, DVD-R, DVD-RW, DVD + R, DVD + RW, etc.) and the like. In the form of a computer readable recording medium. In this case, the computer reads the program from the recording medium, transfers it to an internal storage device or an external storage device, and stores and uses the program. The program may be recorded in a storage device (recording medium) such as a magnetic disk, an optical disk, a magneto-optical disk, or the like, and the program may be provided to the computer from the storage device through a communication line.

The computer is a concept including hardware and an operating system (OS), and refers to hardware operating under the control of the OS. In addition, when the OS is unnecessary and the hardware is operated by the application program alone, the hardware itself corresponds to the computer. The hardware includes at least a microprocessor such as a CPU and means for reading a computer program recorded on a recording medium. As described above, the program includes a program code for realizing the functions of the setting unit 20 (setting step) and the generating unit 30 (generation step) in the computer. In addition, some of the functions may be realized by the OS, not the application program.

In addition, as the recording medium in the present embodiment, in addition to the above-described flexible disk, CD, DVD, magnetic disk, optical disk, magneto-optical disk, IC card, ROM cartridge, magnetic tape, punch card, computer Various computer-readable media, such as an internal storage device (memory such as RAM or ROM), an external storage device, or a printed matter printed with a code such as a barcode, can also be used.

[10] bookkeeping

About the embodiment including the above first to fourth embodiments, the following supplementary notes are also disclosed.

(Book 1)

A register that stores data to be operated on, and one or more calculators that perform an operation based on data read from the registers, indicating a type of data to be read from the registers and an operation to be performed by the calculator. A computing device that receives a single command composed of a plurality of bits, and executes the type of operation indicated by the one command based on the data indicated by the one command,

Setting to set one or more unused bits in the one instruction to execute extended instruction information for at least one of the register and the operator, the execution instruction of an extension process being different from the normal processing executed by the one instruction. An arithmetic unit characterized by having a part.

(Book 2)

Execution of the expansion processing for at least one of the register and the calculator based on the expansion instruction information set in the unused bit by the setting unit and information set in bits other than the unused bit in the one instruction. The computing device according to Appendix 1, further comprising a generation unit for generating an instruction to give an instruction and outputting the instruction as one command.

(Supplementary Note 3)

The unused bit is a bit that is not used during the normal processing by adopting a SIMD method for processing a plurality of data streams with the one instruction and having two or more the above-mentioned operators for dividing the register area. The arithmetic unit as described in the appendix 1 or the appendix 2.

(Appendix 4)

The two or more operators are multi-input multi-output operators that can switch the type of operation according to the operation type code included in the one instruction, respectively,

The unused bit is the most significant bit of the register number indicating field indicating each data in the register to be output to each multiplication operator contained in the one instruction. .

(Note 5)

The two or more operators are multi-input multi-output operators that can switch the type of operation according to the operation type code included in the one instruction, respectively,

The unused bit is the most significant bit of the register number indicating field indicating a storage destination in the register of the result of the operation by each multiplication operator included in the one instruction. The computing device described in the above.

(Note 6)

The extended instruction information is an instruction for changing the data to be output to each multiplication operator to data in an area other than the area of the register corresponding to each multiplication operator. The computing device described in Appendix 5.

(Appendix 7)

The arithmetic unit according to any one of appendices 4 to 6, wherein the extended instruction information provides an instruction for switching the type of operation by each multiplication operator to each multiplication operator.

(Appendix 8)

An arithmetic apparatus having a register for storing data of arithmetic object and at least one arithmetic operator which executes an operation based on the data read from the register, the arithmetic unit of the data to be read from the register and the arithmetic operation to be performed by the arithmetic operator. Receiving an instruction consisting of a plurality of bits indicating a type, the calculator is an operation method for performing the operation of the type indicated by the one instruction based on the data indicated by the one instruction,

Setting to set one or more unused bits in the one instruction to execute extended instruction information for at least one of the register and the operator, the execution instruction of an extension process being different from the normal processing executed by the one instruction. And a step of computing.

(Appendix 9)

Execution of the expansion processing for at least one of the register and the calculator based on the expansion instruction information set in the unused bit in the setting step and information set in bits other than the unused bit in the one instruction. The generation method according to Appendix 8, further comprising a generation step of generating an extension command for giving an instruction and outputting the command as the one command.

(Book 10)

The unused bit is a bit that is not used during the normal processing by adopting a SIMD method for processing a plurality of data streams with the one instruction and having two or more the above-mentioned operators for dividing the register area. The calculation method described in Appendix 8 or Appendix 9.

(Note 11)

The two or more operators are multi-input multi-output operators that can switch the type of operation according to the operation type code included in the one instruction, respectively,

The unused bit is the most significant bit of the register number indicating field indicating each data in the register to be output to each multiplication operator contained in the one instruction.

(Appendix 12)

The two or more operators are multi-input multi-output operators that can switch the type of operation according to the operation type code included in the one instruction, respectively,

The unused bit is the most significant bit of the register number indicating field indicating a storage destination in the register of the result of the operation by each multiplication operator included in the one instruction. The calculation method described in.

(Appendix 13)

The extended instruction information is an instruction to convert the data to be output to each multiplication operator to data in an area other than the area of the register corresponding to each multiplication operator. The calculation method described in Appendix 12.

(Book 14)

The extended instruction information is any one of appendices 11 to 13, characterized in that an instruction for switching the type of operation by each multiplication operator is given to each multiplication operator.

BRIEF DESCRIPTION OF THE DRAWINGS The block diagram which shows the structure of the arithmetic unit as one Embodiment of this invention.

FIG. 2 is a flowchart for explaining the basic operation of the calculation unit in the calculation device shown in FIG. 1. FIG.

FIG. 3 is a diagram for briefly explaining the operation of the computing unit in the computing device shown in FIG. 1 when employing a non-SIMD. FIG.

4 is a view for explaining the operation of an instruction code issuing unit and a generating unit in the arithmetic unit shown in FIG. 1 when employing a non-SIMD.

5 (a) to 5 (d) respectively specify the instruction code, operation code, register write signal, and register number designation (only the most significant bit) in the arithmetic unit shown in FIG. 1 when non-SIMD is employed. Drawings shown by.

FIG. 6 is a diagram for briefly explaining the operation of the computing unit in the computing device shown in FIG. 1 when employing a SIMD. FIG.

FIG. 7 is a view for explaining the operation of an instruction code issuing unit and a generating unit in the arithmetic unit shown in FIG. 1 when employing a SIMD. FIG.

8A to 8D specifically show the instruction code, the operation code, the register write signal, and the register number designation (only the most significant bit) in the arithmetic unit shown in FIG. 1 when employing the SIMD, respectively. The figure which shows.

FIG. 9 is a diagram for briefly explaining the operation of the calculation unit in the arithmetic unit shown in FIG. 1 when the first unused bit use form is employed. FIG.

FIG. 10 is a view for explaining the operation of an instruction code issuing unit (setting unit) and a generating unit in the arithmetic unit shown in FIG. 1 when the first unused bit use form is employed. FIG.

11 (a) to 11 (d) designate command codes, arithmetic codes, register write signals, and register numbers in the arithmetic unit shown in FIG. 1 when employing the first unused bit usage form (highest order bits). Only).

FIG. 12 is a diagram showing a specific example of a combination of calculations by an arithmetic unit in the arithmetic unit shown in FIG. 1 when a first unused bit use form is employed. FIG.

Fig. 13 is a diagram showing a specific example of a combination of calculations by a calculation unit in the arithmetic unit shown in Fig. 1 when the first unused bit use form is adopted.

FIG. 14 is a diagram showing a specific example of a combination of calculations by a calculation unit in the arithmetic unit shown in FIG. 1 when the first unused bit use mode is adopted. FIG.

Fig. 15 is a diagram showing a specific example of the calculation combination by the calculation unit in the arithmetic unit shown in Fig. 1 when the first unused bit use form is adopted.

FIG. 16 is a diagram for easily explaining the operation of the calculation unit in the arithmetic unit shown in FIG. 1 when the second unused bit use form is employed. FIG.

FIG. 17 is a view for explaining the operation of the setting unit and the generation unit in the arithmetic unit shown in FIG. 1 when the second unused bit use form is employed. FIG.

18A to 18D show the instruction code, the operation code, the register write signal, and the register number (highest bit) in the arithmetic unit shown in FIG. 1 when the second unused bit use form is adopted. Only).

FIG. 19 is a diagram for briefly explaining the operation of the calculation unit in the arithmetic unit shown in FIG. 1 when the third unused bit use form is employed. FIG.

FIG. 20 is a diagram for briefly explaining the operation of the calculation unit in the arithmetic unit shown in FIG. 1 when the third unused bit use form is employed. FIG.

FIG. 21 is a view for explaining the operation of an instruction code issuing unit (setting unit) and a generating unit in the arithmetic unit shown in FIG. 1 when the second unused bit use form is employed. FIG.

22A to 22D show an instruction code, an operation code, a register write signal, and a register number designation (highest bit) in the arithmetic unit shown in FIG. 1 when the third unused bit use form is adopted, respectively. Only).

Fig. 23 is a diagram showing a specific example of calculation combination by the calculation unit in the arithmetic unit shown in Fig. 1 when employing the third unused bit usage form.

Fig. 24 is a diagram showing a specific example of a combination of calculations by a calculation unit in the arithmetic unit shown in Fig. 1 when employing a third unused bit use form.

FIG. 25 is a circuit diagram showing a concrete implementation example of a generation unit in the arithmetic unit shown in FIG. 1 when a third unused bit use form is employed. FIG.

<Description of the symbols for the main parts of the drawings>

1: arithmetic unit 10: arithmetic unit

11: register

12b: Normal floating point multiply operators (normal operators, operators)

12e: Extended Floating Point Multiply Operators (Extended Operators, Operators)

20: command code issuing unit (setting unit) 30: generating unit

31, 32, 33, 34: AND circuit (AND gate)

35, 36: exclusive OR circuit (EOR gate)

31a, 32a, 34a, 36a: inversion circuit (NOT gate, inverter)

Claims (10)

A register for storing data to be operated on, a plurality of calculators for performing calculations based on data read from the registers, and the plurality of calculators divide a region of the register into a plurality of commands in one instruction. Has a function of selecting the adoption or non-adoption of the SIMD (Single Instruction stream Multiple Data stream) method for processing the data stream, and indicates the type of data to be read from the register and the operation to be performed by the plurality of calculators And a plurality of calculators, wherein the plurality of arithmetic units are operable to execute a type of operation indicated by the one instruction on the basis of the data indicated by the one instruction, One or more unused bits in the one instruction, which are used when the SIMD method is not employed by the function, but which are not used when the SIMD method is employed, are executed by the SIMD method. A setting unit that sets extension instruction information for executing at least one of the register and the operator instructing execution of an extension process different from the normal process Computing device comprising a. The method of claim 1, Execution of the expansion processing for at least one of the register and the calculator based on the expansion instruction information set in the unused bit by the setting unit and information set in bits other than the unused bit in the one instruction. And a generation unit for generating an extension command for giving an instruction and outputting the command as one command. delete The method of claim 1, Each of the plurality of calculators is a multi-input one-output multiplication operator capable of switching the type of operation according to the operation type code included in the one instruction, And the unused bit is the most significant bit of a register number indicating field indicating each data in the register to be output to each multiplication operator included in the one instruction. The method of claim 1, Each of the plurality of calculators is a multi-input one-output multiplication operator capable of switching the type of operation according to the operation type code included in the one instruction, And the unused bit is the most significant bit of a register number indicating field indicating a storage destination in the register of the result of the operation by each multiplication operator included in the one instruction. The method of claim 4, wherein And the extension instruction information instructs the register to switch data to be output to each multiplication operator to data in an area other than the area of the register corresponding to each multiplication operator. The method of claim 4, wherein And the expansion instruction information gives an instruction to switch the type of operation by each multiplication operator to each multiplication operator. A register for storing data to be operated on, a plurality of calculators for performing calculations based on data read from the registers, and the plurality of calculators divide the register area and use a plurality of data in one instruction. A computing device comprising a function of selecting the adoption or non-adoption of a single instruction stream multiple data stream (SIMD) method for processing a stream, comprising: data of data to be read from the register and operations to be executed by the plurality of calculators; An arithmetic method that receives the one instruction composed of a plurality of bits indicative of a classification, and the plurality of calculators perform the calculation of the classification indicated by the one instruction based on the data indicated by the one instruction; As One or more unused bits in the one instruction, which are used when the SIMD method is not employed by the function, but which are not used when the SIMD method is employed, are executed by the SIMD method. A setting step of setting expansion instruction information for giving execution instructions for expansion processing different from the normal processing to at least one of the register and the operator; Operation method comprising a. The method of claim 8, Execution of the expansion processing for at least one of the register and the calculator based on the expansion instruction information set in the unused bit in the setting step and information set in bits other than the unused bit in the one instruction. And a generating step of generating an extended command for giving an instruction and outputting the same as the one command. delete

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