KR101025918B1 - Structure and Method of forming metal line of the semiconductor device - Google Patents

Abstract

The present invention relates to a metal wiring structure of a semiconductor device and a method of manufacturing the same. In particular, the manufacturing method of the present invention comprises the steps of forming a source / drain junction and a bulk junction in a semiconductor substrate, depositing a first interlayer insulating film and Forming a discharge conductive film connecting the first contact electrodes of the source and the bulk junction to each other on the first interlayer insulating film after forming a first contact electrode perpendicular to these junctions in the insulating film, and depositing a second interlayer insulating film And forming a second contact electrode vertically connected to the first contact electrode or the discharge conductive layer on the second interlayer insulating layer, and then forming a metal wire connected to the second contact electrode on the second interlayer insulating layer. Therefore, the present invention further provides a conductive film for discharging the undischarged carrier by connecting the source and bulk contact electrodes with each other between the contact electrodes connecting the metal wires of the transistors vertically, thereby forming a gap between the multilayer wires through the discharge conductive film. Parasitic capacitance can continue to discharge the undischarged carrier to ground, preventing the transistor from increasing voltage or slowing it down.

Transistors, Source Junction, Bulk, Ground, Discharge

Description

Metal wiring structure of semiconductor device and manufacturing method therefor {Structure and Method of forming metal line of the semiconductor device}             

1 is a vertical cross-sectional view showing a conventional transistor and its wiring structure;

2 is a vertical sectional view showing a wiring structure of a transistor according to the present invention.

* Description of the symbols for the main parts of the drawings *

100 semiconductor substrate 102 device isolation film

104 well 106 gate insulating film

108: gate electrode 110: spacer

112 source and drain junction 114 bulk junction

116: first interlayer insulating film 118: first contact electrode

120: first discharge conductive film 122: second interlayer insulating film

124: second contact electrode 126: first metal wiring

128: third interlayer insulating film 130: third contact electrode

132: second discharge conductive film 134: fourth interlayer insulating film

136: fourth contact electrode 138: second metal wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a metal wiring structure of a semiconductor device capable of high speed operation by reducing parasitic capacitance present between wiring layers in a semiconductor device having a multilayer wiring structure, and a method of manufacturing the same.

At present, since semiconductor devices require high-speed operation at the same time as device size is reduced, in addition to manufacturing with a fine manufacturing technology, the performance of the device itself is greatly improved. Accordingly, the semiconductor device adopts a multi-layered wiring structure to maximize the performance of the device.

1 is a vertical cross-sectional view showing a conventional transistor and its wiring structure, and a transistor and wiring manufacturing process will be described with reference to this.

First, as the semiconductor substrate 10, a device isolation layer 12 is formed in a silicon substrate to define an active region between devices, and the p-well 14 is formed by a well ion implantation process in the substrate between the device isolation layers 12. To form. In the p-well 14, a semiconductor device, for example, a MOS transistor is formed. Accordingly, the gate insulating layer 16 and the gate electrode 18 of the conductive material are sequentially stacked on the p-well 14, and the spacer layer 20 of the insulating material is formed on the side surface thereof. A source / drain junction 22 in which n + impurities are implanted is formed in the p-well 14 between the edge of the gate insulating layer 16 and the device isolation layer 12. A bulk junction 23 is spaced apart from the source junction 22 with the device isolation layer 12 therebetween and implanted with p + impurities.

In order to perform a wiring process on the entire surface of the substrate on which the MOS transistor is formed, at least one or more layers of USG, PSG, BSG, and BPSG are deposited to form first interlayer insulating films 24 and 26. The first interlayer insulating layers 26 and 24 are etched to form contact holes in which the junctions 22 and 23 or the gate electrode 18 of the MOS transistor are exposed. The contact hole is filled with a conductive material, doped polysilicon, or the like, and the surface thereof is planarized to form the contact electrode 28. Then, the metal wiring 30 connected to the contact electrode 28 is formed by a metal wiring manufacturing process. do.

Then, at least one or more layers of TEOS, BSG, PSG, BPSG, etc. are also deposited on the entire surface of the first interlayer insulating film 26 and the metal wiring 30 to form the second interlayer insulating films 32 and 34. The interlayer insulating films 34 and 32 are etched to form contact holes in which the lower contact electrodes 28 are exposed. After filling the inside of the contact hole with a conductive material and planarizing the surface thereof, the contact electrode 36 is formed, and then, a metal is deposited on the second interlayer insulating layer 34 by a metal wiring manufacturing process, and patterned to connect the metal to the contact electrode. The upper metal wiring 38 is formed.

However, semiconductor devices and MOS transistors having such multi-layered metal wiring structures have high voltage consumption and long signal delay times due to parasitic capacitance and wiring resistance charged between the wiring layers, making high-speed operation difficult. At present, the integration of devices also reduces the thickness of the interlayer insulating film between the wirings, which is trapped in the interlayer insulating film due to the interlayer tunneling phenomenon of the carrier, thereby increasing the parasitic capacitance between the wiring layers. Therefore, in order to reduce the parasitic capacitance between wirings, the interlayer insulating material is being researched to replace with a material having a lower dielectric constant than silicon oxide (SiO 2), but it is still difficult to apply.

An object of the present invention is to add a conductive film for discharging the undischarged carrier between the source and the bulk contact electrode of the transistor to solve the problems of the prior art as described above. The present invention provides a metal wiring structure of a semiconductor device that can be operated after being discharged through a film to prevent voltage increase and speed decrease of the semiconductor device due to parasitic capacitance between multilayer wirings.

Another object of the present invention is to form a conductive film for discharging the undischarged carrier between the source and bulk contact electrodes of the transistor, so that the undischarged carrier is always discharged through the discharge conductive film. The present invention provides a method for manufacturing a metal wiring of a semiconductor device that can prevent the voltage increase and the speed decrease of the semiconductor device due to parasitic capacitance.

In order to achieve the above object, the present invention provides a semiconductor device comprising: a first junction and a second junction in which impurities are spaced apart from each other in a semiconductor substrate; A first interlayer insulating film formed on the entire upper surface of the substrate, a first contact electrode vertically connected to the first to third junctions through a contact hole of the first interlayer insulating film, and a first junction and a third junction on the first interlayer insulating film The first to third junctions are formed through contact holes of the discharge conductive film connecting the one contact electrode to each other, the first interlayer insulating film and the second interlayer insulating film formed on the upper surface of the discharge conductive film, and the second interlayer insulating film. And a second contact electrode vertically connected to the contact electrode or the discharge conductive film, and a metal wiring connected to the second contact electrode on the second interlayer insulating film.

The present invention has a multilayer wiring structure in which an interlayer insulating film, a contact electrode, a discharge conductive film, an interlayer insulating film, a contact electrode, and a metal wiring are repeatedly stacked one or more times in sequence, and a discharge conductive film corresponding to the third junction. The connected metal wire is connected to ground.

In order to achieve the above object, the present invention provides a method for forming a semiconductor device comprising: forming a first junction and a second junction in which impurities are implanted spaced apart from each other in a semiconductor substrate, and a third junction in which impurities are implanted and spaced apart from the first junction by a predetermined distance; Depositing a first interlayer insulating film on the entire upper surface of the semiconductor substrate and forming a first contact electrode vertically connected to the first to third junctions through a contact hole of the first interlayer insulating film; Forming a discharge conductive film connecting the first contact electrodes of the third junction to each other; depositing a second interlayer insulating film on the entire upper surface of the first interlayer insulating film and the discharge conductive film; and forming a discharge conductive film through a contact hole of the second interlayer insulating film. Forming a second contact electrode vertically connected to the first contact electrode or the discharge conductive film of the first to third junctions, and a metal layer connected to the second contact electrode on the second interlayer insulating film; A includes forming.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a vertical cross-sectional view showing a wiring structure of a transistor according to the present invention. Referring to this, the multilayer wiring structure of a MOS transistor according to an embodiment of the present invention is as follows.

An isolation layer 102 and a p-well 104 are formed in the silicon substrate 102 as the semiconductor substrate 100, and the gate insulating layer 106 and the gate electrode 108 of the conductive material are formed on the p-well 104. Is laminated. In addition, spacers 110 of an insulating material are formed on side surfaces of the gate electrode 108 and the gate insulating layer 106. N + impurities are implanted into the p-well 104 between the gate electrode 108 edge and the device isolation layer 102 and are spaced apart from each other by the first junction 112 (hereinafter referred to as source junction) and the second junction 112 ( Hereinafter referred to as drain junction). In the p-well 104, a bulk junction is formed, which is a third junction 114 spaced apart from the source junction 112 and spaced apart by a predetermined distance between the device isolation layers 102 and implanted with p + impurities.

The first interlayer insulating layer 116 is deposited on the entire surface of the substrate on which the MOS transistor is formed, and is perpendicular to the source and drain junction 112 and the bulk junction 114 through the contact hole of the first interlayer insulating layer 116. Connected first contact electrodes 118 are formed. A first discharge conductive layer 120 is formed on the first interlayer insulating layer 116 to connect the source junction 112 and the first contact electrodes 118 of the bulk junction 114 to each other. The second interlayer insulating film 122 is formed on the entire surface of the resultant product. A second contact electrode 124 connected to the source junction 112 and the first discharge conductive layer 120 toward the bulk junction 114 is formed through the contact hole of the second interlayer insulating layer 122, and at the same time, the second contact electrode 124 is formed. And a second contact electrode 124 is formed in the drain junction 112 and the gate electrode 108 through the contact holes of the first interlayer insulating layers 122 and 116. A first metal wire 126 connected to the second contact electrode 124 is formed on the second interlayer insulating layer 122.

Next, a third interlayer insulating film 128 is formed on the entire surface of the substrate on which the first metal wiring 126 is formed for the multilayer wiring structure, and the lower first metal wiring 126 is formed through the contact hole of the third interlayer insulating film 128. ) And a third contact electrode 130 is formed. In addition, a second discharge conductive layer 132 is formed on the third interlayer insulating layer 128 to connect the source junction 112 and the third contact electrodes 130 toward the bulk junction 114 to each other. The fourth interlayer insulating film 134 is deposited on the substrate. The fourth contact electrode 136 connected to the second discharge conductive layer 132 is formed through the contact hole of the fourth interlayer insulating layer 134, and at the same time, the contact of the fourth and third interlayer insulating layers 134 and 128 is formed. A fourth contact electrode 136 connected to the first metal wire 126 is formed through the hole. A second metal wire 138 connected to the fourth contact electrode 136 is formed on the fourth interlayer insulating layer 134.

A MOS transistor having a two-layer wiring structure as described above has a multilayer wiring structure by repeatedly laminating an interlayer insulating film, a contact electrode, a discharge conductive film, an interlayer insulating film, a contact electrode, and a metal wiring on the metal wiring.

The MOS transistor, which is a semiconductor device of the present invention, is connected between the source junction 112 and the contact electrodes 118, 124, 130, and 136 of the bulk junction 114 by connecting a ground to a metal wiring corresponding to the bulk junction 114. Carriers not discharged due to parasitic capacitance between wiring layers are continuously discharged to the ground through the first and second discharge conductive layers 120 and 132.

Such a method of manufacturing a semiconductor device having a multilayer wiring structure according to the present invention is as follows.

First, a device isolation layer 102 is formed in the silicon substrate as a semiconductor substrate 100 to define an active region between devices, and a p-well 104 is formed by a well ion implantation process in the substrate between the device isolation layers 102. . And a semiconductor device, eg, a MOS transistor, is formed in the p-well 104. Accordingly, the gate insulating layer 106 and the gate electrode 108 of the conductive material are sequentially stacked on the p-well 104, and the spacer layer 110 of the insulating material is formed on the side surface thereof. A source / drain junction 112 in which an impurity such as n + is implanted is formed in the p-well 104 between the edge of the gate insulating layer 106 and the device isolation layer 102. A bulk junction 114 spaced apart from the source junction 112 is formed with the device isolation layer 102 interposed therebetween.

In order to perform a wiring process on the entire surface of the substrate on which the MOS transistor is formed, at least one layer of USG, PSG, BSG, BPSG, or the like is deposited to form a first interlayer insulating layer 116. A first discharge conductive film 120 is formed on the first interlayer insulating film 116, and TEOS, BSG, PSG, and BPSG are also formed on the entire surface of the first interlayer insulating film 116 and the first discharge conductive film 120. At least one layer or the like is deposited to form a second interlayer insulating film 122. In this case, the first discharge conductive layer 120 is made of doped polysilicon or metal.

Subsequently, the second layer is etched through the discharge conductive layer 120 to etch the first insulating interlayer and the first interlayer insulating layer at a time to form a contact hole in which the source and drain junction 112, the bulk junction 114, or the gate electrode 108 are exposed. do. The contact hole is filled with a conductive material, doped polysilicon, or the like, and the surface thereof is flattened to form the first contact electrode 118. The contact electrode 118 between the bulk junction 114 is connected to the first discharge conductive layer 120.

Next, after forming a contact hole through which the first discharge conductive layer 120 is exposed, a conductive material is embedded to form a second contact electrode 124 connected to the first discharge conductive layer 120. In this case, the second contact electrode 124 connected to the gate electrode 108 or the drain junction 112 is also formed through the contact holes of the second interlayer insulating layer 122 and the first interlayer insulating layer 116.

Next, a metal wire manufacturing process is performed on the entire upper surface of the second interlayer insulating layer 122 to form a first metal wire 126 connected to the second contact electrode 124.

In addition, at least one or more layers of TEOS, BSG, PSG, and BPSG are deposited on the entire upper surface of the second interlayer insulating layer 112 having the first metal wiring 126 to form the third interlayer insulating layer 128 for the multilayer wiring structure. The third interlayer insulating layer 128 is etched to form a contact hole through which the source and bulk side first metal interconnection layers 126 are exposed, and then a third contact connected to the first metal interconnection 126 by filling a conductive material. The electrode 130 is formed.

Next, a second discharge conductive film 132 is formed in which the source and bulk junction-side third contact electrodes 130 are connected to each other by a wire manufacturing process. In this case, the second discharge conductive layer 132 is made of doped polysilicon or metal.

Then, at least one or more layers of TEOS, BSG, PSG, BPSG, etc. are deposited on the entire upper surface of the second discharge conductive film 132 and the third interlayer insulating film 128 to form a fourth interlayer insulating film 134 and inter Etching the insulating layer 134 to form a contact hole through which the source and bulk side second discharge conductive layer 132 is exposed, and then filling the conductive material to connect the fourth contact connected to the second discharge conductive layer 132. An electrode 136 is formed. In this case, a fourth contact electrode 136 connected to the gate electrode or the drain junction side first metal wire 126 is also formed through the contact holes of the fourth interlayer insulating layer 134 and the second interlayer insulating layer 128.

Then, a metal wire manufacturing process is performed on the entire upper surface of the fourth interlayer insulating layer 134 to form a second metal wire 136 connected to the fourth contact electrode 136.

As described above, the present invention provides a discharge conduction by forming a conductive film that connects the source and bulk side contact electrodes to discharge the discharged carriers among the contact electrodes connecting the metal wires of the MOS transistors vertically. The parasitic capacitance between the multilayer interconnections continues to discharge the undischarged carriers to ground through the membrane. Therefore, the present invention can operate at high speed by operating immediately without a separate discharge time.

In addition, since the discharge conductive film connects the source electrodes of the transistors and the contact electrodes of the bulk junctions to each other and the ground power is supplied to these junctions, the discontinuity phenomenon between the gate electrode and the source junction, the drain junction, and the source junction capable of generating parasitic capacitance is eliminated. It can prevent.

Claims (12)

A first junction and a second junction in which impurities are implanted spaced apart from each other in the semiconductor substrate; A third junction spaced apart from the first junction by a predetermined distance and implanted with impurities in the semiconductor substrate; A first interlayer insulating layer formed on the entire upper surface of the semiconductor substrate; A first contact electrode vertically connected to first to third junctions through a contact hole of the first interlayer insulating layer; A discharge conductive layer configured to connect the first contact electrodes of the first and third junctions to each other on the first interlayer insulating layer to discharge the charges of the first junction and the third junction; A second interlayer insulating film formed on the entire upper surface of the first interlayer insulating film and the discharge conductive film; A second contact electrode vertically connected to the first contact electrode or the discharge conductive film of the first to third junctions through the contact hole of the second interlayer insulating film; And And a metal wire connected to the second contact electrode on the second interlayer insulating layer. The metal of the semiconductor device according to claim 1, wherein the interlayer insulating film, the contact electrode, the discharge conductive film, the interlayer insulating film, the contact electrode, and the metal wiring have a multilayer wiring structure in which the metal wiring is repeatedly stacked one or more times in sequence. Wiring structure. The metal wiring structure of a semiconductor device according to claim 1, wherein the metal wiring connected to the discharge conductive film corresponding to the third junction is connected to ground. The metal wiring structure of a semiconductor device according to claim 1, wherein the discharge conductive film is made of doped polysilicon or a metal. The metal wiring structure of a semiconductor device according to claim 1, wherein the first junction is a source junction and the second junction is a drain junction. The metal wiring structure of a semiconductor device according to claim 1, wherein said third junction is a bulk junction. Forming a first junction and a second junction in which impurities are implanted spaced apart from each other in the semiconductor substrate, and a third junction in which impurities are implanted at a predetermined distance from the first junction; Forming a first interlayer insulating film, a discharge conductive film, and a second interlayer insulating film on an entire upper surface of the semiconductor substrate; Etching the second interlayer insulating film and the second interlayer insulating film to form a contact hole; Forming a first contact electrode and a second contact electrode vertically connected to first to third junctions through contact holes of the first interlayer insulating layer; And forming a metal wire connected to the second contact electrode. 8. The semiconductor device according to claim 7, wherein an interlayer insulating film, a contact electrode, a discharge conductive film, an interlayer insulating film, a contact electrode, and a metal wiring are repeatedly stacked one or more times in sequence to form a multilayer wiring structure on the metal wiring. Method of manufacturing metal wiring. The method of claim 7, wherein the metal wire connected to the discharge conductive layer corresponding to the third junction is connected to a ground. The method of claim 7, wherein the discharge conductive film is made of doped polysilicon or a metal. 8. The method of claim 7, wherein the first junction is a source junction and the second junction is a drain junction. 8. The method of claim 7, wherein the third junction is a bulk junction.

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