KR101023075B1 - Image sensor and method for manufacturing the sensor - Google Patents

Abstract

An image sensor and a method of manufacturing the same are disclosed. The method includes forming a metal wiring insulating film on a semiconductor substrate in a pixel region and a logic region, forming metal wirings spaced apart from each other on top of the metal wiring insulating film, and on top of the metal wirings and the metal wiring insulating film. Forming a first interlayer insulating film, removing the first interlayer insulating film existing between the metal wirings in the pixel region, and leaving the first interlayer insulating film existing between the metal wirings in the logic region and in the pixel region. Forming an air gap between the metal wires by forming a second interlayer insulating film on the resultant from which the first interlayer insulating film has been removed, and forming a second interlayer insulating film on the entire upper surface of the semiconductor substrate in the logic region. It features. Therefore, the reliability of the device can be improved by preventing the pattern bridge, the size of the air gap can be adjusted by using the wet etching amount, the air gap forming process can be controlled while the air gap is formed uniformly, and the air gap can be adjusted. The forming process has a simple effect.

Image Sensor, Air Gap, Pixel Area, Logic Area

Description

Image sensor and method for manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a CMOS image sensor (CIS) and a method for manufacturing the same.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal, and is largely a charge coupled device (CCD) and a complementary metal oxide silicon (CMOS) image sensor. It is divided into (Image Sensor). Here, a CCD is a device in which charge carriers are stored and transported in a capacitor while a metal-oxide-silicon (MOS) capacitor is in close proximity to each other, and a CMOS image sensor is a control circuit and a signal processing circuit. ) Is a device that adopts a switching method that uses a CMOS technology that uses) as a peripheral circuit to make MOS transistors as many pixels as possible, and sequentially detects output using the same. Compared to CCD, which is widely used as an image sensor, CMOS image sensor is used in a wide range of products because of various advantages.

On the other hand, the CMOS image sensor is composed of a light sensing portion for detecting light and a logic circuit portion for processing the detected light into an electrical signal to make data. Efforts have been made to increase the fill factor of the area of the photo-sensing part of the entire image sensor device to increase the sensitivity, but this is limited in areas where the logic circuit part cannot be removed. There is a limit to. Therefore, in order to increase the light sensitivity, a light condensing technology that changes the path of light incident to a region other than the light sensing portion and collects the light sensing portion has emerged. Such a technique is a microlens forming technique. In addition, in the image sensor for implementing a color image, a color filter array (CFA) is sequentially arranged on an upper portion of a light sensing portion that receives and receives light from the outside to generate and accumulate an optical charge. The CFA may consist of three color filters, a red filter, a green filter, and a blue filter, or may consist of three color filters, a yellow filter, a purple yellow filter, and a cyan filter. In addition, a microlens is used to increase the light sensitivity of the image sensor on the top of the CFA. Since a general method for manufacturing an image sensor is disclosed in Korean Patent Laid-Open No. 10-2008-0018041, a detailed description thereof will be omitted.

Meanwhile, as the CMOS image sensor shrinks, a capacitance value of the interlayer dielectric (IMD) material adversely affects driving of the device.

1 is a graph showing the capacitance when the IMD is a vacuum (Air-Gap Structure) and the gap fill gap (Oxide) by the high density plasma (HDP: High Density Plasma) method, the horizontal axis represents the total capacitance The vertical axis represents Cumulative Probability, respectively.

Than when the IMD material is vacuumed as shown in FIG. 1. The capacitance is very high as 15pF when the capacitance value is 5 times higher than that of the USG material. This causes the delay of the image sensor. In particular, it is important that the CMOS image sensor does not generate an afterimage according to the movement of the camera. However, if USG, which increases the delay of the time constant RC, is used as the IMD material, legging may occur due to the image being broken. For this reason, CMOS image sensors of 0.11 µm or less have attempted to reduce capacitance by artificially forming voids in the spaces between metal wires.

2A to 2D illustrate process cross-sectional views for describing a method of manufacturing a general CMOS image sensor.

Referring to FIG. 2A, a metal wiring layer 20 such as aluminum (Al) is formed on the silicon semiconductor substrate 10. Thereafter, the metal wiring layer 20 is patterned to form the metal wirings 20 in the pixel region A and the logic region B, as shown in FIG. 2B. Subsequently, a plasma enhanced (CVD) -chemical vapor deposition (CVD) method is performed on the interlayer insulating material layer 40 such as SiO ₂ on the upper surfaces of the metal lines 20 and the exposed semiconductor substrate 10. Form thickly by. At this time, voids 30 and 32 are formed in the interlayer insulating material layer 40. Thus, the voids 30 and 32 formed between the metal wires 20 are referred to as air gaps. Thereafter, as shown in FIG. 2D, the interlayer insulating material layer 40 is planarized to form an interlayer insulating film 40A having air gaps 30 and 32.

When the air gap 32 is formed in the pixel area A, the capacitance value can be reduced to increase the conversion gain when converting the light signal into an electrical signal, thereby improving the resolution of the CMOS image sensor. . However, the general air gap formation method as described above uses a PE-CVD method, so it is not easy to control the air gap formation. In particular, when the air gap is formed in a space less than a specific width, an air gap is formed to an undesired portion, and device degradation such as a W-bridge phenomenon may occur. In addition, in the general method described above, when the air gap 32 is desired only in the pixel region A and the air gap 30 is not desired in the logic region B, the air gap 32 is partially formed. ) Can not be formed alone.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide an image sensor capable of selectively forming an air gap only in a desired area, and a manufacturing method thereof.

In order to achieve the above object, a manufacturing method of an image sensor according to the present invention having a pixel region having a plurality of photodiodes and a logic region for signal processing comprises a metal wiring insulating film on the semiconductor substrate of the pixel region and the logic region. Forming metal wirings spaced apart from each other on top of the metal wiring insulating film; forming a first interlayer insulating film on the metal wirings and the metal wiring insulating film; Removing the first interlayer insulating film existing between the metal wires, leaving the first interlayer insulating film existing between the metal wires of the logic area, and removing the first interlayer insulating film from the pixel area. Forming an air gap between the metal wires by forming a second interlayer insulating film on top of the resultant material; And forming a second interlayer insulating film on the entire upper surface of the semiconductor substrate in the logic region.

According to an aspect of the present invention, there is provided an image sensor comprising: a plurality of photodiodes formed on a semiconductor substrate in a pixel region, logic circuits for signal processing formed on the semiconductor substrate in a logic region, the pixel region and the logic A metal wiring insulating film formed on the semiconductor substrate in a region, metal wirings formed on the pixel region and an upper portion of the metal wiring insulating film in the logic region, spaced apart from each other, between the metal wirings in the logic region, and the metal wiring; And a first interlayer insulating film formed over the insulating film, and a second interlayer insulating film formed over the air gap between the metal lines in the pixel area and over the first interlayer insulating film in the logic area.

The image sensor and its manufacturing method according to the present invention can artificially form an air gap in a desired area, such as a pixel area, and prevent the formation of an air gap in a logic area, thereby preventing pattern bridges, thereby improving reliability of the device. Can improve the

The size of the air gap can be adjusted using a wet etching amount,

Since the air gap is formed by wet etching, the air gap forming process can be controlled while forming the air gap uniformly.

Instead of using a separate mask, an air gap can be formed by a simple patterning technique using a mask for forming a planarization layer, which is used to form a planarization layer of a color filter. The process of forming an air gap at a desired site has a simple effect.

Hereinafter, with reference to the accompanying drawings, an embodiment of a manufacturing method of an image sensor according to the present invention will be described as follows.

3A to 3E illustrate cross-sectional views of a method of manufacturing an image sensor according to an exemplary embodiment of the present invention.

The image sensor is divided into a pixel area A and a logic area B. The pixel region A has a plurality of photodiodes (not shown). Logic region B has logic circuits (not shown) for signal processing.

Referring to FIG. 3A, a pre-metal dielectric layer (PMD) 100 is formed on a semiconductor substrate (not shown) of a pixel region A and a logic region B of an image sensor.

Subsequently, metal wires 110 spaced apart from each other on the metal wire insulating layer 100 are formed in the pixel area A and the logic area B, respectively. For example, at least one of the lower metal layer 112A, the intermediate metal layer 114A (not shown), and the upper metal layer 116A (not shown) is sequentially formed on the metal wiring insulating film 100. Thereafter, the stacked metal layers 112A, 114A, and 116A are patterned by, for example, reactive ion etching (RIE) to form metal wires 110. Each metal line 110 is composed of a patterned lower metal layer 112, a patterned intermediate metal layer 114, and a patterned upper metal layer 116. At least one of the lower metal layer 112 and the upper metal layer 116 may be made of Ti or TiN. In addition, the intermediate metal layer 114 may be made of aluminum (Al).

3B, a first interlayer insulating layer 120 is formed on the metal lines 110 and the metal wiring insulating layer 100. For this purpose, the upper surface of the metal lines 110 and the exposed metal line insulating layer 100 in the pixel region A and the exposed portions of the metal lines 110 and the exposed metal line insulating layer 100 in the logic region B. A first interlayer insulating material layer (not shown) is formed on the entire upper surface. For example, the oxide film may be formed by depositing an oxide film as a material layer for the first interlayer insulating film on the metal wiring insulating film 100 by high density plasma chemical vapor deposition (HDP-CVD). In this case, the first interlayer insulating layer 120 may be planarized by chemical mechanical polishing (CMP) to form the first interlayer insulating layer 120 as illustrated in FIG. 3B.

3C and 3D, the first interlayer insulating layer 120 existing between the metal lines 110 of the pixel region A is removed, and the metal lines of the logic region B are removed. The first interlayer insulating film 120 existing between 110 is left.

For example, in the pixel region A and the logic region B, a photoresist (not shown) is formed on the first interlayer insulating layer 120 illustrated in FIG. 3B. Thereafter, as shown in FIG. 3C, the photoresist is patterned to form an etch mask 130 that exposes the pixel region A and covers the logic region B. Referring to FIG. That is, the etching mask 130 corresponds to the patterned photoresist.

4 is a diagram illustrating an example of a mask for forming a planarization layer used when patterning a photoresist.

In general, an image sensor has a color filter array (not shown) on top of the interlayer insulating films, a planarization layer (not shown) formed on top of the color filter array, and a micro lens formed on the planarization layer. Herein, a method of forming a general planarization layer will be described with reference to FIG. 4.

A planarization layer forming material layer (not shown) is applied to the entire upper surface of the color filter array. Thereafter, a positive type photoresist (not shown) is applied on top of the material layer for forming a planarization layer. Subsequently, as shown in FIG. 4, the photoresist of the positive type is exposed and developed by using a mask in which light is not transmitted to the pixel region A but is transmitted to the logic region B. FIG. Thus, a positive type photoresist pattern covering the pixel region A and opening the logic region B is completed. Using the positive type photoresist pattern as an etching mask, the material for forming the planarization layer is etched, and then the photoresist pattern of the positive tie is removed, and the planarization layer remains in the pixel region A only.

Therefore, in order to form the etching mask 130 covering the logic region B and exposing the pixel region A, as shown in FIG. 3C, a mask for forming a planarization layer as shown in FIG. 4 may be used. . In this case, the photoresist applied to the entire upper surface of the first interlayer insulating film 120 shown in FIG. 3B is of a negative type. Therefore, when the negative type photoresist is developed after exposure using the mask shown in FIG. 4, the etching mask layer opens the pixel region A and covers the logic region B as shown in FIG. 3C. 130 may be formed.

As described above, when the image sensor has a planarization layer, the etch mask 130 illustrated in FIG. 3D may be formed using the planarization layer forming mask illustrated in FIG. 4.

However, if the image sensor does not have a planarization layer, the etch mask 130 passes light through the mask other than the mask shown in FIG. 4, that is, the pixel region A and into the logic region B. It may also be formed using a mask that blocks light. In this case, the photoresist is a positive type.

Thereafter, as illustrated in FIG. 3D, the first interlayer insulating layer 120 of the pixel area A is etched using the etching mask 130.

Thereafter, as shown in FIG. 3E, the second interlayer insulating layer 140B is formed on the resultant 120B from which the first interlayer insulating layer 120 is removed in the pixel region A, and thus, between the metal wires 110. Air gap 150 is formed in the. At the same time, a second interlayer insulating layer 140A is formed on the entire upper surface of the first interlayer insulating layer 120A on the semiconductor substrate in the logic region B. For example, SiO ₂ may be formed as the second interlayer insulating films 140B and 140A on the resultant 120B and the first interlayer insulating film 120A by plasma chemical vapor deposition (PECVD), respectively.

According to the present invention, in the pixel region A illustrated in FIG. 3D, the first interlayer insulating layer 120 may be removed by wet etching. Therefore, the size of the air gap 150 shown in FIG. 3E can be adjusted by the wet etching amount. That is, when the first interlayer insulating layer 120 is completely removed between the metal lines 110 in the pixel area A, the size of the air gap 150 becomes large, and the first interlayer insulating layer 120 is partially removed. If removed, the size of the air gap 150 is reduced.

Hereinafter, with reference to Figure 3e attached to an embodiment of the image sensor according to the present invention will be described as follows.

The image sensor according to the present invention includes a plurality of photodiodes (not shown), logic circuits (not shown), metal wiring insulating film 100, metal wirings 110, first interlayer insulating films 120A and 120B, and second It is composed of the interlayer insulating films 140B and 140A and the air gap 150.

In the image sensor according to the present invention, a photodiode is formed on the semiconductor substrate in the pixel region A, and logic circuits are formed on the semiconductor substrate in the logic region B to process a signal. The metallization insulating film 100 is formed on the semiconductor substrate of the pixel region A and the logic region B. As shown in FIG. The metal lines 110 are formed to be spaced apart from each other on the metal wiring insulating layer 100 of the pixel region A and the logic region B. FIG.

The first interlayer insulating layer 120A is formed on the exposed upper front surface of the metal lines 110 and the metal wiring insulating layer 100 in the logic region B, and the first interlayer insulating layer 120B is the pixel region A. The metal wires 100 and the metal wire insulating layer 100 are partially formed on the metal wires 100.

The second interlayer insulating layer 140B is formed on the upper portion of the air gap 150 between the metal lines 110 in the pixel region A and on the first interlayer insulating layer 120B partially removed. The second interlayer insulating layer 140A is formed on the first interlayer insulating layer 120A in the logic region B.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

FIG. 1 is a graph showing the capacitance when IMD is vacuumed and when the oxide is gapfilled by a high density plasma method.

2A to 2D illustrate process cross-sectional views for describing a method of manufacturing a general CMOS image sensor.

3A to 3E illustrate cross-sectional views of a method of manufacturing an image sensor according to an exemplary embodiment of the present invention.

4 is a diagram illustrating an example of a mask for forming a planarization layer used when patterning a photoresist.

DESCRIPTION OF THE REFERENCE NUMERALS

100: metal wiring insulating film 110: metal wiring

120, 120A, 120B: first interlayer insulating film 130: etching mask

140A, 140B: second interlayer insulating film

Claims (10)

In the manufacturing method of an image sensor having a pixel region having a plurality of photodiodes and a logic region for signal processing, Forming a metallization insulating film on the semiconductor substrate of the pixel region and the logic region; Forming metal wires spaced apart from each other on the metal wire insulating film; Forming a first interlayer insulating film on the metal wires and the metal wire insulating film; Removing the first interlayer insulating film existing between the metal wires in the pixel area, and leaving the first interlayer insulating film existing between the metal wires in the logic area; And A second interlayer insulating film is formed on the resultant from which the first interlayer insulating film is removed in the pixel region, thereby forming an air gap between the metal lines, and a second interlayer insulating film on the upper front surface of the semiconductor substrate in the logic region. Method of manufacturing an image sensor comprising the step of forming a. The method of claim 1, wherein the removing and remaining of the first interlayer insulating film is performed. Forming a photoresist on the first interlayer insulating film; Patterning the photoresist to form an etch mask that exposes the pixel region and covers the logic region; And And etching the first interlayer insulating layer of the pixel area by using the etching mask. The method of claim 2, And a mask used for patterning the photoresist corresponds to a mask for passing light to the logic region, and the photoresist is negative. The method of claim 1, wherein the forming of the metal wires is performed. Sequentially stacking at least one of a lower metal layer, an intermediate metal layer, and an upper metal layer on the metal wiring insulating layer; And And patterning the stacked metal layers to form the metal wires. The method of claim 1, wherein the forming of the first interlayer insulating film is performed. And forming an oxide film as the first interlayer insulating film on the metal wiring insulating film by high density plasma deposition (HDP). The method of claim 1, wherein the forming of the second interlayer insulating film is performed. And forming an oxide film as the second interlayer insulating film on the resultant and the semiconductor substrate by plasma chemical vapor deposition (PECVD). The method of claim 1, wherein the first interlayer insulating layer of the pixel area is removed by wet etching, and the size of the air gap is adjusted by the wet etching amount. The method of claim 4, wherein at least one of the lower metal layer and the upper metal layer is made of Ti or TiN. The method of claim 4, wherein the intermediate metal layer is made of aluminum. A plurality of photodiodes formed on the semiconductor substrate in the pixel region; Logic circuits for signal processing formed on the semiconductor substrate in a logic region; A metal wiring insulating film formed on the semiconductor substrate in the pixel region and the logic region; Metal lines spaced apart from each other on the pixel line and the metal line insulating layer in the logic area; A first interlayer insulating layer formed between the metal lines and on the metal wiring insulating layer in the logic region; And And a second interlayer insulating film formed over the air gap between the metal lines in the pixel area and over the first interlayer insulating film in the logic area.

Images