KR101020627B1 - Driving Circuit For Liquid Crystal Display - Google Patents

Abstract

The present invention provides a driving circuit of a liquid crystal display device having a gate driver for shifting and outputting an input signal. An inverting unit for outputting an inverting signal to output an inverting signal, a pull-up unit for receiving a boosting voltage from a boosting node and outputting a pull-up output signal, and a pull-up pull-down circuit unit for receiving the inverting signal and outputting a pull-down output signal, The inverter unit provides a driving circuit of the liquid crystal display device which outputs a signal having a level lower than the low level signal for a predetermined period in the period in which the pull-up output signal is output.

Gate Driver, Pull Up, Pull Down, Boosting

Description

Driving Circuit for Liquid Crystal Display Device {Driving Circuit For Liquid Crystal Display}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display driving circuit, and more particularly, to a driving circuit of an amorphous silicon TFT liquid crystal display in which a gate driver circuit is integrated in a panel.

Unlike low-temperature polysilicon TFTs, liquid crystal display panels using amorphous silicon (a-Si) TFTs have difficulty in integrating various circuits for driving pixels inside the panel of the liquid crystal display due to low mobility. There was this.

In order to overcome this problem, recent attempts have been actively made to integrate low-frequency regions into a panel, and among them, integrating a gate driver circuit into the panel is most efficiently recognized as a product. It is becoming. The driving circuit of the liquid crystal display device in which the gate driver circuit is integrated according to the prior art is disclosed in Korean Patent No. 705628 of the same applicant.

The gate driver circuit integrated in the LCD panel forms a shift register circuit that increases the width of the TFT and overcomes the effect of bootstrap to overcome low mobility.

1 is a block diagram of a shift resist circuit utilizing a general bootstrap effect. The shift resist circuit using the bootstrap effect can use a two-phase or four-phase scheme. Two phases are two clocks with 180-degree phase difference in which the clock signal used for the synchronization and current supply signals of the shift register operation is synchronized to 1-horizontal time, which is the size of the high level interval of the gate pulse. (Clock) signal is used, and the 4-phase is the same as the 2-phase method in which the clock signal used for the synchronization and current supply signal of the shift register operation is synchronized to the 1-horizontal time, but has a phase difference of 90 degrees. By using four types of clock signals, a clock signal with a high level section is repeated every 4-horizontal time.

FIG. 2A is a graph showing waveforms of a shift register when using a two-phase, and FIG. 2B is a four-phase method.

1, 2A, and 2B, the TFT of the input block 11 is turned off after receiving the front end output (the N-1 or N-2 th output is common) through the input block 11. Switch to to make the bootstrap node (P-node) a floating node. When the clock signal is raised from the low level to the high level in the next horizontal time, the bootstrap node (P-node), which was in a floating state, is ideally at a voltage level of approximately twice the VGH due to the coupling effect with the clock signal. Rise (typically 2VGH-a).

At this time, since the voltage raised by the bootstrap effect is applied to the gate node of the output TFT T11, the output TFT T11 can flow a large amount of current so that the clock signal rises / falls delay time (Rise / Fall Delay). The output node is output to the output node without a great loss of time. Since a signal delay occurs between the input signal and the output signal by 1-horizontal time, the shift register circuit can operate.

Next, a description will be given by taking a Korean Patent No. 705628 of the same cause as a driving circuit having a gate driver circuit in accordance with the prior art. 3 is a driving circuit of the liquid crystal display device of Korean Patent No. 705628.

Referring to FIG. 3, the driving circuit includes eight thin film transistors T1, T2, T3, T4, T5, T6, T7, and T8 and two capacitors C1 and C2. The driving circuit of FIG. 1 includes a pull-up unit T3 for generating a gate high level voltage and a pull-up unit T2 and T4 for generating a gate low voltage. , T3, T4; 130. In order to implement a pull-down function, the output of the NTFT inverter circuits T5 and T6 is used as a control signal.

However, the output signal X of the inverter circuits T5 and T6 is applied to the TFT gate nodes of the pull-down units T2 and T4. At this time, the higher the gate voltage, the better the circuit performance but the stress caused by the gate node bias voltage. As the TFTs deteriorate, reliability deterioration occurs. Usually, when the TFTs of the pull-down sections T2 and T4 are turned off, the Vgs of the TFTs often become 0 V or more, in which case a leakage current exists.

4 is a schematic diagram for explaining a phenomenon in which leakage current increases when the mobility of the I-V characteristic of the TFT increases or the threshold voltage decreases. As shown in FIG. 4, when the mobility increases or the threshold voltage Vth decreases, the I-V characteristic of the TFT decreases circuit performance by increasing leakage current when Vgs is 0V or more.

In addition, when the output of the gate driver integrated with the circuit leakage current components present in the circuits of the pull-down parts T2 and T4 is at a high level, the threshold voltage Vth is small and a factor of increasing mobility such as high temperature occurs. As a result, the gate driver output is attenuated and output.

In order to solve the above problems, the present invention is to provide a driving circuit with excellent reliability while improving circuit performance to exhibit excellent output characteristics.

The main characteristic configuration of the present invention is to adjust the output waveform of the inverter to the signal waveform applied to the pull-down portion of the driving circuit in the period where the output of the shift register becomes a high level, while eliminating the leakage current, In the section where the output goes low level, the output waveform of the inverter is made into an overshoot waveform to improve the reliability by reducing the stress of the pull-down part while reducing the transition delay time of the shift register output from high level to low level. .

According to an aspect of the present invention, there is provided a driving circuit of a liquid crystal display including a gate driver configured to shift and output an input signal, the driving circuit comprising: an input unit configured to receive a pulse input signal including a high level signal and a low level signal and transmit the received pulse input signal to a boosting node; An inverter unit connected to the input unit and outputting an inverting signal by inverting the pulse input signal; A pull-up unit connected to the input unit and the inverter unit, the pull-up unit receiving a boosting voltage from the boosting node to output a pull-up output signal, and a pull-up pull-down circuit unit receiving the inverting signal to output a pull-down output signal; The inverter unit provides a driving circuit of the liquid crystal display that outputs a signal having a level lower than the low level signal for a predetermined period in the period in which the pull-up output signal is output.

Preferably, the inverter unit outputs an overshoot waveform for a predetermined period in a section in which the pull-down output signal is output.

According to another aspect of the present invention, a drain transistor and a gate terminal are commonly connected to an output terminal of an n-1 or n-2th gate line; A second transistor having a drain terminal connected to a source terminal of the first transistor to form a first node (P), and a source terminal connected to a VGL terminal; A first capacitor having a clock signal applied to a first electrode and a second electrode connected to the first node (P); A third transistor having a gate terminal connected to the first node (P), an inverted signal of the clock signal applied to a drain terminal, and a source terminal connected to an n-th gate line; A fourth transistor having a gate connected to the gate of the second transistor to form a second node (X), a drain terminal connected to the n-th gate line, and a source terminal connected to the VGL terminal; A fifth transistor having a gate terminal and a drain terminal connected to a Vbias terminal in common, and a source terminal connected to the second node (X); A sixth transistor connected between the second node and the VGL terminal, and a gate terminal of the sixth transistor connected to a drain terminal of the first transistor; A second capacitor formed between the second node (X) and the gate of the sixth transistor; And a ninth transistor having a gate terminal connected to the first node P, a drain terminal connected to a second node X, and a source terminal connected to an LVGL terminal lower than the VGL voltage. A driving circuit for a liquid crystal display device is provided.

Preferably, a seventh transistor having a gate terminal connected to the n + 1 th gate line and connected in parallel with the second transistor between the first node (P) and the VGL terminal; A gate terminal is further connected to the n + 1 th gate line, and further includes an eighth transistor connected between the Vbias terminal and the second node (X).

In addition, the voltage of the LVGL terminal is characterized in that 0.5 to 5 V lower than the VGL voltage.

According to the present invention, the output waveform of the inverter block applied to the gate node of the TFT in the pull-down function block of the shift register can be formed into an overshoot waveform to reduce the bias stress voltage of the gate node to increase the lifespan. Even when a TFT leakage current increase factor occurs, such as when the leakage current component is removed by a high temperature or a low threshold voltage, the gate output waveform has excellent characteristics without attenuation of the gate output waveform.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the following embodiments of the present invention may be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art.

5 is a block diagram of a driving circuit of a liquid crystal display according to a preferred embodiment of the present invention.

Referring to FIG. 5, the driving circuit includes an input unit 210, an inverting unit 220, and a pull-up pull-down unit 240.

The input unit 210 receives a pulse input signal having a high level (VGH) and a low level (VGL) and transmits the same to a boosting node (P-node), and the inverting unit 220 is connected to the input unit 210. Inverts the pulse input signal and outputs the inverting signal to the X-node. The pull-up pull-down circuit unit 240 is connected to the input unit 210 and the inverter unit 220, respectively, and receives a boosting voltage from a boosting node (P-node) to output a pull-up output signal and a pull-up unit 240a and an inverting signal. It is provided with a pull-down unit 240b for receiving the output to output the pull-down output signal.

Here, the inverter unit 220 outputs a signal having a level LVGL lower than the low level VGL of the pulse input signal input to the input unit 210 for a period of time during the pull-up output signal output period.

The inverter unit 220 may output a signal having an overshoot waveform in a section in which the pull-down output signal is output. Here, the power supply voltage Vbias' applied to the inverter unit 220 outputs the output signal so as to generate an overshoot. For example, a voltage of about 3 to 5 V may be set.

The LVGL voltage has a potential of approximately 0.5 to 5 V below VGL, preferably 1-3 V, and the driver IC uses VGL power supply with low voltage change and noise resistant VGL for stable operation of the shift register. And a method of generating the LVGL potential difference is preferred.

The input unit 210 is effective to have a diode-type input switch using a saturation mode TFT, and a signal is applied when the input signal is at a high level, and signal input is blocked when the input signal is at a low level. After the signal is input to maintain a floating state.

The pull-up unit 240a uses a clock signal as a power source for generating a high level voltage of the gate output waveform. The voltage level of the clock signal is high / low of the gate driving voltage, that is, VGH / VGL. It has a two-level pulse shape. The duty ratio of the clock waveform is approximately 20-50%. As described above, a two-phase or four-phase signal may be used depending on the driving scheme.

FIG. 6 is a detailed configuration diagram of the inverter unit 220 of FIG. 5, and FIG. 7 is a diagram for describing a situation in which an output waveform output from the inverter of FIG. 6 is changed in comparison with the prior art. The left side of FIG. 7 shows the output waveform according to the prior art, and the right side of FIG. 7 shows the output waveform according to the present invention.

Referring to FIG. 6, the inverter unit 220 includes TFTs T21, T22, and T23, and inputs Vbias', an input signal Input, and a bootstrap node P-node of FIG. Send output signal to node. The major difference here is that a TFT (T23) is added and the gate terminal of the TFT (T23) is connected to the bootstrap node (P-node) and the source terminal is smaller than the voltage (VGL) of the source terminal of the TFT (T22). It is connected to the low voltage level LVGL. In addition, the voltage level Vbias to which the drain of the TFT T21 is connected is set so that the X-node output signal has an overshoot as described above.

The inverter unit 220 uses a bootstrap (P-node) as a control signal, and outputs a VGL level using only an input voltage as a control signal in the prior art, and has a potential lower than a voltage of LVGL (Lower VGL: VGL). It is used to eliminate the circuit instability caused by high temperature and Vth reduction by reducing the leakage current by making the inverter circuit output lower than VGL and using Vgs of TFTs in pull-down function block to reduce the leakage current.

8 illustrates an embodiment of a driving circuit of the liquid crystal display according to the present invention. 8 illustrates only basic TFTs and capacitances, and although not shown circuit blocks may be present, parts not necessary for referring to the core idea of the present invention are omitted. In addition, the driving circuit of the liquid crystal display of FIG. 8 is described using nine thin film transistors and two capacitors as an example, and the size of each thin film transistor may be different from each other, and an additional configuration may be included.

The driving circuit of the liquid crystal display of FIG. 8 includes thin film transistors T31, T32, T33, T34, T35, T36, T37, T38, and T39 and two capacitors C31 and C32.

In the first transistor T31, the drain terminal and the gate terminal are commonly connected to the output terminal of the n-1 or n-2th gate line, and the drain terminal of the second transistor T32 is the source of the first transistor T31. The first node P is connected to the terminal, the source terminal is connected to the VGL terminal, the clock signal Clk is applied to the first electrode, and the second electrode is connected to the first node. Is connected to P), a gate terminal of the third transistor T33 is connected to the first node P, an inverted signal Clkb of the clock signal Clk is applied to the drain terminal, and the source terminal is the nth The fourth transistor T34 has a gate connected to the gate of the second transistor T32 to form a second node X, and the drain terminal is connected to the n-th gate line. Is connected to the VGL terminal, and the fifth transistor is connected with the gate terminal to the Vbias terminal. A lane terminal is commonly connected, a source terminal is connected to the second node X, a sixth transistor T36 is connected between the second node and the VGL terminal, and a gate terminal is connected to the first transistor T31. A second capacitor is formed between the second node X and the gate of the sixth transistor T36.

For the convenience of description, the difference from the driving circuit according to the related art of FIG. 3 will be mainly described. The configuration in which the ninth transistor T39 is included in the configuration of the inverter unit 240 is a key difference. In the ninth transistor T39, a gate terminal is connected to the first node P, a drain terminal is connected to the second node X, and a source terminal is connected to an LVGL terminal lower than the VGL voltage.

In addition, the seventh transistor T37 and the eighth transistor T38 may be added for a reset function. The seventh transistor T37 has a gate terminal connected to the n + 1 th gate line, and is connected in parallel with the second transistor T32 between the first node P and the VGL terminal, and the eighth transistor T38. The gate terminal is connected to the n + 1 th gate line, and is connected between the Vbias terminal and the second node (X).

The operation of the driving circuit of the liquid crystal display device of the present invention configured as described above is as follows.

Referring to FIG. 8, the circuit operation is sequentially described. First, an output signal of the n−1 th circuit (not shown) is input through the drain terminal of the first transistor T31.

When the output signal of the n-th circuit (which becomes an input signal based on the n-th circuit of the driving circuit) is input through the first transistor T31, the clock signal Clk is also synchronized with the input signal. Is entered.

When the input signal is a high level signal VGH, the first transistor T31 and the sixth transistor T36 are turned on, the first node P is at the positive level, and the voltage is the first at the VGH voltage. The potential VGH-a is obtained by subtracting the threshold voltage of the transistor T31. On the other hand, the output signal is maintained at a low level because the second node X is at a high level and the third transistor T33 is turned off. The first capacitance C1 and the second capacitance C2 are charged.

At this time, the input signal becomes a low level signal VGL, the first transistor T31 and the sixth transistor T36 are turned off, and the third transistor T33 is connected to the first node P. The output has a high level because it is turned on by the high level voltage and the ClkB signal is high level.

Meanwhile, the gate terminal of the ninth transistor T39 is connected to the first node P and the source terminal is connected to a voltage level LVGL lower than the voltage VGL. This configuration allows the second node X to have a profile as in FIG. 9B.

Meanwhile, when the output signal of the n + 1 th circuit is applied to the seventh transistor T37 and the eighth transistor T38 as a reset signal, the first node P becomes low and the turn of the fifth transistor T5 is turned on. Since the on voltage is lower than the conventional voltage, the second transistor T32 serves as a means for enhancing its function.

At this time, the role of the capacitance Cap of the second capacitor (C2) is formed for the purpose of maintaining and stabilizing the potential level at the node X point, the capacitance of the first capacitor (C1) and the purpose for boosting It is formed as a function for stabilizing off-level characteristics of the output signal (Output).

9A and 9B are graphs showing results of Spice simulation of P-nodes, N-nodes, and output waveforms according to the prior art and embodiments of the present invention.

Referring to FIG. 9A, when the leakage current of the transistor is large or the Vth is small, the floating potential of the bootstrap node (P-node) is collapsed and the output waveform is not properly output. However, in the exemplary embodiment of FIG. As the potential of the bootstrap node (P-node) is maintained as it is, it can be seen that the gate output waveform is stable.

Although the preferred embodiments of the present invention have been described above, it is clear that the present invention can use various changes, modifications, and equivalents, and that the above embodiments can be appropriately modified and applied in the same manner. Accordingly, the above description does not limit the scope of the invention as defined by the limitations of the following claims.

1 is a block diagram of a shift resist circuit utilizing a general bootstrap effect.

FIG. 2A is a graph showing waveforms of a shift register when using a two-phase, and FIG. 2B is a four-phase method.

3 is a driving circuit of the liquid crystal display device of Korean Patent No. 705628.

4 is a schematic diagram for explaining a phenomenon in which leakage current increases when the mobility of the I-V characteristic of the TFT increases or the threshold voltage decreases.

5 is a block diagram of a driving circuit of a liquid crystal display according to a preferred embodiment of the present invention.

FIG. 6 is a detailed configuration diagram of the inverter unit 220 of FIG. 5, and FIG. 7 is a diagram for describing a situation in which an output waveform output from the inverter of FIG. 6 is changed in comparison with the prior art.

8 illustrates an embodiment of a driving circuit of the liquid crystal display according to the present invention.

9A and 9B are graphs showing results of Spice simulation of P-nodes, N-nodes, and output waveforms according to the prior art and embodiments of the present invention.

Claims (5)

delete In a driving circuit of a liquid crystal display device having a gate driver for shifting and outputting an input signal, An input unit configured to receive a pulse input signal including a high level signal and a low level signal, and transmit the received pulse input signal to a boosting node; An inverter unit connected to the input unit and outputting an inverting signal by inverting the pulse input signal; A pull-up unit connected to the input unit and the inverter unit and receiving a boosting voltage from the boosting node to output a pull-up output signal, and a pull-up pull-down circuit unit receiving the inverting signal and outputting a pull-down output signal, The inverter unit outputs a signal having a lower level than the low level signal for a predetermined period in the section where the pull-up output signal is output, and outputs an overshoot for a predetermined period in the section where the pull-down output signal is output. . a first transistor having a drain terminal and a gate terminal connected to the output terminal of the n-1 or n-2 th gate line in common; A second transistor having a drain terminal connected to a source terminal of the first transistor to form a first node (P), and a source terminal connected to a VGL terminal; A first capacitor having a clock signal applied to a first electrode and a second electrode connected to the first node (P); A third transistor having a gate terminal connected to the first node (P), an inverted signal of the clock signal applied to a drain terminal, and a source terminal connected to an n-th gate line; A fourth transistor having a gate connected to the gate of the second transistor to form a second node (X), a drain terminal connected to the n-th gate line, and a source terminal connected to the VGL terminal; A fifth transistor having a gate terminal and a drain terminal connected to the Vbias' terminal in common, and a source terminal connected to the second node (X); A sixth transistor connected between the second node and the VGL terminal, and a gate terminal of the sixth transistor connected to a drain terminal of the first transistor; A second capacitor formed between the second node (X) and the gate of the sixth transistor; And A gate terminal connected to the first node P, a drain terminal connected to the second node X, and a source terminal including a ninth transistor connected to an LVGL terminal lower than the VGL voltage. A drive circuit for a liquid crystal display device characterized by the above-mentioned. The method of claim 3, A seventh transistor having a gate terminal connected to the n + 1 th gate line and connected in parallel with the second transistor between the first node (P) and the VGL terminal; And an eighth transistor connected to the n + 1 th gate line and connected between the Vbias' terminal and the second node (X). The method of claim 3, The voltage of the LVGL terminal is 0.5 to 5 V lower than the VGL voltage driving circuit of the liquid crystal display device.

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