KR101009557B1 - Hybrid multisample/supersample antialiasing - Google Patents

Abstract

Systems and methods for dynamically adjusting the pixel sampling rate during primitive shading may improve image quality or increase shading performance. Hybrid antialiasing is performed by selecting the number of shaded samples per pixel fragment. A combination of supersample and multisample antialiasing is used, where a cluster of subpixel samples (multisamples) is processed for each pass through the fragment shader pipeline. The number of multisamples and shader passes in each cluster can be dynamically determined for each primitive based on the rendering state.

Shading, Primitives, Clusters, Multisamples, Supersamples

Description

Hybrid multisample / supersample antialiasing {HYBRID MULTISAMPLE / SUPERSAMPLE ANTIALIASING}

Overall, embodiments of the present invention relate to antialiasing techniques for graphics processing, and in particular, to dynamically adjusting the number of samples shaded per pixel fragment.

Typically, graphics processors are configured to perform antialiasing by multisampling or supersampling. In multisampling, each pixel fragment is shaded once, and the resulting color value is duplicated for all covered subpixel samples. In supersampling, each pixel fragment is shaded N times, once for each covered subpixel sample.

Multisampling is suitable for anti-aliasing primitive edges because it is important here which samples are covered by the incoming primitive. Typically, the textures are prefiltered such that the shaded color values have a sufficiently low spatial frequency that is adequate once shading per pixel. However, some effects, such as textured alpha transparency and high frequency specular highlights, may have a frequency higher than the pixel frequency to avoid aliasing artifacts, and may require shading to be done at frequencies higher than the pixel frequency. Typically, supersampling is required to avoid these types of aliasing. However, shading at every sample in a pixel results in an excessively high cost, since shading is typically the most expensive operation in rendering. In addition, some supersampling implementations require the input primitive to be processed multiple times, once for each subpixel sample, which results in additional inefficiency. More than one per pixel but less than all samples shading rate may be sufficient to mitigate the causes of the aliasing.

Accordingly, there is a need in the art for a system and method for utilizing pixel shading rates suitable for the current geometry being rendered. The shading rate can be reduced to improve image quality or can be reduced to improve shading performance.

Systems and methods for dynamically adjusting pixel sampling rates during primitive shading improve image quality or increase shading performance. The shading rate can vary anywhere from once per pixel (multisampling) to once per sample (supersampling), or anywhere in between to improve image quality or increase shading performance. Given a specified number of samples per pixel for the render target (image buffer), the number of shader passes is dynamically selected. A combination of supersample and multisample antialiasing is used, and a cluster of subpixel samples (multisamples) is processed for each pass of the fragment shader. Supersample clusters are combined for each pixel to produce anti-aliased pixels.

Various embodiments of the method of the present invention for shading primitives using hybrid antialiasing in a computing device configured to generate multiple samples per pixel are used to receive graphics primitives and antialias each pixel across the graphics primitives. Determining the number of supersample clusters. The graphics primitives are shaded using multiple passes through the fragment shading unit in the computing device, and the number of multiple passes used to generate each hybrid antialiased pixel across the graphics primitives is equal to or less than the number of supersample clusters. to be.

Various embodiments of the present invention include a computing device configured to shade graphics primitives using hybrid antialiasing. The computing device includes a rasterizer coupled to the fragment shading unit. The rasterizer includes a hybrid antialiasing control unit configured to receive the graphics primitives and to determine the number of supersample clusters used to antialias each pillar across the graphics primitives. The fragment shading unit is configured to shade the graphics primitives using multiple passes, wherein the number of multiple passes used to generate each hybrid antialiased pixel across the graphics primitives is less than or equal to the number of supersample clusters.

In a manner in which the features of the invention cited above may be understood in detail, a more specific description of the invention briefly summarized above may refer to embodiments, some of which are illustrated in the accompanying drawings. However, the accompanying drawings show only typical embodiments of the invention, and therefore, are not to be considered as limiting the scope of the invention, as the invention may permit other equally effective embodiments.

In the following description, numerous specific details are set forth in order to provide a more complete understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without one or more of these specific details. In other instances, well known features have not been described in order not to obscure the present invention.

System overview

1 is a block diagram illustrating a computer system 100 configured to implement one or more aspects of the present invention. Computer system 100 includes a central processing unit (CPU) 102 and system memory 104 that communicate over a bus path that includes a memory bridge 105. For example, memory bridge 105, which may be a Northbridge chip, is an I / O (input / output) bridge 107 over a bus or other communication path 106 (eg, a HyperTransport link). Is connected to. For example, I / O bridge 107, which may be a southbridge chip, receives user input from one or more user input devices 108 (eg, keyboard, mouse), and routes the input to path 106. And to the CPU 102 via the memory bridge 105. Parallel processing subsystem 112 is connected to memory bridge 105 via a bus or other communication path 113 (eg, PCI Express, accelerated graphics port, or HyperTransport link), and in one embodiment, parallel processing Subsystem 112 is a graphics subsystem for delivering pixels to display device 110 (eg, a conventional CRT or LCD based monitor). The device driver 103 stored in the system memory 104 stores program instructions as needed for execution by the parallel processing subsystem 112 and processes executed by the CPU 102, such as application programs. Interface between parallel processing subsystem 112 translating them.

System disk 114 is also connected to I / O bridge 107. The switch 116 provides connections between the I / O bridge 107 and other components such as the network adapter 118 and the various add-in cards 120 and 121. Other components (not explicitly shown) may be connected to the I / O bridge 107, including USB or other port connections, CD drive, DVD drive, film recording devices, and the like. The communication paths interconnecting the various components in FIG. 1 may include Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Accelerated Graphics Port (AGP), HyperTransport, or any other bus or point-to-point communication protocol (s). May be implemented using any suitable protocol, such as, and connections between different devices may use other protocols known in the art.

2, an embodiment of a parallel processing subsystem 112 is shown. Parallel processing subsystem 112 includes one or more parallel processing units (PPUs) 202, each of which is coupled to a local parallel processing (PP) memory 204. In general, the parallel processing subsystem includes U PPUs, where U ≧ 1. (In this specification, in many cases, similar objects are denoted by reference numbers identifying such objects and parentheses identifying such cases.) The PPU 202 and the PP memory 204 are examples, for example. For example, it may be implemented using one or more integrated circuit devices such as programmable processors, application specific integrated circuits (ASICs) and memory devices.

As shown in detail with respect to PPU 202 (0), each PPU 202 is connected to a memory bridge 105 (or, in one alternative embodiment, directly to the CPU 102). And a host interface 206 in communication with the rest of the system 100 via 113. In one embodiment, communication path 113 is a PCI-E link in which dedicated lanes are assigned to each PPU 202 as known in the art. Other communication paths may also be used. The host interface 206 generates packets (or other signals) for transmission on the communication path 113, also receives all packets (or other signals) coming from the communication path 113, Send them to the appropriate components of the PPU 202. For example, commands associated with the processing task may be sent to the front end unit 212, and commands associated with memory operations (eg, writing and reading to / from the PP memory 204) may be sent to the memory interface 214. Can be sent to). The host interface 206, the front end unit 212, and the memory interface 214 may generally be of conventional design and are not important to the present invention, and thus detailed descriptions thereof will be omitted.

Each PPU 202 preferably implements a highly parallel processor. As shown in detail with respect to PPU 202 (0), PPU 202 includes C cores 208 (where C ≧ 1). Each processing core 208 can execute multiple (eg, tens or hundreds) threads simultaneously, each thread being an example of a program, and one implementation of the multithreaded processing core 208. Examples are described below. Cores 208 receive processing tasks to be executed via work distribution unit 210, and work distribution unit 210 receives commands defining processing tasks from front end unit 212. Work distribution unit 210 may implement various algorithms for distributing work. For example, in one embodiment, work distribution unit 210 receives a " ready " signal from each core 208 indicating whether the core has sufficient resources to accommodate a new processing task. When a new processing task arrives, the work distribution unit 210 assigns the task to the core 208 asserting the ready signal, and if there is no core 208 asserting the ready signal, the work distribution. Unit 210 maintains a new processing task until the ready signal is asserted by core 208. Those skilled in the art will recognize that other algorithms may be used and that the particular method of distributing the processing tasks that work distribution unit 210 enters is not critical to the present invention.

Core 208 communicates with memory interface 214 to read from or write to various external memory devices. In one embodiment, the memory interface 214 includes an interface adapted to communicate with the local PP memory 204 as well as a connection to the host interface 206, such that the core 208 is a system memory 104 or PPU. Allow 202 to communicate with a memory other than local. Memory interface 214 may generally be of conventional design, and detailed description is omitted.

Core 208 includes, but is not limited to, linear and nonlinear data transformations, filtering of video and / or audio data, modeling operations (e.g., applying physical laws to determine the position, velocity, and other properties of the object). Can be programmed to execute processing tasks related to a wide variety of applications, including image rendering operations (eg, vertex shader, geometry shader, and / or pixel shader programs). The PPU 202 transfers data from the system memory 104 and / or local PP memory 204 to internal (on-chip) memory to process the data, and output the resulting data to the system memory 104 and / or Write back to local PP memory 204, where such data may be accessed by other system components, including, for example, CPU 102 or other parallel processing subsystem 112.

Referring again to FIG. 1, in some embodiments, some or all of the PPUs 202 in the parallel processing subsystem 112 are graphics processors, and such graphics processors are configured to store and update pixel data ( For example, a memory bridge that interacts with a local PP memory 204 (which may be used as a graphics memory including a conventional frame buffer), delivers pixel data to the display device 110, and so forth. 105 and a rendering pipeline that can be configured to perform various tasks related to generating pixel data from graphics data supplied by the CPU 102 and / or system memory 104 via the bus 113. In some embodiments, parallel processing subsystem 112 may include one or more PPUs 202 operating as graphics processors and one or more other PPUs 202 used for general purpose computation. The PPUs 202 may be the same or different, and each PPU 202 may have its own dedicated PP memory device (s) 204 or no any dedicated PP memory device (s). have.

In operation, the CPU 102 is the master processor of the system 100 and controls and coordinates the operations of other system components. In particular, the CPU 102 issues commands to control the operation of the PPU 202. In some embodiments, CPU 102 may access the stream of commands for each PPU 202 to system memory 104, PP memory 204, or both CPU 102 and PPU 202. Write to a pushbuffer (not explicitly shown in FIG. 1) which may be located in another storage location. The PPU 202 reads the command stream from the pushbuffer and executes the commands asynchronously with the operation of the CPU 102. Thus, PPU 202 may be configured to offload processing from CPU 102 to increase processing throughput and / or performance of system 100.

It will be appreciated that the system shown herein is exemplary and that modifications and variations are possible. The connection topology, including the number and arrangement of bridges, can be modified as desired. For example, in some embodiments, system memory 104 is connected directly to CPU 102 without going through a bridge, and other devices communicate with system memory 104 through memory bridge 105 and CPU 102. do. In another alternative topology, parallel processing subsystem 112 is not connected to memory bridge 105, but to I / O bridge 107, or directly to CPU 102. In other embodiments, I / O bridge 107 and memory bridge 105 may be integrated into a single chip. Certain components shown herein are optional, for example, any number of add-in cards or peripheral devices may be supported. In some embodiments, switch 116 is removed and network adapter 118 and add-in cards 120 and 121 are directly connected to I / O bridge 107.

The connection of the PPU 202 to the rest of the system 100 may also vary. In some embodiments, PP system 112 is implemented as an add-in card that can be inserted into an expansion slot of system 100. In other embodiments, PPU 202 may be integrated on a single chip, along with a bus bridge, such as memory bridge 105 or I / O bridge 107. In still other embodiments, some or all elements of PPU 202 may be integrated on a single chip with CPU 102.

The PPU does not include local memory, and may have any amount of local PP memory, and local memory and system memory may be used in any combination. For example, PPU 202 may be a graphics processor in an unified memory architecture (UMA) embodiment, in which embodiment little or no dedicated graphics (PP) memory is provided, and PPU 202 may be a system. The memory will be used exclusively or almost exclusively. In a UMA embodiment, the PPU 202 is integrated into a bridge chip or processor chip, or discrete with a high speed link (e.g. PCI-E) that connects the PPU to system memory, for example, via the bridge chip. It can be provided as a chip.

As mentioned above, any number of PPUs 202 may be included in the parallel processing subsystem. For example, multiple PPUs 202 may be provided on a single add-in card, multiple add-in cards may be connected to the communication path 113, or one or more PPUs 202 may be integrated into the bridge chip. PPUs in multiple PPU systems may be the same or different from one another, for example, different PPUs may have different numbers of cores, different amounts of local PP memory, and the like. If multiple PPUs 202 are present, they may be operated in parallel to process data at higher throughput than is possible with a single PPU 202. Systems that include one or more PPUs 202 may be implemented in various configuration and form elements, including desktops, laptops, or handheld personal computers, servers, workstations, gain consoles, embedded systems, and the like.

Core overview

3 is a block diagram of a core 208 for the parallel processing subsystem 112 of FIG. 2, in accordance with one or more aspects of the present invention. PPU 202 includes a core 208 (or multiple cores 208) configured to execute multiple threads in parallel, wherein the term "thread" executes on an example of context, that is, on a particular input data set. It refers to a specific program. In some embodiments, single-instruction (multi-data) instruction issuance techniques are used to support parallel execution of multiple threads without providing multiple independent instruction units.

In one embodiment, each core 208 comprises an array of P (eg, eight, sixteen, etc.) parallel processing engines 302 configured to receive SIMD instructions from a single instruction unit 312. Include. Each processing engine 302 preferably includes the same set of functional units (eg, arithmetic logic unit, etc.). The functional units may be pipelined so that a new instruction is issued before the previous instruction is terminated, as known in the art. Any combination of functional units may be provided. In one embodiment, functional units are integer and floating point arithmetic (eg, addition and multiplication), comparison operations, Boolean operations (AND, OR, XOR), bit-shifting, and various It supports a variety of operations, including the calculation of algebraic functions (e.g., planar interpolation, trigonometric, exponential, and logarithmic functions, etc.), and the same functional unit hardware may be used to perform different operations. Can be.

Each processing engine 302 uses space in a local register file (LRF) 304 to store its local input data, intermediate results, and the like. In one embodiment, local register file 304 is physically or logically divided into P lanes, each lane having several entries (where each entry may store a 32-bit word, for example). ). One lane is assigned to each processing engine 302, and corresponding entries in different lanes can be populated with data for different threads executing the same program to facilitate SIMD execution. In some embodiments, each processing engine 302 can only access the LRF entries of the lane assigned to it. Advantageously, the total number of entries in local register file 304 is large enough to support multiple concurrent threads per processing engine 302.

Each processing engine 302 also accesses on-chip shared memory 306 that is shared among all processing engines 302 in the core 208. The shared memory 306 can be as large as desired, and in some embodiments, any processing engine 302 can have the same low latency (eg, compared to accessing the local register file 304). Can read from or write to any location in shared memory 306. In some embodiments, shared memory 306 is implemented as a shared register file, and in other embodiments, shared memory 306 may be implemented using shared cache memory.

In addition to the shared memory 306, some embodiments also provide additional on-chip parameter memory and / or cache (s) 308, which may be implemented, for example, as conventional RAM or cache. Parameter memory / cache 308 may be used to maintain state parameters and / or other data (eg, various constants) that may be needed, for example, by multiple threads. The processing engine 302 also accesses off-chip “global” memory via the memory interface 214, which may be, for example, the PP memory 204 and / or the system memory 104. And the system memory 104 is accessible via the host interface 206. It should be understood that any memory external to the PPU 202 can be used as the global memory.

In one embodiment, each processing engine 302 is multithreaded and, for example, by maintaining the current state information associated with each thread in different portions of its allocated lanes in the local register file 304. You can run up to any number of G threads (for example, 24). Advantageously, the processing engines 302 are designed to quickly switch from one thread to another so that instructions from different threads can be issued in any sequence without losing efficiency. Since each thread can correspond to a different context, multiple contexts can be processed over multiple cycles as different threads are issued during each cycle.

The instruction unit 312 is configured such that during any given processing cycle, an instruction INSTR is issued to each of the P processing engines 302. Each processing engine 302 may receive different instructions for any given processing cycle when multiple contexts are being processed at the same time. When all P processing engines 302 process a single context, core 208 implements a P-way SIMD microarchitecture. Since each processing engine 302 is also multithreaded to support up to G threads simultaneously, in this embodiment the core 208 may have up to P * G threads running simultaneously. For example, if P = 16 and G = 24, core 208 supports up to 384 concurrent threads during a single context or up to N * 24 concurrent threads for each context, where N is the processing assigned to the context. The number of engines 302.

Advantageously, the operation of the core 208 is controlled via the job distribution unit 200. In some embodiments, work distribution unit 200 not only pointers to data to be processed (eg, primitive data, vertex data and / or pixel data), but also how the data is to be processed (eg, It also receives the locations of the pushbuffers that contain data or instructions that define which program will run). Work distribution unit 210 may load data to be processed into shared memory 306 and load parameters into parameter memory 308. The work distribution unit 210 also initializes each new context in the instruction unit 312 and then signals the instruction unit 312 to begin execution of the context. The instruction unit 312 reads the instruction pushbuffers and executes the instructions to generate processed data. When execution of the context is complete, the core 208 advantageously notifies the work distribution unit 210. Work distribution unit 210 may then initiate other processes, for example, to retrieve output data from shared memory 306 and / or to prepare core 208 for execution of additional contexts. have.

It will be appreciated that the parallel processing unit and core architecture described herein are illustrative and that variations and modifications are possible. Any number of processing engines can be included. In some embodiments, each processing engine 302 has its own local register file, and the allocation of local register file entries per thread may be fixed or configurable as needed. In particular, entries in local register file 304 may be allocated for processing each context. In addition, although only one core 208 is shown, the PPU 202 may include any number of cores 208, and advantageously the cores 208 may have any core ( 208 are of the same design so as not to depend on whether they receive a particular processing task. Advantageously, each core 208 operates independently of the other cores 208 and has its own processing engines, shared memory, and the like.

Graphic pipeline architecture

4 is a conceptual diagram of a graphics processing pipeline 400 in accordance with one or more aspects of the present invention. PPU 202 may be configured to form graphics processing pipeline 400. For example, the core 208 may be configured to perform one or more functions of the vertex processing unit 444, the geometry processing unit 448, and the fragment processing unit 460. . The functions of the data assembler 442, the primitive assembler 446, the rasterizer 455, and the raster computation unit 465 may also be performed by the core 208. Alternatively, graphics processing pipeline 400 may include vertex processing unit 444, geometry processing unit 448, fragment processing unit 460, data assembler 442, primitive assembler 446, rasterizer 455. And dedicated processing units for one or more of the raster computation units 465.

The data assembler 442 is a processing unit that collects vertex data for high-order surfaces, primitives, and the like and outputs the vertex data to the vertex processing unit 444. Vertex processing unit 444 is a programmable execution unit configured to convert vertex data as specified by vertex shader programs by executing vertex shader programs. For example, vertex processing unit 444 converts vertex data from an object based coordinate representation (object space) into an alternate based coordinate system, such as world space or normalized device coordinates (NDC) space. can be programmed to convert to an alternately based coordinate system. Vertex processing unit 444 can read data stored in PP memory 204 or system memory 104 for use in processing vertex data.

The primitive assembler 446 constructs graphic primitives, such as points, lines, triangles, etc., for receiving the processed vertex data from the vertex processing unit 444 and processing by the geometry processing unit 448. Geometry processing unit 448 is a programmable execution unit configured to transform graphics primitives received from primitive assembler 446 as specified by geometry shader programs by executing geometry shader programs. For example, geometry processing unit 448 may be programmed to subdivide the graphic primitives into one or more new graphic primitives and calculate parameters such as plane equation coefficients used to rasterize the new graphic primitives. Can be. In some embodiments of the invention, geometry processing unit 448 may also add or remove elements from the geometry stream. Geometry processing unit 448 outputs parameters and vertices that specify new graphics primitives to rasterizer 455 or memory interface 214. Geometry processing unit 448 may read data stored in PP memory 204 or system memory 104 for use in processing geometry data.

The rasterizer 455 scan converts new graphics primitives and outputs fragments and coverage data to the fragment processing unit 260. When antialiasing is used to generate image data, rasterizer 455 is configured to generate sub-pixel sample coverage data. When hybrid antialiasing is used, a hybrid antialiasing control unit 500 that may be present in the rasterizer 455 is used to process each primitive, as described in conjunction with FIGS. 5C and 6. Configured to determine the number of passes through the fragment processing unit 460.

The fragment processing unit 460 is a programmable execution unit configured to convert fragments received from the rasterizer 455 as specified by the fragment shader programs by executing fragment shader programs. For example, the fragment processing unit 460 performs shading that is output to the raster calculation unit 465 by performing operations such as perspective correction, texture mapping, shading, blending, and the like. It can be programmed to generate fragments. Fragment processing unit 460 may read data stored in PP memory 204 or system memory 104 for use in processing fragment data. The fragments may be shaded at pixel, sample, or supersample cluster granularity, depending on the sampling rate selected by the hybrid antialiasing control unit.

Memory interface 214 generates read requests for data stored in graphics memory and performs texture filtering operations, such as bilinear, trilinear, anisotropic, and the like. In some embodiments of the invention, memory interface 214 may be configured to decompress data. In particular, memory interface 214 may be configured to decompress fixed length block encoded data, such as compressed data represented in the DXT format. Raster operation unit 465 is a processing unit that performs raster operations such as stencils, z tests, etc. and outputs the pixel data as processed graphic data for storage in graphics memory. The processed graphic data is for display on the display device 110 or for further processing by the CPU 102 or the parallel processing subsystem 112, for example graphics memory, eg, PP memory 204 and / or system memory. And stored at 104. In some embodiments of the present invention, raster computing unit 465 is configured to compress z or color data written to memory and decompress z or color data read from memory.

hybrid Anti-aliasing

As previously described, the PPU 202 may be configured to perform shading at various sampling rates to improve image quality or to improve shading performance. The hybrid antialiasing control unit determines the number of shader passes used to shade each pixel in the primitive. As a fragment processing unit 460 for each pass, a supersample cluster of one or more multisamples (sub-pixel samples) per pixel produces a single shader color value that is replicated for all multisamples in the supersample cluster. It is processed by the configured core 208. After the scene is rendered, the samples for the supersample clusters are combined to create an antialiased image.

The number of sub-pixel samples and shader passes for each primitive is increased to improve image quality. The number of sub-pixel samples is determined when the application is launched and is consistent for each pixel of the render target (image buffer). The hybrid antialiasing control unit can dynamically determine the number of shading passes based on the rendering state, eg, alpha test enable / disable, texture map content, user provided quality / performance controls, and the like.

5A illustrates supersample clusters 503 and 511 and multisamples 502, 504, and 513 in pixel 501, in accordance with one or more aspects of the present invention. When eight sub-pixel sample antialiasing is used, various different combinations of multisample and supersample clusters may be used to generate eight sub-pixel samples. In the example shown in FIG. 5A, the three supersample clusters 503 and the supersample cluster 511 each have a supersample cluster 511, for a total of eight sub-pixel sample positions with the pixel 501. ) Include two multisamples, such as multisamples 502 and 504. The other eight sub-pixel sample configurations include eight many supersample clusters each with one multisample or one small supersample cluster with eight multisamples. Shading is performed once for each supersample cluster, and the shaded value, eg, color, is stored for all multisamples in the supersample cluster.

Shader attributes may be sampled at the location of a particular multisample within the supersample cluster, or may be sampled at some other location within or near the supersample cluster. For example, fragment attributes (color, texture coordinates, etc.) in FIG. 5A may be sampled at solid multisample locations, such as multisample 502 in supersample cluster 511. Also, when fragments only partially cover a supersample cluster, it is beneficial to adjust the location where the attributes are sampled so that they lie within the area of covered multisamples in the supersample cluster. This is commonly known as centroid sampling, which term applies here to supersample clusters rather than whole pixel fragments.

5B illustrates fragment 509 and centroid location 517 in supersample cluster 511, in accordance with one or more aspects of the present invention. In some embodiments of the invention, centroid sampling is used to modify the position where the attributes are evaluated to better correspond to the screen area actually covered by the fragment. In some embodiments of the invention, the sample interpolation unit 510 may be configured to sample each supersample cluster at a particular multisample position or approximate centroid position.

The centroid may be a geometric centroid of the covered multisamples, or may be approximated, for example, by selecting the covered multisample in the supersample cluster closest to the centroid of the fully covered supersample cluster. For example, the centroid position 517 is a multisample position calculated at the geometric center of the supersample cluster 511 that is used to represent the sampled color for the supersample cluster 511, because This is because the location of the multisample 502 is near the edge and not near the center of the fragment 509. The shaded value is calculated at the centroid position 517 to more accurately represent the fragment color compared to the multisample 502.

5C is a block diagram of a portion of a graphics processing pipeline 400 that includes a rasterizer 455, a fragment processing unit 460, and a raster computation unit 465, in accordance with one or more aspects of the present invention. Other processing units may be included within the rasterizer 455, the fragment processing unit 460, and the raster calculation unit 465. Their other processing units are not shown in FIG. 5C because they can generally be of a conventional design, and detailed descriptions that are not important to the present invention are omitted.

Rasterizer 455 receives primitives from geometry processing unit 448 and generates fragments for each pixel that the primitives traverse. The hybrid antialiasing control unit 500 (optionally in the rasterizer 455) can be used to render states such as alpha test enable / disable, texture map content, user provided quality / performance controls, etc. Based on the number of shader passes used to process the fragments of each primitive.

Hybrid antialiasing control unit 500 improves antialiasing efficiency by performing more shading passes for primitives that benefit from higher shading rate and reducing the shading rate for other primitives. Hybrid antialiasing control unit 500 may be configured to operate with various quality settings by user, application, or device driver 103. These may range from the lowest quality setting "multisample-always" to the highest quality setting "supersample-always." Intermediate quality settings may take into account the render pipeline state in determining the number of shading passes. For example, if an alpha test or shader pixel kill is enabled, more shading passes may be desirable. Conversely, when high performance is specified, alpha test and shader pixel kills are disabled and the sampling rate can be reduced by the hybrid antialias control unit 500. Hybrid antialiasing control unit 500 may also take into account the characteristics of pixel shader or texture sampler settings in determining the number of shading passes. Those skilled in the art will appreciate that various criteria may be used by the hybrid antialias control unit 500 to determine the number of shading passes. In conventional graphics systems, the sampling rate is determined for all primitives of the scene based on user provided or fixed settings. In addition, sampling for conventional systems is limited to multisampling or supersampling and there are no intermediate alternatives.

In one embodiment, rasterizer 455 generates 2x2 quads of pixel fragments received by hybrid antialias repeater unit 515. When the hybrid antialias control unit 500 sets passes = 1 (ie, when multisampling), the hybrid antialias repeater unit 515 is these quads that are not modified by the fragment processing unit 460. Pass them. However, when the hybrid antialiasing control unit 500 sets the passes to N> 1, the hybrid antialias repeater unit 515 includes the number of passes corresponding to the shader pass to fragment processing unit 460. Print each quad several times. The hybrid antialias repeater unit 515 may mask the coverage sent to the fragment processing unit 460 such that only multisamples in the supersample cluster corresponding to the current pass are enabled. In other embodiments, fragment processing unit 460 may mask coverage based on the number of passes provided to it by hybrid antialias repeater unit 515. Note that other embodiments may repeat for regions other than 2x2 fragment quads, such as single pixels, 4x4 fragment tiles, and the like. Iterating over regions (quads) of pixels other than primitives can be beneficial because the texture map data is likely to be reused for subsequent shader passes for a particular quad, while Iterating over the primitives that can be is because the texture data can be re-fetched from memory, eg, PP memory 204 or system memory 104.

Importantly, the geometry calculations needed to generate the fragments are not repeated for each shader pass. Conversely, conventional systems that supersample into a multisample buffer using a sample mask typically repeat geometry calculations for each shader pass. The primitive attributes sampled to the fragment processing unit 460 need to be calculated only once, regardless of the number of hybrid antialiasing passes, since they will be referenced by subsequent repeated quads and then discarded. Pay attention.

The sample lookup table of the fragment processing unit 460 uses the hybrid antialiasing parameters and the number of passes to determine where the interpolated fragment parameters are sampled. The sample lookup table 505 may select the centroid position or multisample position for each supersample cluster. The multisample locations may include one or more interpolated parameters for each supersample cluster, eg, color channels (red, green, blue, alpha), texture coordinates, etc. (ie, for each pixel in the pixel quad. One set of interpolated parameters) is output to the sample interpolation unit 510. Shader 520 processes the set of interpolated parameters for each pixel in the pixel quad using techniques known to those of ordinary skill in the art to execute fragment shader programs, and the like, for each supersample cluster. Produces a shaded pixel value, for example a color.

Sub-pixel samples for each supersample cluster during shading are the result of shader pixel kill or alpha testing such that raster-generated coverage is modified to generate post-shader coverage based on pixel kill or alpha test results. It may be removed (culled or killed). Because supersample clusters are processed in separate passes through shader 520, supersample clusters can be removed individually during alpha testing. Conversely, when processing all sub-pixel samples in a single shading pass using conventional multisampling, all the sub-pixel samples are retained or removed, resulting in a less precise alpha testing granularity that produces a lower quality image. do.

Shader 520 outputs the shaded pixel values and sub-pixel coverage (possibly modified compared to the coverage provided by rasterizer 455) to color buffer 535 and coverage collector 530, respectively. . The coverage collector 530 accumulates post-shader coverage for each shader pass to generate the collected coverage information for each pixel. Color buffer 535 accumulates shaded values for each pixel. When the shaded values for the last shader pass are received, the collected coverage information is output to the raster computation unit 465. The shaded values for the pixel quad may be output with the collected coverage information or later, for example, after z testing is completed by the raster computation unit 465. In other embodiments of the invention, the coverage collector 530 and the color buffer 535 may be omitted.

Coverage collection and coalescing of color values into the color buffer is beneficial in systems that pack samples of each pixel together into memory so that multiple samples can be written or read using a single memory transaction. Other embodiments may omit the coverage collector 530. Coverage collector 530 is less advantageous in systems that do not constantly store sample values for a pixel in memory.

The optional z / color compression unit 55 in the raster calculation unit 465 receives the collected coverage information and z values, or other representation of z or depth values for the fragments (followed by z testing), and the area of the pixels. Produces compressed z values for. The z / color compression unit 550 can also receive the collected color values for the fragments and generate compressed color values for the area of pixels. Compression can be improved when applied to a large group of pixels. Thus, several pixel quads can be collected together and z tested before the result is compressed. Importantly, hybrid antialiasing does not interfere or reduce the efficiency of z compression. z compression is preferably used to reduce memory bandwidth requirements for accessing the z buffer, and in some embodiments, so does the memory footprint.

6 is a flowchart of method steps for performing hybrid antialiasing, in accordance with one or more aspects of the present invention. In step 610, the hybrid antialiasing control unit 500 receives the primitives. In step 615, hybrid antialiasing control unit 500 determines whether hybrid antialiasing is enabled, and if not, processes the fragment using conventional antialiasing. In step 615, if hybrid antialiasing is enabled, in step 635 the hybrid antialiasing control unit 500 determines hybrid antialiasing parameters for the primitive. Specifically, the hybrid antialiasing control unit 500 determines the number of supersample clusters (shader passes) used when shading each pixel across the primitive.

At step 640, rasterizer 455 generates simple level coverage for the covered portions of the primitive. The granularity of this coverage may be coarse or fine, but at least the size of a pixel quad. Rasterizer 455 outputs coverage information for the quad across the primitive to hybrid antialias repeater unit 515. The hybrid antialias repeater unit 515 enlarges each quad based on the hybrid antialias parameters to shade the quad in multiple passes. The hybrid antialias repeater unit 515 may be configured to skip shader passes if all of the multisamples in the supersample cluster are not covered, according to the coverage information. In step 643, the hybrid antialias repeater unit 515 determines the number of passes (first, second, etc.) and outputs the pixel quad and the number of passes to the fragment processing unit 460. As described above, when the number of passes is greater than one, the hybrid antialias repeater unit 515 may mask coverage information. The sample lookup table 505 is indexed using the number of passes and the number of multisamples to determine the programmed value for the multisample locations, including an indication of the location in the supersample cluster used to interpolate the fragment parameters. It is poisonous. The interpolated parameters are calculated for the supersample cluster by the sample interpolation unit 510.

In step 645, fragment processing unit 460 shades the pixel quad to generate a shaded value for each supersample cluster, i.e. one shaded value for each pixel in the pixel quad. Within a supersample cluster, the shaded value will be used for each multisample covered by the primitive. Fragment processing unit 460 also outputs post shader coverage for the pixel quad. Post shader coverage may differ from rasterized pixel coverage information because multisamples may be removed during shading as described above.

In step 650, hybrid antialias repeater unit 515 determines whether to use a different shader pass to process the pixel quad, and if so, steps 643 and 645 allow for different shader passes (second and second). 3, etc.). In step 650, if the hybrid antialias repeater unit 515 determines that no other shader pass is needed to process the pixel quad, then in step 660 the coverage collector 530 for each shader pass. Combine post shader coverage to generate the collected coverage information for the pixel quad. At step 660, coverage collector 530 also combines the post shader color values for each shader pass to generate the collected color values for the pixel quad. The coverage collector 530 may be configured to collect post shader color and coverage information at multiple quad levels. In step 665, the raster operation unit 465 performs a raster operation to determine which shader values will be written to the frame buffer. Raster operations can be performed at the quad or multi quad level. Z / color compression unit 550 in raster calculation unit 465 may be used to compress z and / or color data for a pixel quad before z and / or color data is stored in the z buffer and / or color buffer. Can be.

In step 670, rasterizer 455 determines if another pixel quad intersects the primitive, and if so, in step 640, rasterizer 455 processes the different pixel quads covered by the primitive. At step 670, rasterizer 455 determines whether all of the pixel quads that the primitive traverses have been shaded, and then at step 675, primitive processing is complete. In a pipeline system, one or more of the steps shown in FIG. 6 may be performed in parallel for different quads.

The hybrid antialiasing control unit 500 may perform hybrid antialiasing parameters, e.g., for each primitive based on the rendering state, i.e., alpha test enable / disable, texture map content, user provided quality / performance controls, etc. It is possible to dynamically determine the number of supersample clusters per pixel. Adapting antialiasing based on the rendering state improves efficiency, because primitives that benefit from high quality antialiasing are shaded with more samples, while other primitives are shaded with fewer samples to optimize image quality and performance. Because.

The present invention has been described above with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made thereto without departing from the broad spirit and scope of the invention as set forth in the appended claims. One embodiment of the invention may be implemented as a program product for use with a computer system. The program (s) of the program product define the functionality of the embodiments (including the methods described herein) and may be included on various cup computer readable storage media. Exemplary computer readable storage media include (i) non-writable storage media (CD-ROM disks, flash memories, ROM chips or other types of solid state nonvolatile semiconductor memory readable by a CD-ROM drive) in which information is stored permanently. Read-only memory devices in the same computer) and (ii) recordable storage media (e.g., floppy disks in a diskette drive or hard disk drive or any type of solid state random access semiconductor memory) for storing changeable information. However, it is not limited thereto. The description and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

1 is a block diagram illustrating a computer system configured to implement one or more aspects of the present invention.

2 is a block diagram of a parallel processing subsystem for the computer system of FIG. 1, in accordance with one or more aspects of the present invention.

3 is a block diagram of a core for the parallel processing subsystem of FIG. 2, in accordance with one or more aspects of the present invention.

4 is a conceptual diagram of a graphics processing pipeline, in accordance with one or more aspects of the present invention.

5A illustrates a supersample cluster and multisample locations within a pixel in accordance with one or more aspects of the present invention.

5B illustrates fragment and centroid positions within a multisample cluster in accordance with one or more aspects of the present invention.

5C is a block diagram of a portion of a graphics processing pipeline in accordance with one or more aspects of the present invention.

6 is a flow diagram of method steps for performing hybrid antialiasing in accordance with one or more aspects of the present invention.

<Explanation of symbols for the main parts of the drawings>

400: graphics processing pipeline

442: Data Assembler

444: vertex processing unit

446 primitive assembler

448: geometry processing unit

455: rasterizer

460: fragment processing unit

465 raster calculation unit

Claims (10)

A computing device configured to shade graphics primitives using hybrid antialiasing, the computing device comprising: Rasterizer comprising a hybrid antialias control unit-The hybrid antialias control unit, Receive the graphic primitives; Determine a number of supersample clusters used for antialiasing each pixel across the graphic primitives; Determine a number of multisamples used to process graphic primitives for each of the supersample clusters; And A fragment shading unit coupled to the rasterizer, the fragment shading unit configured to shade the graphic primitives using a plurality of passes through the fragment shading unit. Including, A computing device in which the number of multiple passes used to generate each hybrid antialiased pixel across the graphics primitives is less than or equal to the number of supersample clusters. The method of claim 1, And said number of supersample clusters is determined based on a rendering state of said computing device. The method of claim 2, And the rendering state comprises one or more of high quality mode setting, high performance setting, alpha testing setting, and use of a texture map comprising high frequency content. The method of claim 1, And the fragment shading unit is further configured to generate post-shader coverage indicating which of the multisamples are covered by a graphic primitive for each of the supersample clusters. The method of claim 4, wherein A raster computation unit coupled to the fragment shading unit and configured to z test graphics primitives for each of the multisamples covered by a graphics primitive, in accordance with the post shader coverage, to generate z tested values. Computing device. The method of claim 5, And the raster computing unit is further configured to compress z tested values for a portion of a z buffer across each of the graphics primitives. The method of claim 1, The number of supersample clusters used for antialiasing each pixel across the first graphics primitive among the graphic primitives is the supersample used for antialiasing each pixel across the second graphics primitive among the graphics primitives. Computing device different from the number of clouters. The method of claim 1, The number of passes used to generate each hybrid antialiased pixel across the graphics primitive does not include a pass for any supersample cluster without one or more multisamples covered by the graphics primitive. . The method of claim 1, The fragment shading unit calculates the shaded value for only one of the multisamples in each cluster of the supersample clusters and duplicates the shaded value for other multisamples in the same supersample cluster. The computing device further configured to shade. The method of claim 1, The fragment shading unit may be configured to obtain a shaded value for a first supersample cluster of the supersample clusters. Use a location of a first multisample in the first supersample cluster; Using a centroid, which is a geometric centroid of the multisamples in the first supersample cluster covered by a graphics primitive; or And calculate using an approximate centroid that is covered by a graphics primitive and is a multisample within the first supersample cluster closest to the geometric centroid of the first supersample cluster.

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