KR101008574B1 - Aes encryption method using multi-processor - Google Patents

Abstract

PURPOSE: An AES(Advanced Encryption Standard) encryption method using multi-processor is provided to improve processing speed while reducing useless data exchanges between processors by embodying AES encryption algorithm as multi-processor. CONSTITUTION: A state is divided by selecting each element(10a,10b,10c,10d) to be processed at each processor. Each processor performs conversions required for the AES encryption for the divided state. A round key is added to the conversion result. One column vector(12a) is successively selected according to the each result of the processes. Each processor receives the state elements which is necessary for the next stage of the AES encryption work, and performs division work.

Description

AES encryption method using multi-processor

The present invention relates to an advanced encryption standard (AES) encryption method, and more particularly, to a method for performing an AES encryption algorithm using a multiprocessor.

AES (Advanced Encryption Standard) encryption algorithm has largely used a T-look-up method and a transposed method. T-Lookup is a method proposed by Gladman that implements AES 4 * 4 byte sized two-dimensional array in the vertical direction (column vector). This method improves the computation speed by configuring one subbyte, MixColumn, and inverse SubByte and Inverse MixColumn as a table. However, this method requires several Kbytes of tables.

The transposition method is proposed by Bertoni. Unlike the T-lookup, the AES state is implemented in the horizontal direction (row vector) to reduce the size of the table required for the operation and to T-lookup in a system with limited cache memory. Compared to the fast features.

In general, multiple processors are used to improve the operation speed and lower the operation clock. However, the T-lookup or pre-positioned AES method is not implemented in multiple processors.

SUMMARY OF THE INVENTION An object of the present invention is to provide an AES encryption method using multiple processors that divides a state into multiple processors in AES operation and calculates and recombines them, thereby reducing unnecessary data exchange between processors and allocating load computations similarly between processors. .

In order to achieve the above object, the present invention provides a method for AES encryption using multiple processors, comprising: selecting elements to be processed in each processor for a state and dividing the state; Performing, by each processor, transformations necessary for AES encryption on the partitioned state; Adding a round key to the result of the transformations being completed; Selecting one column vector sequentially for each processor from the result of the addition; And each processor receiving the state elements necessary for the next round of AES encryption from other processors and repeating the above processes.

In order to achieve the above object, the present invention provides a method for AES encryption using multiple processors, comprising: dividing a row vector of a state by the number of multiple processors, respectively; Performing transformations for AES encryption on the divided row vectors, respectively; Each processor calculating a row vector processed by the processor and row vectors transferred from other processors, and updating the row vector processed by the processor first; And adding the round key to the first updated row vector and repeating the above processes.

According to the present invention, by implementing the AES encryption algorithm in multiple processors, it is possible to improve the operation speed by allocating similar load calculation amount while reducing unnecessary data exchange between processors.

1 illustrates a T-lookup AES encryption process performed in multiple processors according to the present embodiment.
2 illustrates a T-lookup AES key expansion process performed in multiple processors according to the present embodiment.
3 illustrates a transposed AES encryption process performed through multiple processors according to the present embodiment.
4 illustrates a pre-AES key expansion process performed by multiple processors according to the present embodiment.

AES encryption is described in the Federal Information Processing Standards Publication 197, a standard document, and each function required for the AES encryption process is also defined in this document.

The key used for AES encryption has 128 bits, 192 bits, and 256 bits, and the number of rounds is 10/12/14 depending on the encryption key length, and the length of the input / output block is 128 bits. Key expansion generates round keys for AES encryption from the encryption key, generating 44,52,60 words, respectively, depending on the length of the key, with the initial key value 128/192/256 bits. Expand the key of 4 words needed for the round.

Functions used for key expansion for encryption and round key generation used for encryption include AddRoundkey, MixColumn, RotWord, ShiftRow, Subbyte, Subword, and XOR operation. Rcon is specified to represent an array of round constants.

The operation of each function is specified in the FIPS 197 standard. A brief description follows.

AddRoundkey is a transformation that XORs a round key to a state.

MixColumn creates a new column by mixing each data independently for all the columns in the state.

RotWord is a function for cyclic permutation of 4-byte words, which is used in the key expansion process.

ShiftRow is a transformation that cyclically shifts the elements of the remaining three rows except for the first row of elements in the state with different offsets.

SubByte is a transformation that processes states using S-box, a nonlinear byte substitution table.

SubWord is a function used for key expansion. It is used for key expansion process by applying S-box to each of 4 bytes for 4 byte input word and getting the output.

) 및 곱셈(*)은 FIPS-197에 정의되어 있다. 덧셈(

)은 각 비트별 XOR연산으로 정의된다.Each operation and addition used in the present invention (

) And multiplication (*) are defined in FIPS-197. addition(

) Is defined by the XOR operation for each bit.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided to those skilled in the art to fully understand the present invention, and may be modified in various forms, and the scope of the present invention is limited to the embodiments described below. no. For example, a method of changing the number of multiprocessors, a method of dividing in a vertical direction without using a T-lookup, a method of implementing AES decryption algorithms, and a method of implementing an encryption / decryption algorithm multiprocessor similar to AES also include the scope of the present invention. Included in In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

1 illustrates a T-lookup AES encryption process performed in multiple processors according to the present embodiment.

The T-Lookup AES encryption method is to repeat the ShiftRow, SubByte, MixColum, and AddRoundKey processes for the state.

In this embodiment, in order to implement the T-lookup AES encryption method in multiple processors, first, states necessary for a process to be performed in each processor are reconfigured. In FIG. 1, only the elements 10a that make up the diagonal of the state are selected in the first processor. The second to fourth processors select only the elements 10b, 10c, and 10d located to the right of 1, 2, and 3 bytes from the diagonal, respectively.

Next, the processors perform the ShiftRow, SubByte, MixColum, and AddRoundKey processes on the reconstructed states, respectively, and each processor generates a column vector constituting the next round of states as shown by reference numbers 12a, 12b, 12c, and 12d. Get every time. Here, T-Lookup uses SubByte and MixColumn at once, and in other methods. Although not shown in the drawing, in order to implement SubByte conversion, a memory for storing an S-Box is required in addition to the multiprocessor.

Each processor receives its elements from the obtained column vectors 12a, 12b, 12c and 12d from the other three processors, respectively. For example, the first processor is a second, from _{1, 1,} the third processor W, W from the processor from _2,2, and a fourth processor, W _{'3, 3,} as shown.

Processors repeat this process as many times as necessary according to the encryption key length (14a, 14b, 14c, 14d).

On the other hand, the round key is required to perform the AddRoundKey procedure. The round key is generated according to the T-lookup AES key expansion procedure shown in FIG.

First, the first processor performs a RotWord and SubWord transformation on the rightmost column vector 21a of the input key data block 21b, performs an XOR operation on the Rcon (22a), and temp (23) the vector 23a. ) The temp vector 23a is passed to the second processor, and also XOR operation 24a with the P ₃ vector passed from the second processor to generate the next round W 'vector 25a. The first processor repeats this process as many times as necessary according to the encryption key length (26a). Although not shown in the drawing, in order to implement SubWord conversion, a memory for storing an S-Box is required in addition to a multiprocessor.

The second processor sequentially accumulates (22b) each column vector of the state 21b from the left (22b) to generate column vectors P ₁ , P ₂ , and P ₃ (23b), respectively. Among them, P ₃ is transferred to the first processor, and the leftmost column vector of the state 21b and P1, P2, and P3 are respectively XORed with the temporal vector 23a transferred from the first processor (24b). Each column vector computed becomes the key data 25b of the next round. The second processor repeats this process as many times as necessary according to the encryption key length (26b).

3 illustrates a transposed AES encryption process performed through multiple processors according to the present embodiment.

Processors process the row vector data of the state according to the pre-AES encryption process. First, ShiftRow transform (32a, 32b, 32c, 32d) with 0, 1, 2, and 3 byte offsets for each row vector (31a, 31b, 31c, 31d), and then SubByte transform (34a, 34b, 34c, 34d). do. Reference numerals 33a, 33b, 33c, and 33d indicate the ShiftRow conversion results, and 35a, 35b, 35c, and 35d show the SubByte conversion results. Although not shown in the drawing, in order to implement SubByte conversion, a memory for storing an S-Box is required in addition to the multiprocessor.

MixColumn transformations, such as reference numerals 36a, 36b, 36c, and 36d, are performed on the row vector where the SubByte transformation is completed. MixColumn performs the following operations.

는 덧셈을, *는 곱셈 연산이다.Here, Row1, Row2, Row3, and Row4 are row vectors as a result of performing SubByte, respectively, and W0, x, W1, x, W2, x, W3, x are row vectors generated after the MixColumn operation.

Is addition and * is a multiplication operation.

For the MixColumn transform according to Equation 1, processors receive a row vector from other processors and calculate a MixColumn transform.

Next, each processor performs AddRoundkey operations 37a, 37b, 37c, and 37d on the MixColumn transformed row vector to generate next round row vectors 38a, 38b, 38c, and 38d. Each processor repeats these processes as many times as necessary according to the encryption key length (39a, 39b, 39c, 39d).

Here, the round key used for AddRoundKey conversion is generated according to the transpose AES key expansion process shown in FIG. 4.

The first processor operates on the first two row vectors and the elements W _{1 , 3} of the key data block (41a), and the second processor operates on the remaining two row vectors and the elements W _{0 , 3} of the key data block (41b).

The first processor first performs a SubByte operation and a 3-byte left shift on elements W _{1 and 3} (42a), and performs an XOR operation on Rcon (43). An XOR operation 45a of the operation result 44a and the result of shifting the first row vector to the right by 1, 2, and 3 bytes, respectively, produces an XOR operation 45a to generate the first row vector 46a of the next round key data block 51a. Although not shown in the drawing, in order to implement SubByte conversion, a memory for storing an S-Box is required in addition to the multiprocessor.

Next, the first processor performs a subbyte operation 47a and a 3-byte left shift on the elements W _{2 and 3} (48a). The result 48a and the result of shifting the second row vector to the right by 1, 2 and 3 bytes, respectively, are all XORed 49a to produce the second row vector 50a of the next round key data block 51a.

The first processor also passes the elements W _{0 , 3} necessary for the next round operation to the second processor.

The second processor performs the operation SubByte (42b) and 3-byte left shifts for the element W _{3, 3} (44b). The third row vector of the next round key data block 51a is generated by performing an XOR operation on the shift result data 44b and the result of shifting the third row vector of the key data block to the right by 1, 2 and 3 bytes, respectively (45b). Transfer to the first processor.

Next, the second processor performs a 48-byte left shift and SubByte operation 47b on the elements W _{0 and 3} (48b). The fourth row vector of the next round key data block 51a is generated by performing an XOR operation on the shift result data 48b and the result of shifting the fourth row vector of the key data block to the right by 1, 2 and 3 bytes, respectively (49b). Transfer to the first processor.

The first and second processors repeat this process as many times as necessary according to the encryption key length (52a, 52b).

In contrast to the encryption process, the decryption consists of the reverse ShiftRow, reverse SubByte, reverse MixColumn, and AddRoundKey processes. In the encryption process, this embodiment illustrates a process in which four processors operate in parallel. However, the two processors may operate in parallel, and in the case of decryption, multiple operations may be performed in the reverse order.

The following table shows key expansion performance using single and multiple processors, respectively, for the AES-128.

Number of processors
Data exchange between processors
Operation cycles encryption Decrypt T-Lookup
One - 411 1257 2 72 bit 274 726 transposition
One - 642 622 2 64-bit 405 205

The following table shows encryption performance using single and multiple processors, respectively, for AES-128.

Number of processors Data exchange between processors Operation cycles encryption Decrypt
T-Lookup
One - 823 822 2 128 bit 469 469 4 192 bit 312 312
transposition
One - 2087 2959 2 192 bit 1102 1601 4 256 bit 695 1201

According to the table, it can be seen that when using multiple processors, the computational speed is faster than using a single processor.

As described above, an optimal embodiment has been disclosed in the drawings and the specification. Herein, specific terms have been used, but they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (8)

In a method for AES encryption using multiple processors,
Dividing the state by selecting elements to be processed in each processor for a state;
Performing, by each processor, transformations necessary for AES encryption on the partitioned state;
Adding a round key to the result of the transformations being completed;
Selecting one column vector sequentially for each processor from the result of the addition; And
Each processor receiving the state elements necessary for the next round of AES encryption from other processors and repeating the dividing step;
The dividing of the state may include a process in which the first processor selects elements corresponding to the diagonal of the state, and the remaining processors select elements shifted right by one byte sequentially from the diagonal. AES encryption method. delete The method of claim 1, wherein the round key
And a key data block having the same size as the state from the input key data, and the elements of the key data block are updated and generated every round of the repetition. The method of claim 3, wherein the round key
Updated by a second multiprocessor,
A first processor of the second multiprocessor updates a first value of a size corresponding to a column vector of the key data block every round using a second value transferred from a second processor, and then transfers the first value to the second processor. and,
The second processor of the second multiprocessor AES encryption method using a multi-processor, characterized in that for updating the elements of the key data block every round using the first value received. In a method for AES encryption using multiple processors,
Dividing the row vectors of the state by the number of the multiple processors, respectively;
Performing transformations for AES encryption on the divided row vectors, respectively;
Each processor calculating a row vector processed by the processor and row vectors transferred from other processors, and updating the row vector processed by the processor first; And
And adding the round key to the first updated row vector and repeating the partitioning operation.
The round key is a key data block having the same size as that of the state from the input key data, AES encryption method using a multi-processor characterized in that the elements of the key data block is generated by updating every round of the iteration. delete The device of claim 5, wherein the round key is
Updated by a second multiprocessor,
The second multiprocessor updates the row vectors every round using first elements of the key data block, row vectors of the data block, and second elements transmitted by the second multiprocessor. AES encryption method using multiple processors. The method of claim 7, wherein
A first processor of the second multiprocessor performs data conversion and a first operation on a third element of the first elements of the key data block, and performs a data conversion and a second operation on a fourth element. Perform a third operation on the first row vectors of the key data block, add the first operation result or the second operation result to the third operation result, and update the first row vectors; AES encryption method using a multi-processor, characterized in that for transferring one of the second elements to another processor of the processor.

Images