KR101005933B1 - Method and Apparatus for transmitting of data between Master and Slave - Google Patents

Abstract

The present invention relates to a data transmission method and apparatus between a master and a slave. The present invention further configures an external pin informing that the slave 200 has data to be transmitted to the master 100 in addition to the pin configuration according to the SPI (Serial Peripheral Interface) standard between the master 100 and the slave 200. The external pins are provided in the master 100 and the slave 200, respectively, and connected to each other. In such a state, when the slave 200 completes the data transmission preparation, sets the external pin to the low level state. The low level state is a state in which data can be transmitted and received. When the master 100 monitors an external pin state and the external pin of the slave 200 is set to a low level, the master 100 generates a clock signal having a predetermined frequency to the slave 200 through the clock pin SCK. The slave 200 transmits data to the master 100 according to the clock signal. When the slave 200 completes the data transmission, the slave 200 sets the external pin to a high level state to notify the master 100 that the data transmission is completed. According to the present invention as described above, there is an advantage of reducing data overhead since the master does not need to confirm the presence or absence of data to be received from the slave.

 Master, Slave, SPI, External Pins

Description

Method and device for transmitting data between master and slave {Method and Apparatus for transmitting of data between Master and Slave}

The present invention relates to a wireless sensor network system, and more particularly, to a method and apparatus for transmitting data between a master and a slave in which a physical (PHY) layer and a MAC (MAC) layer transmit data in a serial manner in a sensor node of a marine wireless sensor network. It is about.

The wireless sensor network refers to a network consisting of a sensor node and a sink node that collects and exports it to the outside. These sensor networks are also being applied to the marine environment, and the need continues to grow.

The sensor node includes a MAC layer on which the IEEE 802.15.4 MAC protocol is mounted, and a physical (PHY) layer on which the IEEE 802.15.4 PHY protocol is mounted. The MAC layer controls overall data communication of a sensor node, and the physical layer plays a role of transmitting data according to a control operation of the MAC layer. When the sensor node is applied to the marine environment, the physical layer becomes an underwater modem.

The MAC layer and the physical layer perform data transmission and reception with each other according to a predetermined communication method. For example, a serial interface (SPI) is one of the serial communication methods. In the SPI method, data is transmitted and received by four pins. That is, as described in detail below, data output pins, data input pins, clock pins, and slave select pins are used. The SPI scheme uses a master / slave model similar to the server / client model of socket communication. Therefore, in this description, the Mac layer is named master and the physical layer is named slave.

A master / slave configuration connected by the SPI scheme is shown in FIG. 1 is a configuration diagram in which a master / slave is connected by an SPI method.

Referring to FIG. 1, four pins are provided in the master 10 and the slave 20 to use the SPI scheme. The four pins include a clock (SCK: serial clock) pin for generating a clock signal necessary for data transmission, a master input slave out (MIS) pin used by the slave 20 to transmit data to the master 10, A master output slave input (MOSI) pin used by the master 10 to transmit data to the slave 20, and a slave select for selecting one slave when the slave 20 is plural. SS) pin. The slave select pin (/ SS) can transmit and receive data only in a low level state.

Although not shown, the SPI provides three registers. SPPI (SPI Control Register), which manages various settings for using SPI, SPDR (SPI Data Register), an 8-bit register that stores data sent and received by SPI, and SPSR (SPI, which manages data transmission and speed). Status Register). It is checked whether data transmission is completed according to a flag value included in a predetermined bit of the SPSR. For example, when the flag is set, it is determined that data is transmitted, and the value recorded in the buffer to be described below is read.

The master 10 is provided with a CPU 12. This is for the master 10 to control the overall data communication.

On the other hand, the master 10 and the slave 20 is provided with a buffer for storing data by the SPDR. The buffer consists of 8-bit shift registers (hereinafter referred to as 'shift registers') 14, 22. The shift registers 14 and 22 behave like circular queues.

Hereinafter, data transmission between the master 10 and the slave 20 will be described according to the related art.

First, the master 10 transmits 1-byte data to the slave 20. In the SPI method, data transmission is performed in 1-byte units.

First, the CPU 12 of the master 10 causes the slave select pin (/ SS) to be in a low level state.

In such a state, the master 10 writes new 1-byte data to the shift register 14 and generates a clock signal of a predetermined frequency through the clock pin SCK. The clock signal is automatically output from the clock pin SCK when the CPU 12 supports the SPI interface. However, the clock signal should be generated directly by the master 10 when the CPU 12 does not support the SPI interface.

In response to the clock signal generation, the master 10 transmits data to the slave 20 through the MOSI pin. The slave 20 stores the transmitted data in the shift register 22. When the data is transmitted, the master 10 sets the slave select pin (/ SS) to a high level to notify the slave 20 that data transmission is completed.

On the other hand, the slave 20 checks the flag setting of the shift register 22 when the slave select pin (/ SS) is in the low level state, and if the flag is set, the slave 20 checks the data stored in the shift register 22. Will lead. The flag is set when 1-byte data is received, but the flag status must be checked continuously when not using an interrupt service routine (ISR).

Next, the slave 20 transmits 1-byte data to the master 10.

First, the slave 20 writes data to be transmitted to the shift register 22. Then, it waits until a clock signal occurs at the clock pin SCK of the master 10. That is because the clock signal is generated only in the master (10).

In this state, when the master 10 sets the slave select pin / SS to a low level, a clock signal is generated through the clock pin SCK. When the clock signal is generated, the slave 20 transmits data to the master 10 through the MISO pin.

When all clock signals are output, that is, all data is transmitted, the master 10 reads the data by reading the shift register 14.

However, as described above, when data transfer is performed between master and slaves using only 4-pins, there are the following problems.

First, in order to receive normal data from the slave 20, the master 10 should check whether there is data to be periodically received. At this time, the master 10 generates a large overhead in the process of sending a request signal to the slave 20 and receiving an acknowledgment signal.

In addition, even when the slave 20 is ready to transmit data to the master 10, the slave 20 must wait for the clock signal to be generated from the master 10. As a result, the slave 20 cannot perform other tasks while preparing for the data transmission. If code is written to perform another task while waiting for the generation of the clock signal, a problem may occur in which data to be transmitted is changed by the other task.

Accordingly, an object of the present invention is to solve the above problems, and to reduce overhead caused when a master (MAC layer) and a slave (PHY layer) transmit data between each other using an SPI scheme.

Another object of the present invention is to reduce the clock generation delay time of the master (MAC layer).

According to a feature of the present invention for achieving the above object, a master for controlling data communication of the sensor node in the wireless sensor network; A slave transmitting data according to a control operation of the master; And an SPI interface unit connected between the master and the slave to perform data transmission and reception between the master and the slave in a serial transmission method, wherein the SPI interface unit is configured to provide the serial transmission method to the master and the slave. A clock pin (serial clock) for generating a clock signal for data transmission, a master input slave out (MISO) pin for transmitting data to the master, and the master transmitting data to the slave And a master output slave input (MOSI) pin, a slave selection pin (/ SS) for selecting the slave, and an input / output pin for requesting data transmission to the master.

The input / output pin may include a first pin for requesting data transmission by the slave to the master, a second pin indicating that the slave is receiving data, and a third pin indicating that the slave is transmitting data.

The driving of the first, second, and third pins is all performed at a low level.

According to another feature of the invention, the step of the slave completes the data transmission preparation; A first notification step of notifying that a master connected with the slave has data to transmit when the slave completes data transmission; Transmitting, by the slave, the data when a clock signal having a predetermined frequency is generated from the master; And a second notification step of notifying the master that data transmission is completed when the slave completes the data transmission.

According to still another aspect of the present invention, the slave and the data transmission in a state in which the master and the slave is connected to the SPI interface and the external pin provided to allow the slave to request data transmission to the master to transmit data in a serial communication method. Completing the preparation; Setting the external pin to a low level state when the slave completes data transmission preparation; Generating, by the master, the clock signal of a predetermined frequency to the slave when the external pin is set to a low level state; The slave transmitting data to the master according to the clock signal; Setting the external pin to a high level state to notify the master that the data transfer is complete when the slave completes the data transfer.

When the external pin is set to the low level state, the master writes dummy data in its shift register to generate the clock signal.

While the slave is transmitting data, the master checks the state of the external pin, and stops receiving the dummy data when the external pin is set to a high level as a result of the test.

When the external pin is interrupted, the master receives data from the slave as long as the external pin is set to the low level.

In the present invention, when the MAC layer (i.e., master) and the physical layer (i.e., slave) in the sensor node of the wireless sensor network transmit and receive data by the serial peripheral interface, the slave has data to transmit to the master. Since the slave notifies the master, the master does not need to periodically check whether there is data to be received from the slave, thereby reducing the overhead of the data.

In addition, when the slave transmits data to the master, since the master generates a clock signal only at the request of the slave, the clock generation delay time of the master is shortened, thereby improving the operation efficiency of the slave.

Hereinafter, a method and an apparatus for transmitting data between a master and a slave according to the present invention will be described in detail with reference to a preferred embodiment shown in the accompanying drawings.

As described above, a sensor node applied to an underwater sensor network or the like includes a MAC layer and a physical layer, and the MAC layer generally controls data communication of the sensor node, and the physical layer is the MAC layer. In the embodiment of the present invention, the MAC layer is referred to as a master and the physical layer is referred to as a slave. The physical layer may be an underwater modem capable of data communication with other nodes in the water.

FIG. 2 is a diagram illustrating an SPI pin configuration and a configuration diagram between a master and a slave connected by the pin configuration according to an exemplary embodiment of the present invention.

2, the master 100 and the slave 200 are connected to each other by a serial peripheral interface (SPI) scheme.

The configurations of the master 100 and the slave 200 are the same as those mentioned in the related art, and thus a detailed description thereof will be omitted. However, the master 100 includes a CPU 110 and a master shift register 120, and the slave 200 includes a temporary reception buffer 210 and a slave shift register 220. The temporary reception buffer 210 temporarily stores the slave 200 when it receives data from the master 100.

In the pin configuration for applying the SPI method, a clock pin (serial clock, SCK) for generating a clock signal required for data transmission, and MISO (Master used by the slave 200 to transmit data to the master 100) input slave out) pin, a master output slave input (MOSI) pin used by the master 100 to transmit data to the slave 200, a slave select pin (/ SS) for selecting the slave 200, and In addition, the slave 200 includes an additional pin for requesting data transmission to the master 100.

The additional pins consist of all three pins. The first pin serves to request data transmission from the slave 200 to the master 100. In this case, the first pin should be in a low level. When the second pin is in the low level state, the slave (ie, the underwater modem) 200 indicates that data is being received. The third pin indicates that the slave (ie, underwater modem) 200 is transmitting data when the low level state is reached. The additional pins are all set to be output from the slave 200 to the master 100. Here, the first pin is an essential pin for the slave 200 to transmit data, and the first pin is effectively handled by the master 100 in an interrupt manner. In addition, the second pin and the third pin are not necessarily pins that should be used as a part for minimizing a portion where a problem may occur in the operation of the slave 200.

Next, the data transmission process between the master and the slave according to the above configuration will be described. Here, the process will be divided into a process of receiving and transmitting data by the slave and a process of transmitting and receiving data by the master.

First, the operation of the slave 200 is described.

First, a case in which the slave 200 receives data from the master 100 will be described with reference to FIG. 3.

Receiving data by the slave 200 is performed by an SPI Interrupt Service Routine (ISR). The SPI ISR is generated when 1-byte transfer is completed to the MOSI pin (s100).

Therefore, when the SPI ISR occurs, the slave 200 receives data stored in the shift register 120 of the master 100 and temporarily stores the data stored in the temporary reception buffer 210 (S102). The data stored in the temporary reception buffer 210 is stored in the shift register 220 when all data transmission is completed (s104).

In this case, when the master 100 transmits data of 1 byte or more bytes, the slave 200 has no method of checking whether data transmission is completed. Thus, the slave 200 preferably stores the data stored in the temporary reception buffer 210 in the shift register 220 about 30us after receiving the last data. This is because the slave 200 first stores the data received from the master 100 through the MOSI pin in the temporary reception buffer 210 and then moves it back to the shift register 220 to store the data. Because.

Next, the slave 200 transmits data to the master 100. This is referred to FIG. 4.

First, the slave 200 prepares for data transmission (s110). When the preparation for data transmission is completed, the slave 200 changes the state of the first pin among its additional pins to notify the master 100 that there is data to transmit (s112).

The master 100 checks the state of the first pin of the slave 200 connected to the first pin of its additional pin (s114). As a result of the inspection, when the first pin is changed from the high level to the low level state (s116), the master 100 generates a clock signal of a predetermined frequency through the clock pin (SCK) (s118).

When the clock signal is generated, the slave 200 transmits data to the master 100 through the MISO pin according to the clock signal (S120).

When the slave 200 transmits all data to the master 100 (s122), the slave 200 changes the first pin from a low level state to a high level state (s124). Therefore, the master 100 is notified that the transmission is completed.

That is, in FIG. 4, if there is data to be transmitted to the master 100, the slave 200 does not wait for the master 100 to generate a clock signal, but may notify the master 100 that there is data to be transmitted. It is.

Second is the description of the master operation.

First, a case in which the master transmits data to the slave will be described with reference to FIG. 5.

In order to transmit data, the master 100 sets the slave select pin (/ SS) to a low level (s130), and writes data to be transmitted to the shift register 120 (s132). Then, the master 100 generates a clock signal of a predetermined frequency through the clock pin (SCK) (s134).

When the clock signal is generated, the master 100 transmits data written to the shift register 120 to the slave 200 through the MOSI pin according to the clock signal (S138).

When the data transmission is completed, the master 100 sets the slave select pin (/ SS) to a high level and ends the transmission (s140).

At this time, the master 100 should not transmit the data within a predetermined time when the data transmission is completed. That is, the slave 200 first stores the data received from the master 100 through the MOSI pin in the temporary reception buffer 210 and then moves it back to the shift register 220 to store the data. Because. In general, since the movement time is 30 ms, the master 100 preferably does not transmit data to the slave 200 again within 30 ms after completion of data transmission.

Next, the master receives data from the slave. This is referred to FIG. 6.

The master 100 checks the state of the first pin of the slave 200 connected to the first pin among its additional pins (S150). The first pin state is a high level or low level state. This means that there is data to be transmitted only at the low level.

When the first pin of the master 100 is at a low level as a result of the inspection (s152), the master 100 generates a clock signal by writing dummy data in the shift register 120, or The master 100 directly generates a clock signal (s154).

In response to the clock signal generation, the slave 200 transmits data to the master 100 through the MISO pin (s156).

When the slave 200 completes the transmission of all data to the master 100 (s158), the slave 200 sets the first pin to a high level (s160). Accordingly, the master 100 does not receive dummy data to be recorded in its shift register 120. That is, the master 100 should always check the first pin state after receiving 1-byte data. This is because data transfer is performed in units of 1 byte in the SPI.

In this case, when the master 100 receives data from the slave 200, if the first pin is treated as an interrupt, the master 100 may set the slave only if the first pin is set to a low level. Data is received from the 200.

Although described with reference to the illustrated embodiment of the present invention as described above, this is merely exemplary, those skilled in the art to which the present invention pertains various modifications without departing from the spirit and scope of the present invention. It will be apparent that other embodiments may be modified and equivalent. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

That is, in the present embodiment, a sensor node used in the underwater sensor network is described as an example, but the present invention can be applied to the sensor node used on the ground.

1 is a configuration diagram in which a master / slave is connected by an SPI method

2 is a configuration diagram between the SPI pin configuration and the master and slave connected by the pin configuration in accordance with a preferred embodiment of the present invention

3 is a flowchart illustrating a process in which a slave receives data from a master in the configuration of FIG.

4 is a flowchart illustrating a process in which a slave transmits data to a master in the configuration of FIG.

5 is a flowchart illustrating a process in which a master transmits data to a slave in the configuration of FIG.

6 is a flowchart illustrating a process in which a master receives data from a slave in the configuration of FIG.

* Description of the symbols for the main parts of the drawings *

100: master 110: CPU

120: master shift register 200: slave

210: temporary receive buffer 220: shift register for slave

Claims (8)

A master for controlling data communication of sensor nodes in a wireless sensor network; A slave transmitting data according to a control operation of the master; And, And an SPI interface unit connected between the master and the slave to perform data transmission and reception between the master and the slave by a serial transmission method. The SPI interface unit is installed in each of the master and the slave to provide the serial transmission method, a clock pin for generating a clock signal for data transmission, a MISO for the slave to transmit data to the master (Master input slave out) pin, a master output slave input (MOSI) pin for the master to transmit data to the slave, a slave selection pin (/ SS) for selecting the slave, and the slave transmits data to the master Data transmission device between the master and the slave, characterized in that it comprises an input and output pin for requesting. The method of claim 1, wherein the input and output pins, And a first pin for requesting data transmission by the slave to the master, a second pin indicating that the slave is receiving data, and a third pin indicating that the slave is transmitting data. Transmission device. 3. The method of claim 2, Driving of the first pin, the second pin, and the third pin are all performed in the low level state, the data transmission device between the master and the slave. delete When the master and the slave are connected to an SPI interface and an external pin provided to allow the slave to request data transmission to the master to transmit data in a serial communication manner, the slave completing data transmission preparation; Setting the external pin to a low level state when the slave completes data transmission preparation; Generating, by the master, a clock signal of a predetermined frequency to the slave when the external pin is set to a low level state; The slave transmitting data to the master according to the clock signal; And, And setting the external pin to a high level state to notify the master that the data transmission is completed, when the slave completes data transmission. The method of claim 5, And when the external pin is set to the low level state, the master writes dummy data in its shift register to generate the clock signal. The method of claim 6, While the slave is transmitting data, the master checks the state of the external pin, and if the external pin is set to a high level as a result of the test, the master stops receiving the dummy data. Data transfer method. The method of claim 5, When the external pin is interrupted, the master receives data from the slave only if the external pin is set to a low level.

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