KR101005669B1 - Method for manufacturing air gap of semiconductor device - Google Patents

Method for manufacturing air gap of semiconductor device Download PDF

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KR101005669B1
KR101005669B1 KR1020080086557A KR20080086557A KR101005669B1 KR 101005669 B1 KR101005669 B1 KR 101005669B1 KR 1020080086557 A KR1020080086557 A KR 1020080086557A KR 20080086557 A KR20080086557 A KR 20080086557A KR 101005669 B1 KR101005669 B1 KR 101005669B1
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air gap
thin film
plasma
semiconductor device
manufacturing
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KR20100027580A (en
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여상학
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주식회사 동부하이텍
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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  • Chemical & Material Sciences (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 에어갭 제조 기술에 관한 것으로, 패턴된 반도체 기판 상에 플라즈마 폴리머 유기 박막 및 저 유전 물질(low-k)층을 형성한 후에 열처리 및 플라즈마 처리 공정을 수행하여 플라즈마 폴리머 유기 박막이 갭필되었던 공간에 에어갭을 형성하는 것을 특징으로 한다. 본 발명에 의하면, 플라즈마 폴리머를 이용한 IMD/ILD 물질의 개선 및 에어갭 형성으로 배선 간 캐패시턴스를 크게 감소하여 소자 구동에 있어 지연 상수(RC)딜레이 및 신호 왜곡에 대한 영향을 급감시킬 수 있다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for manufacturing an air gap of a semiconductor device. A plasma polymer organic thin film is formed by performing a heat treatment and a plasma treatment process after forming a plasma polymer organic thin film and a low-k layer on a patterned semiconductor substrate. It is characterized by forming an air gap in this gap-filled space. According to the present invention, the improvement of the IMD / ILD material using the plasma polymer and the formation of the air gap can greatly reduce the capacitance between the wirings, which can drastically reduce the effects on the delay constant (RC) delay and the signal distortion in device driving.

반도체, low-k, 에어갭, 플라즈마 폴리머(Plasma Ploymer) Semiconductor, low-k, air gap, plasma polymer

Description

반도체 소자의 에어갭 제조 방법{METHOD FOR MANUFACTURING AIR GAP OF SEMICONDUCTOR DEVICE} TECHNICAL FOR MANUFACTURING AIR GAP OF SEMICONDUCTOR DEVICE

본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 특히 플라즈마 폴리머(Plasma Ploymer) 박막을 이용한 에어갭(air-gap) 제조를 통하여 공정 간소화 및 후속 공정의 위험성을 줄이는데 적합한 반도체 소자의 에어갭 제조 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to an air gap manufacturing method of a semiconductor device suitable for streamlining the process and reducing the risk of subsequent processes by manufacturing an air gap using a plasma polymer (Plasma Ploymer) thin film. It is about.

요즘 들어 초고밀도(ULSI) 반도체 소자의 집적회로에 사용되는 다층 금속 배선 공정에서 저 유전 물질(low-k)과 에어갭을 사용하여 배선 간 기생 캐패시턴스(Parasitic Capacitance)를 줄이는 방법에 대해 많은 연구가 이루어지고 있으며, 이러한 저 유전 물질과 에어갭을 이용한 캐패시턴스 감소 방법으로서, 스핀 코팅법(Spin on coating)을 사용한 기술이 개발되어 사용되고 있다. Nowadays, a lot of research has been conducted on how to reduce parasitic capacitance between wires by using low-k materials and air gaps in multilayer metal wiring processes used in integrated circuits of ultra high density (ULSI) semiconductor devices. As a method for reducing capacitance using such a low dielectric material and an air gap, a technique using a spin on coating has been developed and used.

이러한 스핀 코팅법은 반도체 기판 상에 에어갭 형성을 위해 희생층으로 사용되는 유기 고분자 박막을 스핀 코팅법으로 형성하고 다공성 유전막을 형성한 후에 산소 분위기에서의 열처리 공정을 수행하여 유기 고분자 박막을 산화 및 증발시킴으로서, 유기 고분자 박막이 형성되었던 공간에 에어갭을 형성하게 되는 것이다. In the spin coating method, an organic polymer thin film, which is used as a sacrificial layer for forming an air gap on a semiconductor substrate, is formed by spin coating, a porous dielectric film is formed, and a heat treatment process is performed in an oxygen atmosphere to oxidize and By evaporating, an air gap is formed in the space where the organic polymer thin film was formed.

상기한 바와 같이 동작하는 종래 기술에 의한 에어갭 형성 방법에 있어서는, 상하 배선 물질과의 접착이 불량하고, 유기 고분자 박막 특유의 열 경화에 의한 고응력이 발생하며, 주위 수분의 흡착으로 인해 유전상수가 변하여 소자의 신뢰성이 떨어지는 등의 단점이 있다. 또한 공정수가 많고 박막 간 유착(adhesion) 문제를 유발한다는 문제점이 있었다. In the air gap forming method according to the prior art operating as described above, adhesion to the upper and lower wiring materials is poor, high stress due to thermal curing peculiar to the organic polymer thin film is generated, and dielectric constant is caused by adsorption of ambient moisture. There is a disadvantage that the reliability of the device is lowered. In addition, there is a problem that a large number of processes and causes adhesion problems between the thin films.

이에 본 발명은, 플라즈마로 증착된 폴리머 박막을 이용한 에어갭 제조를 통하여 공정 간소화 및 후속 공정의 위험성을 줄일 수 있는 반도체 소자의 에어갭 제조 방법을 제공한다. Accordingly, the present invention provides a method of manufacturing an air gap of a semiconductor device, which can simplify the process and reduce the risk of subsequent processes by manufacturing an air gap using a polymer thin film deposited by plasma.

또한 본 발명은, 패턴된 반도체 기판 상에 플라즈마 폴리머 유기 박막 및 저 유전 물질(low-k)층을 형성한 후에 열처리 및 플라즈마 처리 공정을 수행하여 플라즈마 폴리머 유기 박막이 갭필되었던 공간에 에어갭을 형성할 수 있는 반도체 소자의 에어갭 제조 방법을 제공한다. In addition, the present invention, after forming a plasma polymer organic thin film and a low-k material layer on the patterned semiconductor substrate and performing a heat treatment and a plasma treatment process to form an air gap in the space where the plasma polymer organic thin film was gap-filled A method for manufacturing an air gap of a semiconductor device can be provided.

본 발명의 일 실시예 방법은, 패턴된 반도체 기판 상에 플라즈마 폴리머 유기 박막 및 저 유전 물질(low-k)층을 형성한 후에 열처리 및 플라즈마 처리 공정을 수행하여 플라즈마 폴리머 유기 박막이 갭필되었던 공간에 에어갭을 형성하는 것을 특징으로 한다. In one embodiment of the present invention, a plasma polymer organic thin film and a low dielectric material (low-k) layer are formed on a patterned semiconductor substrate, followed by a heat treatment and a plasma treatment process. It is characterized by forming an air gap.

본 발명의 다른 실시예 방법은, 패턴된 반도체 기판 상에 실리콘 포함 박막 을 증착하는 단계; 상기 실리콘 포함 박막 상에 플라즈마 폴리머 유기 박막을 증착한 후, 평탄화 공정을 수행하는 단계; 상기 평탄화 공정 이후, 저 유전 물질(low-k)층을 형성하는 단계; 상기 저 유전 물질층의 형성 이후 열처리 및 플라즈마 처리 공정을 수행하는 단계; 상기 열처리 및 플라즈마 처리 공정을 통하여 상기 저 유전 물질층 상에 다공성 실리콘 박막을 형성하고, 상기 플라즈마 폴리머 유기 박막이 갭필되었던 공간에 에어갭을 형성하는 단계를 포함한다. Another embodiment method of the present invention includes the steps of depositing a silicon-containing thin film on a patterned semiconductor substrate; Depositing a plasma polymer organic thin film on the silicon-containing thin film, and then performing a planarization process; After the planarization process, forming a low-k layer; Performing a heat treatment and a plasma treatment process after the formation of the low dielectric material layer; Forming a porous silicon thin film on the low dielectric material layer through the heat treatment and the plasma treatment process, and forming an air gap in a space where the plasma polymer organic thin film was gap-filled.

본 발명에 있어서, 개시되는 발명 중 대표적인 것에 의하여 얻어지는 효과를 간단히 설명하면 다음과 같다. In the present invention, the effects obtained by the representative ones of the disclosed inventions will be briefly described as follows.

본 발명은, 플라즈마 폴리머를 이용한 상부 층간 절연막(Inter Metal Dielectric, 이하 IMD라 한다)/층간 절연막(ILD: interlayer dielectrics) 물질의 개선 및 에어갭 형성으로 배선 간 캐패시턴스(capacitance)를 크게 감소하여 소자 구동에 있어 지연 상수(RC)딜레이 및 신호 왜곡에 대한 영향을 급감시킬 수 있다. 그리고 에어갭 형성 시 열처리 공정을 시행하여 박막이 열처리 공정에 대한 내열성을 갖추게 됨으로써, 후속 열처리 공정을 줄일 수 있다. According to the present invention, an improvement in the material of an upper interlayer dielectric (IMD) / interlayer dielectric (ILD) material using plasma polymer and air gap formation greatly reduces the capacitance between wirings, thereby driving devices. The effects on the delay constant (RC) delay and signal distortion can be greatly reduced. In addition, when the air gap is formed, the heat treatment process is performed to provide the heat resistance to the heat treatment process, thereby reducing the subsequent heat treatment process.

또한 열처리 및 플라즈마 처리를 증착 장비 내에서 인-시츄로 시행할 수 있으므로, 후속 IMD 열처리 공정을 단순화시킬 수 있는 효과가 있다. In addition, since the heat treatment and the plasma treatment can be performed in-situ in the deposition equipment, there is an effect that can simplify the subsequent IMD heat treatment process.

이하 첨부된 도면을 참조하여 본 발명의 동작 원리를 상세히 설명한다. 하기에서 본 발명을 설명함에 있어서 공지 기능 또는 구성에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우에는 그 상세한 설명을 생략할 것이다. 그리고 후술되는 용어들은 본 발명에서의 기능을 고려하여 정의된 용어들로서 이는 사용자, 운용자의 의도 또는 관례 등에 따라 달라질 수 있다. 그러므로 그 정의는 본 명세서 전반에 걸친 내용을 토대로 내려져야 할 것이다. Hereinafter, the operating principle of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, if it is determined that a detailed description of a known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. The following terms are defined in consideration of the functions of the present invention, and may be changed according to the intentions or customs of the user, the operator, and the like. Therefore, the definition should be based on the contents throughout this specification.

본 발명은 플라즈마 폴리머 박막을 이용한 에어갭 제조를 통하여 공정 간소화 및 후속 공정의 위험성을 줄이기 위한 것으로서, 열적 불안정성으로 300℃ 이하에서 완전히 분해되는 플라즈마 폴리머 박막을 희생층으로 사용하여 열처리(anneal) 공정을 통해 에어갭 형성을 수행하는 것이다. The present invention is to simplify the process and reduce the risk of subsequent processes through the air gap manufacturing using a plasma polymer thin film, using an annealing process using a plasma polymer thin film that is completely decomposed at 300 ℃ or less due to thermal instability as a sacrificial layer Through air gap formation.

도 1a 내지 도 1e는 본 발명의 바람직한 일 실시예에 따른 반도체 소자의 에어갭 형성 단계를 나타낸 공정 순서도이다. 1A to 1E are process flowcharts illustrating an air gap forming step of a semiconductor device according to an exemplary embodiment of the present invention.

도 1a를 참조하면, 패턴된 반도체 기판 상(100)에 실리콘이 포함된 박막(예컨대, USG(Undoped Silcate Glass))(102)을　 증착하고, 도 1b에 도시한 바와 같이 플라즈마로 폴리머 유기(organic) 박막(104)을 증착한 후, 도 1c와 같이 화학적 기계적 연마(이하, CMP라 한다)를 통한 평탄화 공정을 수행한다. Referring to FIG. 1A, a silicon-containing thin film (eg, USG (Undoped Silcate Glass)) 102 is deposited on the patterned semiconductor substrate 100 and polymerized with plasma as shown in FIG. 1B. ) After the thin film 104 is deposited, a planarization process through chemical mechanical polishing (hereinafter referred to as CMP) is performed as shown in FIG. 1C.

이후, 도 1d에 도시한 바와 같이 평탄화된 반도체 기판 상에 저 유전 물질(low-k)층(예컨대, SiOCH)(106)을 형성하고, 급속 열처리(Rapid Thermal process, 이하 RTP라 한다) 방법을 이용한 열처리 공정과, 플라즈마 처리 공정을 1~2분 내외 동안 수행한다. 한편, 열처리 및 플라즈마 처리 공정은 증착 장비 내에서 인-시츄로 시행할 수 있으므로, 이를 통해 후속 IMD 열처리 공정을 단순화시킬 수 있다. Thereafter, a low-k layer (eg, SiOCH) 106 is formed on the planarized semiconductor substrate as shown in FIG. 1D, and a rapid thermal process (hereinafter referred to as RTP) method is described. The used heat treatment process and the plasma treatment process are performed for about 1 to 2 minutes. On the other hand, the heat treatment and plasma treatment process can be performed in-situ in the deposition equipment, thereby simplifying the subsequent IMD heat treatment process.

이러한 열처리 및 플라즈마 처리 공정을 통하여 도 1e에 도시한 바와 같이 다공성 실리콘(porous Si)이 포함된 박막(108)이 형성됨과 동시에 플라즈마 폴리머 유기 박막(104)이 외부로 배출(Out gassing) 됨으로써, 정형화된 에어갭(112)을 형성하게 된다. 또한, 플라즈마 처리 공정을 통해 다공성 실리콘이 포함된 박막(108) 상에 절연성이 개선된 박막층(110)이 형성되어, IMD 층의 유전율을 급격히 감소시키게 된다. Through the heat treatment and the plasma treatment process, as shown in FIG. 1E, the thin film 108 including the porous silicon is formed and the plasma polymer organic thin film 104 is out gassed to the outside, thereby shaping. The air gap 112 is formed. In addition, the thin film layer 110 having improved insulation is formed on the thin film 108 including porous silicon through the plasma treatment process, thereby rapidly decreasing the dielectric constant of the IMD layer.

한편, 본 발명의 실시예에서 이용되는 플라즈마 폴리머 유기 박막(104)의 특성은 유기물로만 구성되어 있으므로, 플라즈마 폴리머 유기 박막(104)이 증착된 상부에 열적으로 불안한 에틸렌(-CH2-)기가 많고 기공성을 가진 전구체로 박막, 즉 저 유전 물질 층(106)을 형성함으로써, 도 1e에 도시한 바와 같이 정형화된 에어 갭(112)을 IMD 층에 형성시킨다. On the other hand, since the plasma polymer organic thin film 104 used in the embodiment of the present invention is composed of only organic materials, the thermally unstable ethylene (-CH2-) groups and pores on the plasma polymer organic thin film 104 are deposited. By forming a thin film, i.e., low dielectric material layer 106, with a precursor having a property, a shaped air gap 112 is formed in the IMD layer as shown in FIG.

이와 같이 도 1a 내지 도 1e와 같은 제조 공정에서는 습식(wet) 공정의 진행시 발생할 수 있는 문제점 및 리스크(risk)가 줄어들 뿐만 아니라 후속 금속 배선 공정에 대한 영향을 미치지 않는 특징이 있다. As described above, in the manufacturing process as shown in FIGS. 1A to 1E, problems and risks that may occur during the progress of the wet process may be reduced, and the subsequent metal wiring process may not be affected.

도 2a 내지 도 2c는 본 발명의 바람직한 다른 실시예에 따른 반도체 소자의 에어갭 형성 단계에서 열처리 및 플라즈마 처리 공정을 나타낸 공정 순서도이다. 2A to 2C are flowcharts illustrating heat treatment and plasma treatment processes in an air gap forming step of a semiconductor device according to another exemplary embodiment of the present invention.

도 2a를 참조하면, 실리콘을 포함하는 박막(202)이 증착된 반도체 기판(200) 상에 플라즈마로 증착되는 폴리머 유기 박막(204) 즉, 플라즈마 폴리머 유기 박막(204)은, 열적으로 불안정 하며 분자사이즈가 작기 때문에 갭필(gap fill) 능력이 우수하며, 플라즈마 폴리머 유기 박막(204) 위에 증착 되는 저 유전 물질 층(206)은 캡핑(Capping) 박막으로 사용되며, TEOS(Tetra Ethyl Ortho Silicate), 실리콘 함유물질(SiOCH, SiO, SiN, SiONCH, SiCH, SiCNH)들 중 어느 하나를 사용한다. Referring to FIG. 2A, the polymer organic thin film 204, ie, the plasma polymer organic thin film 204, which is deposited with plasma on the semiconductor substrate 200 on which the thin film 202 including silicon is deposited, is thermally unstable and molecular. Due to its small size, it has excellent gap fill capability, and the low dielectric material layer 206 deposited on the plasma polymer organic thin film 204 is used as a capping thin film, and is a tetra ethyl ortho silicate (TEOS) or silicon. One of the materials (SiOCH, SiO, SiN, SiONCH, SiCH, SiCNH) is used.

이러한 낮은 유전상수 값을 갖는 저 유전 물질 층(206)은 도 2b에 도시한 바와 같이 300℃~450℃ 범위에서의 RTP 공정을 통하여 플라즈마 폴리머 유기 박막(204)의 소멸 제거와 동시에 다공성 박막(208)을 형성하게 되며, 플라즈마 폴리머 유기 박막(204)의 소멸을 통해 에어갭(210)을 형성하게 된다. The low dielectric material layer 206 having such a low dielectric constant value is a porous thin film 208 at the same time as the disappearance removal of the plasma polymer organic thin film 204 through the RTP process in the range 300 ℃ ~ 450 ℃ as shown in Figure 2b ) To form an air gap 210 through the disappearance of the plasma polymer organic thin film 204.

이때 발생될 수 있는 절연특성의 박막 형성 및 다공성 박막(208) 내에 잔재하는 물질들을 고정화 및 제거하기 위해서 He와 N2O가스를 사용하는 플라즈마 처리 공정을 수행하게 된다. 도 2c에서와 같이 플라즈마 처리 공정 시 유도결합형 플라즈마(Inductively Coupled Plasma)를 사용하는데, 증착기판과 플라즈마 사이의 거리가 있는 유도 결합형 플라즈마는 박막의 표면에 작은 수십 나노미터 이하(예컨대, 5~100nm의 범위)의 절연성에 대해 개선되어진 박막층(210)을 형성하게 되며, 이러한 절연성이 개선된 박막층(210)이 플라즈마로부터 발생되는 직접적인 피해(damage)를 줄일 수 있다는 장점이 있다. In this case, a plasma treatment process using He and N 2 O gas may be performed to form a thin film having an insulating property and to fix and remove materials remaining in the porous thin film 208. As shown in FIG. 2C, an inductively coupled plasma is used in the plasma treatment process. An inductively coupled plasma having a distance between the deposition substrate and the plasma has a small tens of nanometers or less (eg, 5 to 5 ~) on the surface of the thin film. The thin film layer 210 is improved with respect to the insulation of the range of 100nm, and the improved thin film layer 210 has an advantage of reducing the direct damage generated from the plasma.

이와 같이, 플라즈마 폴리머를 이용한 층간 절연막(IMD/ILD) 물질의 개선 및 에어갭 형성으로 배선 간 캐패시턴스를 크게 감소하여 소자 구동에 있어 지연 상수(RC)딜레이 및 신호 왜곡에 대한 영향을 급감시킬 수 있다. 그리고 에어갭 형성 시 열처리 공정을 수행하여 박막이 열처리 공정에 대한 내열성을 갖추게 됨으로써, 후속 열처리 공정을 줄일 수 있다. As described above, the improvement of the interlayer insulating film (IMD / ILD) material using the plasma polymer and the formation of the air gap can greatly reduce the capacitance between the wires, which can drastically reduce the effects on the delay constant (RC) delay and the signal distortion in driving the device. . In addition, since the thin film has heat resistance to the heat treatment process by performing a heat treatment process when the air gap is formed, the subsequent heat treatment process may be reduced.

이상 설명한 바와 같이, 본 발명은 플라즈마 폴리머 박막을 이용한 에어갭 제조를 통하여 공정 간소화 및 후속 공정의 위험성을 줄이기 위한 것으로서, 열적 불안정성으로 300℃ 이하에서 완전히 분해되는 플라즈마 폴리머 박막을 희생층으로 사용하여 열처리 공정을 통해 에어갭을 형성한다. As described above, the present invention is to simplify the process and reduce the risk of subsequent processes through the air gap manufacturing using the plasma polymer thin film, heat treatment using a plasma polymer thin film that is completely decomposed at 300 ℃ or less due to thermal instability as a sacrificial layer The process forms an air gap.

한편 본 발명의 상세한 설명에서는 구체적인 실시예에 관해 설명하였으나, 본 발명의 범위에서 벗어나지 않는 한도 내에서 여러 가지 변형이 가능함은 물론이다. 그러므로 본 발명의 범위는 설명된 실시예에 국한되지 않으며, 후술되는 특허청구의 범위뿐만 아니라 이 특허청구의 범위와 균등한 것들에 의해 정해져야 한다. While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but is capable of various modifications within the scope of the invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by those equivalent to the scope of the claims.

도 1a 내지 도 1e는 본 발명의 바람직한 일 실시예에 따른 반도체 소자의 에어갭 형성 단계를 나타낸 공정 순서도, 1A to 1E are process flowcharts illustrating an air gap forming step of a semiconductor device according to an embodiment of the present invention;

도 2a 내지 도 2c는 본 발명의 바람직한 다른 실시예에 따른 반도체 소자의 에어갭 형성 단계를 나타낸 공정 순서도. 2A to 2C are process flowcharts illustrating an air gap forming step of a semiconductor device according to another exemplary embodiment of the present invention.

< 도면의 주요 부분에 대한 부호 설명 > <Explanation of Signs of Major Parts of Drawings>

100 : 반도체 기판 　　　　　　　　　　　　　　　　102 : 실리콘 성분 포함 박막 100: semiconductor substrate # 102: thin film containing silicon component

104 : 플라즈마 폴리머 유기막　　　　　　106 : SiOCH막 104: plasma polymer organic film # 106: SiOCH film

108 : 다공성 SiOCH막　　　　　　　　　　　　　　110 : 절연성이 개선된 박막 108: porous SiOCH film # 110: thin film with improved insulation

112 : 에어갭112: air gap

Claims (8)

패턴된 반도체 기판 상에 플라즈마 폴리머 유기 박막 및 저 유전 물질(low-k)층을 형성한 후에 열처리 및 플라즈마 처리 공정을 수행하여 상기 플라즈마 폴리머 유기 박막이 갭필되었던 공간에 에어갭을 형성하는 반도체 소자의 에어갭 제조 방법. After forming a plasma polymer organic thin film and a low dielectric material (low-k) layer on the patterned semiconductor substrate, a heat treatment and a plasma treatment process are performed to form an air gap in the space where the plasma polymer organic thin film was gap-filled. Air gap manufacturing method. 패턴된 반도체 기판 상에 실리콘 포함 박막을 증착하는 단계; Depositing a thin film comprising silicon on the patterned semiconductor substrate; 상기 실리콘 포함 박막 상에 플라즈마 폴리머 유기 박막을 증착한 후, 평탄화 공정을 수행하는 단계; Depositing a plasma polymer organic thin film on the silicon-containing thin film, and then performing a planarization process; 상기 평탄화 공정 이후, 저 유전 물질(low-k)층을 형성하는 단계; After the planarization process, forming a low-k layer; 상기 저 유전 물질층의 형성 이후 열처리 및 플라즈마 처리 공정을 수행하는 단계; Performing a heat treatment and a plasma treatment process after the formation of the low dielectric material layer; 상기 열처리 및 플라즈마 처리 공정을 통하여 상기 저 유전 물질층을 다공성 실리콘 박막으로 형성시키고, 상기 플라즈마 폴리머 유기 박막이 갭필되었던 공간에 에어갭을 형성하는 단계 Forming the low dielectric material layer into the porous silicon thin film through the heat treatment and the plasma treatment process, and forming an air gap in the space where the plasma polymer organic thin film was gap-filled; 를 포함하는 반도체 소자의 에어갭 제조 방법. Air gap manufacturing method of a semiconductor device comprising a. 제 2항에 있어서, 3. The method of claim 2, 상기 플라즈마 처리 공정을 통하여 상기 다공성 실리콘 박막 표면에 5~100nm 범위의 절연성에 대해 개선된 박막층을 형성하는 것을 특징으로 하는 반도체 소자의 에어갭 제조 방법. The method of manufacturing an air gap of a semiconductor device, characterized in that to form an improved thin film layer for insulation in the range of 5 ~ 100nm on the surface of the porous silicon thin film through the plasma treatment process. 제 2항에 있어서, 3. The method of claim 2, 상기 평탄화 공정은 화학적 기계적 연마(CMP) 공정인 것을 특징으로 하는 반도체 소자의 에어갭 제조 방법. The planarization process is a chemical mechanical polishing (CMP) process, characterized in that the air gap manufacturing method of a semiconductor device. 제 1항 또는 2항에 있어서, The method according to claim 1 or 2, 상기 열처리는, The heat treatment, 300℃에서 450℃의 온도범위에서 수행하는 급속 열처리(RTP) 공정인 것을 특징으로 하는 반도체 소자의 에어갭 제조 방법. Air gap manufacturing method of a semiconductor device, characterized in that the rapid heat treatment (RTP) process carried out in a temperature range of 300 ℃ to 450 ℃. 제 1항 또는 2항에 있어서, The method according to claim 1 or 2, 상기 플라즈마 처리는, The plasma treatment, He와 N2O 가스를 이용한 유도결합형 플라즈마를 수행하는 것을 특징으로 하는 반도체 소자의 에어갭 제조 방법. Method for manufacturing an air gap of a semiconductor device, characterized in that for performing inductively coupled plasma using He and N 2 O gas. 제 1항 또는 2항에 있어서, The method according to claim 1 or 2, 상기 열처리 및 플라즈마 처리 공정은, The heat treatment and plasma treatment process, 인-시츄로 수행하는 것을 특징으로 하는 반도체 소자의 에어갭 제조 방법. Air gap manufacturing method of a semiconductor device, characterized in that performed in-situ. 제 1항 또는 2항에 있어서, The method according to claim 1 or 2, 상기 저 유전 물질(low-k)층은, The low dielectric material (low-k) layer, TEOS 또는 실리콘 함유 물질인 것을 특징으로 하는 반도체 소자의 에어갭 제조 방법. Air gap manufacturing method of a semiconductor device, characterized in that the TEOS or silicon-containing material.
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