KR101004809B1 - Method for manufacturing gate dielectric layer of the merged memory and logic device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a gate insulating film of a composite semiconductor memory device. In particular, a first insulating film (silicon oxide film) and a second insulating film (silicon nitride film) are formed on an entire surface of a semiconductor substrate to define a gate insulating film of a memory cell region. The second insulating film and the first insulating film are patterned so that the semiconductor substrate of the logic transistor region of the circuit region is opened, a floating gate is formed on the gate insulating film of the memory cell region, and a third insulating film (amorphous silicon film) is formed on the entire surface of the semiconductor substrate. After forming and removing the third insulating film of the I / O and logic transistor areas of the peripheral circuit region, a fourth insulating film (silicon oxide film) is formed on the entire surface of the semiconductor substrate to define a gate insulating film having a step in the peripheral circuit region. Therefore, the present invention defines a gate insulating film in the memory cell region and performs a different gate insulating film manufacturing process in the peripheral circuit region, while reducing the number of oxidation processes that cause thermal budgets and depositing different insulating layers in the peripheral circuit region. The yield of these transistors can be increased by forming gate insulating films of high voltage transistors, I / O transistors, and logic transistors.

Composite, high voltage

Description

Method for manufacturing gate dielectric layer of the composite semiconductor memory device             

1 through 5 are diagrams sequentially illustrating a process of manufacturing each gate insulating layer in a cell region and a peripheral circuit region of a composite semiconductor memory device according to the present invention.

-Explanation of symbols for the main parts of the drawing-

10 semiconductor substrate 12 first insulating film

14 second insulating film 16, 22 photoresist pattern

18: floating gate 20: third insulating film

22a, 22b, 22c, 22d: fourth insulating film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a composite semiconductor memory device, and more particularly, to a method for manufacturing a gate insulating film of a composite semiconductor memory device, which can simplify a process and improve a yield in a gate insulating film manufacturing process.

MFL (Merged Flash and Logic) devices, which are complex semiconductor memory devices integrating flash memory devices such as EEPROM and logic circuits, replace the existing mask ROM, OPT, and PLD markets, and have a short life cycle in the digital market, The application is expanding to mobile products.

The layout of the complex semiconductor memory device is divided into a memory cell region and a peripheral circuit region. In the cell region, a memory cell transistor such as an EEPROM is formed, and in the peripheral region, a high voltage transistor, an input / output (I / O) buffer circuit, a logic transistor, and the like are formed.

In the method of manufacturing the composite semiconductor memory device, the gate insulating film manufacturing process of the cell region and the peripheral circuit region is performed respectively. Because the effective thickness of the tunnel oxide film of the cell transistor affecting the program / erase operation is the gate insulating film of the low voltage transistor, together with the gate insulating film for the high voltage transistor used in the peripheral circuit region and the gate insulating film for the I / O transistor operated at a specific voltage. This is because the thicknesses of are different. That is, the memory cell transistor needs a tunnel oxide film having a suitable thickness for charge injection during program / erase operation, and the high voltage transistor, which is a peripheral circuit, is usually applied with a high voltage of 8V to 20V to prevent breakdown. A gate insulating film much thicker than the region is required. In addition, logic transistors require a thin gate insulating film for high-speed characteristics, and I / O transistors require a gate insulating film structure capable of withstanding various input voltages for I / O buffers and chip protection.

Therefore, in the manufacturing process of the conventional semiconductor memory device, each transistor in the semiconductor memory device is formed by forming a gate insulating film having an appropriate thickness for the different thickness of the gate insulating film, leaving only the necessary area, and etching the gate insulating film in the remaining areas. The gate insulating films required by were formed.

Therefore, the gate insulating film manufacturing process according to the prior art has a problem in that the entire manufacturing process is complicated and the process time is increased as a number of photo mask process and the etching process or the insulating film deposition process according to it is made. In addition, there is a problem that the yield and reliability of the semiconductor device are deteriorated due to a large effect on the doping profile prior to the oxidation process due to thermal budget due to oxidation, which is a process of manufacturing a plurality of gate insulating layers.

An object of the present invention is to define a gate insulating film in the memory cell region and to perform a different gate insulating film manufacturing process in the peripheral circuit region in order to solve the problems of the prior art as described above, the number of oxidation processes that cause thermal budget By reducing and depositing different insulating layers, the gate insulating films of the high voltage transistors, I / O transistors, and logic transistors in each peripheral circuit region can be formed to adjust the threshold voltages of each transistor in these peripheral circuit regions, thereby improving the yield and reliability of the semiconductor device. The present invention provides a method for manufacturing a gate insulating film of a composite semiconductor memory device.

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method of manufacturing a composite semiconductor memory device having at least two transistors in a peripheral circuit region, wherein the gate insulating layer of the memory cell region is formed by forming first and second insulating layers over the entire upper surface of the semiconductor substrate. Defining and patterning the second insulating film and the first insulating film to open the semiconductor substrate in the third region of the peripheral circuit region; forming a floating gate over the gate insulating film of the memory cell region; Forming an insulating film and removing the third insulating film of the second and third regions of the peripheral circuit region; and forming a fourth insulating film on the entire surface of the semiconductor substrate to form the first, second, and third regions of the peripheral circuit region. And defining the gate insulating film of the corresponding region by the remaining first insulating film and the fourth insulating film.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 through 5 are diagrams sequentially illustrating a process of manufacturing each gate insulating layer in a cell region and a peripheral circuit region of a composite semiconductor memory device according to the present invention. In these figures, A represents a memory cell region in which cell transistors are formed, and B to D represent peripheral circuit regions (first to third regions) in which high voltage, I / O, and logic transistors are formed, respectively. More specifically, B is a region (first region) in which a high voltage transistor is formed in a peripheral circuit region, C is a region (second region) in which an I / O transistor is formed, and D is a region (third region) in which a logic transistor is formed. Define.

First, as shown in FIG. 1, an isolation process such as shallow trench isolation (STI) is performed on a silicon substrate with a semiconductor substrate 10, and a well (not shown) is formed in the memory cell region A. FIG. do. After the silicon oxide film (SiO2) is formed on the semiconductor substrate 10 as the first insulating film 12 by about 20 to 50 microseconds, it is etched to define the tunnel portion in the cell region. As a result, the first insulating layer 12 in the cell transistor region A becomes a tunnel oxide layer in which the tunnel portion is etched, and the first insulating layer 12 in the remaining peripheral circuit regions B, C, and D is not etched. Has a status. Then, a silicon nitride film (SiN) is formed on the entire upper surface of the semiconductor substrate 10 as a silicon nitride film (SiN) of about 50 to 100 Å, and the photolithography process is performed to form a photoresist pattern in which the logic transistor region D in the peripheral circuit region is opened. 16). At this time, since the first insulating film 12 and the second insulating film 14 of the memory cell region A become the entire gate insulating film of the cell transistor, the capacitance becomes larger than that of the general single oxide film structure.                     

Next, referring to the drawings below, a stepped gate insulating film is manufactured in the transistors in the first region B, the second region C, and the third region D of the peripheral circuit region.

As shown in FIG. 2, the surface of the semiconductor substrate 10 in the region D is exposed by removing the second insulating layer 14 and the first insulating layer 12 of the logic transistor region D opened by an etching process. Let's do it. The photoresist pattern 16 is removed.

A doped polysilicon film is deposited on the entire surface of the resultant as a conductive film for the floating gate, and an oxide Nitride Oxide (ONO) film is deposited thereon as an inter-gate insulating film and patterned to form the floating gate 18 and the dielectric film pattern in the memory cell region A. (Not shown).

Next, as shown in FIG. 3, an undoped amorphous silicon film is deposited on the entire surface of the resultant as the third insulating film 20 for the gate insulating film process required for the high voltage transistor region B, and then heat treatment is performed. do. In this case, the third insulating layer 20 may deposit a high temperature oxide (HTO) instead of an amorphous silicon film, and the heat treatment process is a rapid thermal process (RTP) process. Next, a photoresist pattern 22 having the I / O and logic transistor regions C and D in the peripheral circuit region open is formed on the third insulating layer 20 by a photo process.

Subsequently, an amorphous silicon layer, which is the third insulating layer 20 exposed to the I / O and logic transistor regions C and D by the photoresist pattern 22, is removed by an etching process. As a result, as shown in FIG. 4, only the third insulating film 20 remains in the cell region A and the high voltage transistor region B in the peripheral circuit region, and the I / O and logic transistor regions C and D remain. ), The surface of the second insulating film 14 and the semiconductor substrate 10 are exposed.

Subsequently, for the gate insulating film required for the logic transistor, the silicon oxide film (SiO2) is formed in the memory cell region A and the peripheral circuit regions B, C, and D as the fourth insulating films 22a, 22b, 22c, and 22d, respectively. Grow about 45Å. In this case, an amorphous silicon film as the third insulating film 20 is exposed in the memory cell region A and the high voltage transistor region B in the peripheral circuit region, and a silicon nitride film as the second insulating film 14 in the I / O transistor region C. Since the exposed state and the surface of the semiconductor substrate 10 are exposed in the logic transistor region D, the thicknesses of the fourth gate insulating layers 22a, 22b, 22c, and 22d grown in the respective regions are changed.

Then, as shown in FIG. 5, a doped polysilicon film is deposited on the entire surface of the semiconductor substrate 10 having the above structure as a control gate conductive film and patterned, thereby controlling the control gate 24a in the memory cell region A. FIG. ) And gates in the peripheral circuit areas B, C, and D, respectively. That is, the gate 24b of the high voltage transistor in the B region, the gate 24c of the I / O transistor in the C region, and the gate 24d of the logic transistor are formed in the D region, respectively.

Although not shown in the drawings, a source / drain ion implantation and a wiring process are performed on the semiconductor substrate 10 to complete the manufacturing process of the composite semiconductor memory device according to the present invention.

Therefore, in the present invention, the gate insulating film of the memory cell region A is composed of a double insulating film as compared to a single insulating film (silicon oxide film) because the first insulating film 12 and the second insulating film 14 are combined to have a total thickness of 70 Å to 120 Å. As a result, the capacitance of the cell transistor is increased. Since the gate insulating film of the high voltage transistor region B has a thickness of 200 kW to 350 kW in the first to fourth insulating films 12, 14, 20, and 22b, the breakdown is prevented even when a high voltage of 8V to 20V is applied. It becomes thickness to be able to do it. The gate insulating film of the I / O transistor region C has a thickness of 50 mW to 70 mW as the first insulating film 12, the second insulating film 14, and the fourth insulating film 22c are combined to form an I / O buffer and chip protection. In addition to being able to cope with various input voltages, the gate insulating film of the logic transistor region D is thin with a thickness of 25 kV to 45 kV as it is in the fourth insulating film 22d, thereby enabling high-speed operation.

As described above, the present invention defines a gate insulating film in the memory cell region and performs a different gate insulating film manufacturing process in the peripheral circuit region, but by depositing different insulating layers, the high voltage transistor and the I / O transistor in each peripheral circuit region. The gate insulating film of the logic transistor is formed.

Therefore, the present invention can reduce the number of oxidation processes that cause thermal budgets and adjust the threshold voltages of the transistors in the memory cell and the peripheral circuit region, thereby improving the yield and reliability of the semiconductor device.

On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

Claims (5)

A method of manufacturing a composite semiconductor memory device having at least two transistors in a peripheral circuit region, First and second insulating layers are formed on the entire upper surface of the semiconductor substrate to define a gate insulating layer of the memory cell region, and to open the semiconductor substrate of the third region among the first, second and third regions of the peripheral circuit region. Patterning the second insulating film and the first insulating film; Forming a floating gate over the gate insulating layer of the memory cell region; Forming a third insulating film over the semiconductor substrate and removing third insulating films of second and third regions of the peripheral circuit region; And A first gate insulating layer defined by first to fourth insulating layers remaining in a first region of the peripheral circuit region by forming a fourth insulating layer over the semiconductor substrate, and the first, second, and fourth remaining in the second region; And defining a gate insulating film of the first to third regions with a second gate insulating film defined as an insulating film and a third gate insulating film defined as a fourth insulating film remaining in the third region. A method of manufacturing a gate insulating film of a semiconductor memory device. The gate insulating layer of claim 1, wherein the first region of the peripheral circuit region is a high voltage transistor, the second region is an I / O transistor, and the third region is a region in which a logic transistor is formed. Manufacturing method. The method of claim 1, wherein the first insulating film and the fourth insulating film are silicon oxide films, the second insulating film is a silicon nitride film, and the third insulating film is an undoped amorphous silicon film. The method of claim 1, wherein the first insulating film and the fourth insulating film are silicon oxide films, the second insulating film is a silicon nitride film, and the third insulating film is a high temperature silicon oxide film. The gate of the composite semiconductor memory device according to claim 1, wherein the first insulating film is 25 kPa to 50 kPa, the second insulating film is 50 kPa to 100 kPa, the third insulating film is 150 kPa to 300 kPa, and the fourth insulating film is 25 kPa to 45 kPa thick. Method of manufacturing insulating film.

Images