KR101004445B1 - State metric computation apparatus for turbo decoding - Google Patents

Abstract

The present invention relates to a state metric calculation device for decoding a convolutional turbo code (CTC), wherein the binary turbo decoded state metric calculation device of the present invention comprises a sum of two input previous state metrics and a branch metric. A first adder for outputting the first and second metric sums; A second adder configured to output first and second output values obtained by adding a constant value to each of the first metric sum and the second metric sum and a mean value of the first and second metric sums as a third output value; And a minimum value calculator configured to select and output a minimum value among the first to third output values of the second adder.

According to the present invention, it is possible to reduce hardware complexity compared to the conventional maximum log maximum post (Max-Log-MAP) method while improving the error correction performance compared to the improved maximum log maximum post (Log-MAP) method. In addition to this, the operation delay time can also be effectively reduced.

Turbo Code, Status Metrics, Max-Log-MAP, Improved Max-Log-MAP

Description

STATIC METRIC COMPUTATION APPARATUS FOR TURBO DECODING}

The present invention relates to a turbo decoder, and more particularly to an apparatus for calculating a state metric for decoding a convolutional turbo code (CTC).

As technology related to communication systems and data transmission and reception are advanced, and information to be transmitted becomes high speed, large capacity, and multimedia, it is becoming an important issue to be able to transmit information quickly and accurately. Loss of information occurs due to noise, fading, interference, etc. generated in the communication channel, which causes transmission errors.

The error correction code refers to a technique of transmitting an additional bit to an information bit at an transmitting end and transmitting the additional bit, and effectively decoding the bits received through a communication channel to increase the reliability of the information bit. Since the publication of Shannon's research in 1948, "If information is less than the channel capacity, information can be transmitted without error", research on error correction codes that show excellent error correction performance has been ongoing.

Among these error correction codes, the turbo code, first proposed by Berrou et al. In 1993, has a relatively simple structure and is very close to Shannon's limitations. It is applied as an error correction code in many wireless communication fields.

In general, a dual binary turbo decoder includes two SISO decoders, an interleaver and a deinterleaver as shown in FIG. Each SISO decoder receives a priori information (APR) generated by another SISO decoder from information bits and parity bits transmitted from an encoder, and includes a posteriori information (APP) and additional information (EI). Calculate The additional information EI is fed back to another SISO decoder for use as advance information APR through an interleaver or deinterleaver. The result value obtained through repeated decoding by the specified number of times using two SISO decoders is output as the final decoded result value through the hard decision process.

In order to simplify the decoding process, the output of the SISO decoder is expressed as Log Likelihood Ratio (LLR). The decoding algorithm used to extract the LLR value from the SISO decoder is largely the maximum post-algorithm (MAP). It is divided into Soft Output Viterbi Algorithm (SOVA). In general, the method using the MAP algorithm is known to perform better than the method using the SOVA.

The MAP algorithm is in turn purely MAP, Log-MAP, Max-Log-MAP, or Min-Log-MAP. Divided.

According to the pure maximum MAP algorithm, the LLR value is obtained using the forward state metric, the reverse state metric, and the branch metric. The forward state metric, the reverse state metric, and the branch metric are defined as follows.

,

,

,

,

는 순방향 상태 메트릭이고,

는 역방향 상태 메트릭이며,

는 가지 메트릭이다.here

Is the forward status metric,

Is a reverse state metric,

Is the branch metric.

In the pure maximum MAP scheme, the forward state metric and the reverse state metric may be calculated using Equations 1 and 2 below.

However, Equation 1 and Equation 2 have a disadvantage in that it is difficult to implement in hardware since the operation of a general equation as shown in Equation 3 below is required.

Since this pure maximum MAP method is complicated to implement in hardware, other methods that reduce the implementation complexity are used. A representative method is the maximum log-maximum (Max-Log-MAP) method, which reduces the complexity of implementation by calculating Equation 3 using the following approximation.

The Max-Log-MAP method is widely used for hardware implementation because of its low implementation complexity, but has a problem in that error correction capability is somewhat reduced.

The improved Max-Log-MAP method proposed by Talakoub approximates Equation 3 using the Maclaurin Series as follows to improve the error correction capability.

Improved Max-Log-MAP has the advantage of higher error correction than Max-Log-MAP or Min-Log-MAP. . However, the improved Max-Log-MAP method has a drawback in that the operation delay time is increased a little.

2 is a block diagram of a state metric computing device with an improved Max-Log-MAP algorithm. In FIG. 2, the part indicated by a dotted line is a hardware implementation of the added term on the right side of Equation 5 above. Although the terms added in FIG. 2 are not complex combinational-logics circuits, this increases the operating delay time. This is because the critical path of turbo code decoding is a state metric operation.

This increase in operating delay can cause a problem of lowering the maximum operating clock speed. Naturally, this problem is especially great when applied to dual binary turbo decoders.

Therefore, there is an urgent need for a state metric algorithm that can reduce operation delay time in binary turbo decoding or dual binary turbo decoding.

An object of the present invention is to provide a state metric computing device capable of reducing operation delay time while reducing implementation complexity in binary turbo decoding or dual binary turbo decoding.

Binary turbo decoded state metric computing device of the present invention for achieving the above object comprises: a first adder for outputting each sum of two pairs of the previous state metric and the branch metric input to the first and second metric sum; A second adder configured to output first and second output values obtained by adding a constant value to each of the first metric sum and the second metric sum and a mean value of the first and second metric sums as a third output value; And a minimum value calculator configured to select and output a minimum value among the first to third output values of the second adder.

A dual binary turbo decoded state metric computing device of the present invention for achieving the above object comprises: a first adder for outputting each sum of four input previous state metrics and branch metrics as first to fourth metric sums; The first to fourth output values are obtained by adding a constant value to each of the first to fourth metric sums of the first adder, and outputting the average values of the first and second metric sums and the average of the third and fourth metric sums, respectively. A second adder outputting the fifth and sixth output values; And a minimum value calculator configured to select and output any one of the first to sixth output values of the second adder as a minimum value.

According to the state metric calculation apparatus of the present invention through the above configuration, the improved maximum log maximum post-signal (Improved Max-Log-MAP) method with improved error correction performance compared to the conventional maximum log-maximum post-Max-Log-MAP method In addition to reducing hardware complexity, operating latency can be effectively reduced.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and that additional explanations of the claimed invention are provided. Reference numerals are shown in detail in preferred embodiments of the invention, examples of which are indicated in the reference figures. In any case, like reference numerals are used in the description and the drawings to refer to the same or like parts. DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

The present invention proposes a binary turbo decoding and a double binary turbo decoding algorithm capable of reducing operation delay time while having high error correction capability, and a state metric computing device for a binary turbo decoder and a double binary turbo decoder implemented by the proposed algorithm. To provide.

First, the binary turbo decoding algorithm according to the present invention is derived as follows.

은 순방향 상태 메트릭과 가지 메트릭의 합(또는 역방향 상태 메트릭과 가지 메트릭의 합)을 의미하고,

이므로

라고 정의하면 상기 수학식 5는 다음과 같이 대체될 수 있다.

Means the sum of the forward state metric and the branch metric (or the sum of the reverse state metric and the branch metric),

Because of

Equation 5 can be replaced as follows.

In terms of hardware implementation to prevent overflow in state metric operations, finding the minimum value from Equation 6 is simpler than finding the maximum value from Equation 5.

,

라고 정의하면, 상기 수학식 6은 다음과 같이 보다 간단하게 대체될 수 있다.

,

Equation 6 can be replaced more simply as follows.

In order to reduce an operation delay time by reducing a critical path, the last term of Equation 7 may be expressed as follows.

Since only the addition operation exists in Equation 8, when calculating the state metric using Equation 8, the error correction performance is the same as the improved maximum log-maximum (Improved Max-Log-MAP) method, but the operation delay time. Can be effectively reduced.

3 is a block diagram of a binary turbo decoded state metric arithmetic unit in which the state metric arithmetic algorithm of Equation 8 is implemented in hardware. Referring to FIG. 3, the binary turbo decoded state metric computing device 300 of the present invention includes a first adder comprising two adders 301 and 302 and a third adder 311, 312 and 3213. It includes two adders and a minimum value calculator. The minimum value calculator includes a third adder consisting of three adders 321, 322, and 323, an AND gate 330, a combiner 340, and a demultiplexer 350.

The adders 301 and 302 of the first adder add two input previous state metrics and branch metrics and output the first metric sum δ ₁ and the second metric sum δ _2, respectively. The output first metric sum δ ₁ and the second metric sum δ ₂ are input to the second adder.

The adders 311, 312, and 313 of the second adder perform an addition operation using the first metric sum δ ₁ , the second metric sum δ ₂ , and a constant value. Specifically, the adder 311 adds the first metric sum δ ₁ and the constant value ln2 to output the first output value a, and the adder 313 adds the second metric sum δ ₂ and the constant value. (ln2) is added and output as the second output value c. The adder 312 outputs an average value of the first metric sum δ ₁ and the second metric sum δ ₂ as a third output value b. The first to third output values a, b, and c respectively output from the adders 311, 312, and 313 of the second adder are provided to the minimum value calculator.

The minimum value calculator selects and outputs one of the first to third output values as a minimum value through a minimum value calculation. Specifically, the adders 321, 322, and 323 of the third adder calculate a difference between two different output values among the first to third output values a, b, and c, respectively, when the value is greater than zero. '0' is output as the corresponding bit value. If it is less than 0, '1' is output as the corresponding bit value. For example, the adder 321 calculates the difference between the first output value a and the second output value b to output the first bit value, and the adder 322 outputs the first output value a and the third output value c. The second bit value is output by calculating the difference of the?, And the adder 323 calculates the difference between the second output value b and the third output value c to output the third bit value.

The AND gate 330 logically operates the first bit value and the second bit value and outputs one bit value. The combiner 340 combines the output bit value of the AND gate 330 and the third bit value to provide to the demultiplexer 350.

The demultiplexer 350 selects one of the first to third output values based on the output of the combiner 340 and outputs the minimum value. The output value of the demultiplexer 350 becomes the current state metric value.

According to the binary turbo decoded state metric calculation device implemented by the proposed state metric calculation algorithm of the present invention, it is possible to improve the error correction performance compared to the conventional maximum log-maximum (Max-Log-MAP) method. Compared to the Improved Max-Log-MAP method, not only can the hardware complexity be reduced, but the operational delay time can be effectively reduced.

Next, the double binary turbo decoding algorithm according to the present invention is derived as follows.

Equation 8 may be developed as follows for dual binary turbo decoding.

The dual binary turbo decoding state metric calculation algorithm according to Equation (9) finds a minimum value among seven values. The last seventh value of Equation (9) greatly increases the operation delay time while greatly improving the error correction capability. Can't contribute.

Accordingly, the present invention proposes a dual binary turbo decoding state metric algorithm that omits the seventh value of Equation 9 and finds the minimum of six values as follows to effectively reduce the critical path.

FIG. 4 is a block diagram of a dual binary turbo decoded state metric arithmetic unit in which the state metric arithmetic algorithm of Equation 11 is implemented in hardware. Referring to FIG. 4, the dual binary turbo decoded state metric computing device 400 of the present invention includes a first adder including four adders 401 to 404, and a second adder comprising six adders 411 to 416. An adder and a minimum value calculator. The minimum calculator includes a third adder consisting of 15 adders 421-435, an AND gate part consisting of four AND gates 441-444, a combiner 450, and a demultiplexer 460.

The adders 401 to 404 of the first adder add four input previous state metrics and branch metrics and output the first metric sum δ ₁ to the fourth metric sum δ _4, respectively. The output first metric sum δ ₁ to fourth metric sum δ ₄ are input to the second adder.

The adders 411 to 416 of the second adder perform an addition operation using the first metric sum δ ₁ to the fourth metric sum δ ₄ and a constant value. Specifically, the adders 411, 413, 414, and 416 add the constant value ln2 to the first metric sum δ ₁ to the fourth metric sum δ ₄ , respectively, so that the first to fourth output values a , c, d, f). The adder 412 outputs an average value of the first metric sum δ ₁ and the second metric sum δ ₂ as a fifth output value b, and the adder 415 generates a third metric sum δ ₃ and a second value. The average value of the four metric sum δ ₄ is output as the sixth output value. The first through sixth output values a, b, c, d, e, and f respectively output from the adders 411 through 416 of the second adder are provided to the minimum value calculator.

The minimum value calculator selects and outputs one of the first to sixth output values as a minimum value through a minimum value calculation. Specifically, the adders 421 to 435 of the third adder respectively calculate a difference between two different output values among the first to sixth output values a, b, c, d, e, and f. If the value is greater than 0, '0' is output as the corresponding bit value. If the value is less than 0, '1' is output as the corresponding bit value. For example, the adder 421 calculates the difference between the first output value a and the second output value b to output the first bit value, and the adder 422 outputs the first output value a and the third output value c. The second bit value is output by calculating the difference of the?, And the adder 423 outputs the third bit value by calculating the difference between the second output value b and the third output value c. In this manner, the adders 421 to 435 of the third adder output the first to fifteenth bit values, respectively.

The AND gates 441 to 444 of the AND gate portion logically operate on the first to fourteenth bit values and output one bit value. Specifically, the AND gate 441 outputs one bit value by performing a logical operation on the first to fifth bit values, and the AND gate 442 performs a logical operation on the sixth to ninth bit values to output one bit value. The AND gate 443 outputs one bit value by performing a logical operation on the tenth to twelfth bit values, and the AND gate 444 performs a logical operation on the thirteenth and fourteenth bit values to output one bit value. Output

The combiner 450 combines the four bit values output from the AND gates 441 to 444 of the AND gate portion and the fifteenth bit value to provide to the demultiplexer 460. The demultiplexer 460 selects any one of the first to sixth output values based on the output of the combiner 450 and outputs the minimum value. The output of the demultiplexer 460 becomes the current state metric value.

According to the dual binary turbo decoded state metric arithmetic unit implemented by the proposed state metric arithmetic algorithm of the present invention, the error correction performance is improved compared to the conventional maximum log-maximum (Max-Log-MAP) scheme, and the improved maximum Compared to the Improved Max-Log-MAP method, not only can the hardware complexity be reduced, but the operational delay time can be effectively reduced.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

1 is a block diagram showing the structure of a typical dual binary turbo decoder.

FIG. 2 is a block diagram showing the structure of a state metric computing device implemented by an improved Max-Log-MAP algorithm. FIG.

3 is a block diagram showing the structure of a binary turbo decoded state metric computing device according to the present invention;

4 is a block diagram showing the structure of a dual binary turbo decoded state metric computing device according to the present invention;

Claims (8)

A first adder configured to output each sum of two input previous state metrics and branch metrics as first and second metric sums; A second adder configured to output first and second output values obtained by adding a constant value to each of the first metric sum and the second metric sum of the first adder, and an average value of the first and second metric sums as a third output value; And a minimum value calculator configured to select and output a minimum value among the first to third output values of the second adder. The apparatus of claim 1, wherein the constant value is ln2. The method of claim 1, wherein the minimum value calculator, A third adder configured to calculate a difference between two different output values among the first to third output values of the second adder and output the first to third bit values; An AND gate for performing a logic operation on the first and second bit values of the third adder; A combiner for combining and outputting a third bit value of the third adder and an output bit value of the AND gate; And And a demultiplexer for selecting and outputting any one of the first to third output values of the second adder as a minimum value based on the output of the combiner. The binary turbo of claim 3, wherein the first to third bit values are output as '0' when the value is greater than 0 and '1' when the value is less than 0. Decoded state metric computing device. A first adder configured to output each sum of the input four pairs of previous state metrics and branch metrics as first to fourth metric sums; The first to fourth output values are obtained by adding a constant value to each of the first to fourth metric sums of the first adder, and outputting the average values of the first and second metric sums and the average of the third and fourth metric sums, respectively. A second adder outputting the fifth and sixth output values; And a minimum value calculator configured to select one of the first to sixth output values of the second adder as a minimum value and output the minimum value. 6. The apparatus of claim 5, wherein the constant value is ln2. The method of claim 5, wherein the minimum value calculator, A third adder configured to calculate a difference between two different output values among the first to sixth output values of the second adder and output the first to fifteenth bit values; An AND gate part configured to perform a logic operation on the first to fourteenth bit values of the third adder to output four bit values; A combiner for combining the fifteenth bit value of the third adder and the output bit values of the AND gate part; And And a demultiplexer for selecting and outputting any one of the first to sixth output values of the second adder as a minimum value based on the output of the combiner. The method of claim 7, wherein the first to fifteenth bit values are output as '0' if the value is greater than zero and '1' if less than zero. Binary Turbo Decoded State Metric Arithmetic Unit.

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