KR101003125B1 - Refresh Control Circuit and Method in Semiconductor Memory Apparatus - Google Patents

Abstract

The refresh control circuit of the semiconductor memory device of the present invention comprises: bank refresh control means for generating a plurality of bank refresh enable signals in response to a refresh operation signal and a plurality of refresh timing signals; And timing control means for generating the plurality of refresh timing signals by variably delaying the plurality of bank refresh enable signals in response to a capacity determining signal.

Semiconductor memory device, refresh, capacity determination

Description

Refresh control circuit and method in semiconductor memory device {Refresh Control Circuit and Method in Semiconductor Memory Apparatus}

The present invention relates to a semiconductor memory device, and more particularly, to a refresh control circuit and a method of a semiconductor memory device for setting the refresh interval of each bank.

In general, a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) has a large number of memory cells composed of one transistor and one capacitor, and the data stored in each memory cell is volatile. Therefore, in order to prevent the loss of the logic data that each cell capacitor should have due to leakage current in each cell of the semiconductor memory, the logic held by each cell by periodically rewriting the data in each cell. A refresh operation is needed to keep the data.

The refresh operation of the semiconductor memory device is basically carried out for all banks simultaneously. However, in the semiconductor memory device operating in such a manner, excessive peak current occurs during the refresh operation, and thus malfunctions have become a problem. Accordingly, the semiconductor memory device solves the above-mentioned problem by introducing a technique of simultaneously performing refresh operations in all banks, and performing refresh operations with a slight time difference in each bank. To this end, the semiconductor memory device includes a refresh control circuit that adjusts an enable timing of a bank refresh enable signal transmitted to each bank.

In general, the refresh operation period is implemented differently according to the capacity of each semiconductor memory device. In other words, if the capacity of the semiconductor memory device is large, the refresh operation section should be relatively long. If the capacity of the semiconductor memory device is small, the refresh operation should be relatively short. However, the refresh control circuit of the conventional semiconductor memory device is designed without considering the capacity of the semiconductor memory device, and thus has a fixed refresh operation section. Therefore, the refresh operation section has to be set in accordance with the capacity of the semiconductor memory device, and as a result, the efficiency of time and cost in manufacturing the semiconductor memory device is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and there is a technical problem to provide a refresh control circuit and method for a semiconductor memory device that can adjust a refresh operation section according to the capacity of the semiconductor memory device.

According to one or more embodiments of the present invention, a refresh control circuit of a semiconductor memory device generates a plurality of bank refresh enable signals in response to a refresh operation signal and a plurality of refresh timing signals. Way; And timing control means for generating the plurality of refresh timing signals by variably delaying the plurality of bank refresh enable signals in response to a capacity determining signal.

In addition, the refresh control circuit of the semiconductor memory device according to another embodiment of the present invention generates the first bank refresh enable signal in response to the refresh operation signal, and generates the second bank refresh enable signal in response to the refresh timing signal. Generating bank refresh control means; And timing control means for generating the refresh timing signal by applying a delay time corresponding to the capacitance determination signal to the first bank refresh enable signal.

The refresh control method of a semiconductor memory device according to another embodiment of the present invention may include: a) driving a refresh operation signal to enable a first bank refresh enable signal; b) enabling the refresh timing signal by delaying the first bank refresh enable signal with a delay time corresponding to the capacity determination signal; And c) driving the refresh timing signal to enable a second bank refresh enable signal.

The refresh control circuit and method of the semiconductor memory device of the present invention adjusts the enable intervals of the plurality of bank refresh enable signals in response to the capacity discrimination signal, thereby making it possible to change the refresh operation section, thereby reducing the capacity of the semiconductor memory device. Create effects that can be equipped regardless.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

FIG. 1 is a configuration diagram of a refresh control circuit of a semiconductor memory device according to an embodiment of the present invention, and illustrates that the semiconductor memory device includes four banks.

As shown in the drawing, the refresh control circuit of the semiconductor memory device according to an embodiment of the present invention may respond to the refresh operation signals rfop and the first to third refresh timing signals rftm1 to rftm3. Bank refresh control means 10 for generating bank refresh enable signals brfen1 to brfen4; And timing control for generating the first to third refresh timing signals rftm1 to rftm3 by variably delaying the first to third bank refresh enable signals brfen1 to brfen3 in response to the capacity determining signal ddttg. Means (20).

Here, the timing control means 20 includes: a first delay unit 210 for delaying the first bank enable enable signal brfen1 to generate a first delay signal dly1; A first selector 220 for selectively passing the first bank refresh enable signal brfen1 or the first delay signal dly1 in response to the capacitance determination signal ddtt; A second delay unit 230 for delaying an output signal of the first selector 220 to generate the first refresh timing signal rftm1; A third delay unit 240 generating a second delay signal dly2 by delaying the second bank refresh enable signal brfen2; A second selector (250) for selectively passing the second bank refresh enable signal (brfen2) or the second delay signal (dly2) in response to the capacity determination signal (dndtg); A fourth delay unit 260 for delaying an output signal of the second selector 250 to generate the second refresh timing signal rftm2; A fifth delay unit 270 for delaying the third bank refresh enable signal brfen3 to generate a third delay signal dly3; A third selector (280) for selectively passing the third bank refresh enable signal (brfen3) or the third delay signal (dly3) in response to the capacity determination signal (dndtg); And a sixth delay unit 290 for delaying the output signal of the third selector 280 to generate the third refresh timing signal rftm3.

Here, the capacitance determination signal ddttg is a signal indicating the size of the capacitance of the semiconductor memory device including the refresh control circuit, and may be generated using a fuse option. Here, when the capacitance determining signal ddttg is at a high level, it indicates that the capacity of the current semiconductor memory device is relatively small, and the capacitance determining signal ddttg is at a low level. In this case, it will be assumed that the capacity of the current semiconductor memory device is in a relatively large state.

Meanwhile, the first to sixth delay units 210, 230, 240, 260, 270, and 290 may all have the same delay value. Preferably, in particular, the first delay unit 210, the third delay unit 240, and the fifth delay unit 270 all have the same value, and the second delay unit 230 and the fourth delay unit 270 have the same value. The delay unit 260 and the sixth delay unit 290 are set to have the same value.

When the refresh operation signal rfop is enabled, the bank refresh control means 10 generates the first bank refresh enable signal brfen1 by driving the refresh operation signal rfop. Then, the timing control unit 20 generates the first refresh timing signal rftm1 by delaying the first bank refresh enable signal brfen1. At this time, the first selector 220 of the timing control means 20 passes the first bank refresh enable signal brfen1 when the potential of the capacitance determining signal ddttg is at a high level, and the capacitance When the potential of the determination signal ddttg is at a low level, the first delay signal dly1 output from the first delay unit 210 is passed. According to the operation of the first selector 220, an enable timing of the first refresh timing signal rftm1 output from the second delay unit 220 is determined. That is, the timing control means 20 generates the first refresh timing signal rftm1 by applying a delay time corresponding to the capacitance determination signal ddtdt to the first bank refresh enable signal brfen1. .

Thereafter, the bank refresh control means 10 drives the first refresh timing signal rftm1 to generate the second bank refresh enable signal brfen2. The timing control means 20 generates the second refresh timing signal rftm2 by delaying the second bank refresh enable signal brfen2 with a delay time corresponding to the capacitance determination signal ddttg.

The operation of the bank refresh control means 10 and the timing control means 20 is continuously performed, and the third refresh timing at which the bank refresh control means 10 is output from the timing control means 20. The fourth bank refresh enable signal brfen4 is enabled by driving the signal rftm3, which is completed.

The operation of the refresh control circuit as described above can be more easily understood through the timing diagram of FIG. 2.

Referring to FIG. 2, the first to third refresh timings of the refresh operation signal rfop when the potential of the capacitance determining signal ddtdt is high level (CASE I) and low level (CASE II). The timings of the signals rftm1 to rftm3 and the first to fourth bank refresh enable signals brfen can be viewed.

That is, the first bank refresh enable signal brfen1 is generated by the refresh operation signal rfop, and then the first refresh timing signal rftm1 is generated by the first bank refresh enable signal brfen1. Is generated. Similarly, each bank enable signal and each refresh timing signal affect each other's enable timing.

Here, in the first case (CASE I) and the second case (CASE II) it can be seen that the generation timing of the first to fourth refresh timing signals rftm1 to rftm4 are different. This difference is due to the difference in the amount of delay that the timing control means 20 has according to the capacitance discrimination signal ddttg, so that the first case (CASE I) and the second case (CASE II) The lengths of the refresh operation sections are different from each other.

As described above, the refresh control circuit of the semiconductor memory device according to an exemplary embodiment may change the total refresh operation period as described above in response to the capacitance determination signal ddttg. Therefore, the refresh control circuit can be provided irrespective of the capacity of the semiconductor memory device, thereby making it possible to improve the efficiency of production time and cost of the semiconductor memory device.

FIG. 3 is a detailed configuration diagram of the first delay unit illustrated in FIG. 1, wherein the first delay unit 210 of the timing control unit 20 includes remaining second to sixth delay units 230, 240, 260, 270, Since it is configured in the same form as 290, the description of the configuration and operation of the first delay unit 210 is shown to replace the description of the remaining delay unit.

As illustrated, the first delay unit 210 includes: a first inverter IV1 inverting the first bank refresh enable signal brfen1 and outputting the inverted signal to a first node N1; A second inverter IV2 inverting the potential applied to the first node N1 to output the first delay signal dly1; First and second capacitors CAP1 and CAP2 provided between a supply terminal of an external power supply VDD and the first node N1; And third and fourth capacitors CAP3 and CAP4 provided between the first node N1 and a ground terminal.

In addition, the first delay unit 210 further includes first to fourth fuses FS1 to FS4 between the first to fourth capacitors CAP1 to CAP4 and the first node N1. .

As such, the first delay unit 210 is configured in the form of a general delay circuit. However, since the first to fourth fuses FS1 to FS4 are provided, the delay amount of the first delay unit 210 may be adjusted according to artificial control thereof. As such, since the enable timing of the first to third refresh timing signals rftm1 to rftm3 can be finely adjusted, more efficient control over the total refresh period of the refresh control circuit is possible.

Here, only the configuration and operation of the first delay unit 210 have been described, but the second to sixth delay units 230, 240, 260, 270, and 290 may also have the same configuration and operation as the first delay unit 210. It should be understood to have an operation.

FIG. 4 is a detailed configuration diagram of the first selection unit illustrated in FIG. 1. Since the first to third selection units 220, 250, and 280 are configured in the same shape, the first selection unit 220 is configured. The description of the above is to replace the description of the remaining selection.

As shown, the first selector 220 includes: a second node N2 for outputting the first refresh timing signal rftm1; A third inverter IV3 that receives the capacitance determination signal ddttg; The first passgate PG1 transferring the first bank refresh enable signal brfen1 to the second node N2 in response to the capacitance determination signal ddtdt and the output signal of the third inverter IV3. ; And a second pass gate PG2 which transmits the first delay signal dly1 to the second node N2 in response to the capacitance determination signal ddtdt and the output signal of the third inverter IV3. Include.

With this configuration, the first selector 220 uses the first bank refresh enable signal brfen1 as the first refresh timing signal rftm1 when the potential of the capacitance discrimination signal ddttg is at a high level. Output Accordingly, the enable interval between the first bank refresh enable signal brfen1 and the second bank refresh enable signal brfen2 is relatively short.

On the other hand, when the potential of the capacitance determining signal ddttg is at the low level, the first selector 220 outputs the first delay signal dly1 as the first refresh timing signal rftm1. Accordingly, the enable interval between the first bank refresh enable signal brfen1 and the second bank refresh enable signal brfen2 is relatively long.

Herein, only the configuration and operation of the first selector 220 have been described, but it should be understood that the configuration and operation of the second selector 250 and the third selector 280 are also implemented in such a form. .

As described above, the refresh control circuit of the semiconductor memory device of the present invention can change the enable interval of each bank refresh enable signal in accordance with the state of the capacity discrimination signal. Accordingly, the refresh control circuit may be applied to refresh operation sections of various types of semiconductor memory devices only by changing the state of the capacity determining signal, and thus may be provided regardless of the capacity of the semiconductor memory device. Due to the implementation of the refresh control circuit of the semiconductor memory device, in the production of the semiconductor memory device, the efficiency of time and cost can be improved.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a block diagram of a refresh control circuit of a semiconductor memory device according to an embodiment of the present invention;

2 is a timing diagram for describing an operation of a refresh control circuit of the semiconductor memory device shown in FIG. 1;

3 is a detailed configuration diagram of the first delay unit illustrated in FIG. 1;

4 is a detailed block diagram of the first selection unit illustrated in FIG. 1.

<Description of the symbols for the main parts of the drawings>

10: bank refresh control means 20: timing control means

Claims (13)

Bank refresh control means for generating a plurality of bank refresh enable signals in response to a refresh operation signal and a plurality of refresh timing signals; And And timing control means for generating the plurality of refresh timing signals by variably delaying the plurality of bank refresh enable signals in response to a capacity determination signal. And an interval at which the plurality of refresh timing signals are activated is adjusted according to a delay amount of the plurality of bank refresh enable signals. The method of claim 1, The bank refresh control means is configured to drive the refresh operation signal and the plurality of refresh timing signals, respectively, to generate the plurality of bank refresh enable signals that are sequentially enabled. Circuit. The method of claim 2, The capacity determining signal is a signal indicating the size of the capacity of the semiconductor memory device provided with the refresh control circuit, and when the capacity determining signal is activated, indicates that the memory capacity of the semiconductor memory device is smaller than when it is deactivated. And a refresh control circuit of the semiconductor memory device. The method of claim 3, wherein The timing control means, When the capacity determination signal is inactivated, the refresh control of the semiconductor memory device is configured to generate the plurality of refresh timing signals by giving a greater delay time to the plurality of bank refresh enable signals than when the capacity determination signal is activated. Circuit. The method of claim 4, wherein The timing control means, A plurality of first delay units configured to respectively delay the plurality of bank refresh enable signals to generate respective delay signals; A plurality of selectors configured to selectively pass the plurality of bank refresh enable signals or the plurality of delay signals in response to the capacitance determination signal; And A plurality of second delay units configured to delay the output signals of the plurality of selectors, respectively, to generate the plurality of refresh timing signals; And a refresh control circuit of the semiconductor memory device. Bank refresh control means for generating a first bank refresh enable signal in response to a refresh operation signal, and generating a second bank refresh enable signal in response to a refresh timing signal; And And timing control means for generating the refresh timing signal by applying a delay time corresponding to the capacitance determination signal to the first bank refresh enable signal. And a time point at which the refresh timing signal is activated is adjusted according to a delay amount of the first bank refresh enable signal. The method of claim 6, The capacity determining signal is a signal indicating the size of the capacity of the semiconductor memory device provided with the refresh control circuit, and when the capacity determining signal is activated, indicates that the memory capacity of the semiconductor memory device is smaller than when it is deactivated. And a refresh control circuit of the semiconductor memory device. The method of claim 7, wherein The timing control means, A refresh control circuit of the semiconductor memory device according to claim 1, wherein when the capacitance determination signal is deactivated, the refresh timing signal is generated by giving a greater delay time to the first bank refresh enable signal than when the capacitance determination signal is deactivated. . The method of claim 8, The timing control means, A first delay unit configured to delay the first bank refresh enable signal to generate a delay signal; A selector configured to selectively pass the first bank refresh enable signal or the delay signal in response to the capacitance determination signal; And A second delay unit configured to delay the output signal of the selector to generate the refresh timing signal; And a refresh control circuit of the semiconductor memory device. a) driving the refresh operation signal to enable the first bank refresh enable signal; b) enabling the refresh timing signal by delaying the first bank refresh enable signal with a delay time corresponding to the capacity determination signal; And c) driving the refresh timing signal to enable a second bank refresh enable signal; Refresh control method of a semiconductor memory device comprising a. The method of claim 10, The capacity determining signal is a signal indicating the size of the capacity of the semiconductor memory device provided with the refresh control circuit, and when the capacity determining signal is activated, indicates that the memory capacity of the semiconductor memory device is smaller than when it is deactivated. And a refresh control method for the semiconductor memory device. The method of claim 11, In the step b), when the capacity determination signal is deactivated, the refresh timing signal is generated by giving a greater delay time to the first bank refresh enable signal than when the capacity determination signal is deactivated. Refresh control method of a semiconductor memory device. 13. The method of claim 12, B), b-1) delaying the first bank refresh enable signal to generate a delay signal; b-2) selectively passing the first bank refresh enable signal or the delay signal in response to the capacity determination signal; And b-3) generating the refresh timing signal by delaying the signal passed in step b-2); Refresh control method of a semiconductor memory device comprising a.

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