KR101002874B1 - Sound quality adjusting circuit - Google Patents

Abstract

In the tone control circuit, the deviation of the start frequency at the time of boosting and cutting is eliminated. The components of different specific frequency bands of the original audio signal are extracted by the boost filter 202 and the cut filter 204 to obtain an extracted signal. Either of these two extraction signals is selected as a boost or a cut in the sector 206, and attenuation processing is performed by the adjustment circuit 210 for the selected extraction signal to generate a sound range adjustment signal. The synthesizing circuit 212 switches between adding and subtracting the range adjustment signal to use the range adjustment signal obtained from one of the two extracted signals.

Boost filter, filter for cut, sector, adjustment circuit, synthesis circuit

Description

Sound quality adjustment circuit {SOUND QUALITY ADJUSTING CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal characteristic adjusting circuit for adjusting the intensity of an original signal for each of a plurality of set frequency bands, and more particularly to a sound quality adjusting circuit such as a tone control circuit and a graphic equalizer.

In the audio device, a tone control circuit or a graphic equalizer that performs boost processing for increasing the level of the predetermined frequency band and cut processing for decreasing the level of the predetermined frequency band is employed.

8 is a circuit diagram showing a basic configuration of a conventional tone control circuit. In this circuit, the trouble band block 2 and the bus band block 4 are connected in series between the input terminal IN and the output terminal OUT, and the audio signal input to the input terminal IN is sequentially connected to the trouble band block 2. And output from the output terminal OUT through the bus band block 4. This circuit is composed of a main portion integrally formed on a semiconductor substrate as an integrated circuit and an exterior component connected to the external terminals 6 to 10 of the integrated circuit.

The trouble band block 2 performs a boost process or a cut process on a high frequency component of an audio signal. A capacitor C1 is connected to the external terminal 6 of the trouble band block 2. When boost processing is performed, the switches SW1 and SW3 are set to on. Thus, the trouble band block 2 constitutes a non-inverting amplifier circuit having a differential action, and amplifies the high frequency component of the input audio signal. When the cut processing is performed, the switches SW2 and SW4 are set to on. Thereby, the trouble band block 2 constitutes a low pass filter (LPF), and attenuates the high frequency component of the input audio signal.

On the other hand, the bus band block 4 performs a boost process or a cut process on the low frequency component of the audio signal. Capacitors C2 and C3 and resistor R1 are connected to the external terminals 8 and 10 of the bus band block 4. When boost processing is performed, the switches SW1 and SW3 are set to on. As a result, the bus band block 4 constitutes a non-inverting amplifier circuit having an integration effect, and amplifies the low pass component of the input audio signal. When the cut processing is performed, the switches SW2 and SW4 are set to on. As a result, the bus band block 4 constitutes a high pass filter (HPF), and attenuates low-pass components of the input audio signal.

The trouble band block 2 and the bus band block 4 each include a resistor connected in series in multiple stages in an integrated circuit. The series-connected bodies 12 and 14 of this resistor are divided into two at various ratios according to which of the switches provided at the plurality of locations are turned on, whereby the gain of the boost or the cut can be adjusted.

In addition, the frequency band boosted or cut by the trouble band block 2 and the bus band block 4 has a resistance value determined by the method of dividing the series connection bodies 12 and 14 of the resistor and the capacity of the external component. It depends on the resistance value. Here, in order to set the frequency region targeted by the trouble band block 2 to a high frequency range in the audio signal, for example, a region of about 10 Hz or more, the resistance value of the series connection body 12 and the capacitor C1 are relatively high. It must be large. Similarly, in the case where the frequency band to be processed by the bus band block 4 is set to a low range of an audio signal, for example, an area of about 100 Hz or less, the resistance value of the series connecting member 14 and the capacitor C2 , C3 needs to be made relatively large.

[Patent Document 1] Japanese Patent Application Laid-Open No. 5-090926

In integrated circuits, the number of external terminals such as pins may be limited due to package size and the like, and it may be necessary to reduce external components. In addition, the reduction of exterior components can also be expected to reduce assembly labor, reduce cost, and the like. From this point of view, it is conceivable to incorporate capacitors C1 to C3 into the integrated circuit.

However, the capacitors C1 to C3 require a relatively large value as described above. For this reason, if they are to be incorporated in an integrated circuit, there is a problem that a large area is required on a semiconductor substrate and the chip size is increased.

In addition, the present applicant, in Japanese Patent Application No. 2006-314615 (unpublished), extracts a signal of a predetermined frequency band and adjusts the amplitude of the extracted signal to create a sound range adjustment signal, and adds or subtracts it to the original audio signal. Thus, a circuit for boosting or cutting the band is proposed. In this circuit, it is relatively easy to incorporate in an integrated circuit. However, signals with different frequency characteristics were obtained in addition and subtraction, and there was a possibility of hearing loss.

The present invention provides an extraction circuit for extracting a component of a specific frequency band of the original audio signal to obtain an extraction signal in a sound quality adjustment circuit for adjusting gain for a specific frequency band with respect to the original audio signal, and extracting the extraction circuit. A gain adjustment circuit for attenuating the signal to generate a range adjustment signal, and a synthesis circuit for adding or subtracting the range adjustment signal from the gain adjustment circuit to the original audio signal, wherein the extraction circuit has two kinds of cutoff frequencies. Obtains two extracted signals, and in the synthesizing circuit, in the case of adding and subtracting the range adjustment signal, it is switched whether the range adjustment signal obtained from one of the two extraction signals is used. do.

Further, the synthesis circuit uses the sound range adjustment signal obtained by using a cutoff frequency having a lower frequency among the two extracted signals when the sound range adjustment signal is added, and subtracts the two areas when the sound range adjustment signal is subtracted. It is preferable to use a sound range adjustment signal obtained by using a cutoff frequency having a high frequency among the extracted signals.

As described above, according to the present invention, two extraction signals obtained at different cutoff frequencies are obtained and used separately in the case of adding and subtracting the tuning range adjustment signal formed therefrom. Therefore, after the addition and after the subtraction, the boosted signal and the cut signal can be obtained starting from the same frequency.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention (henceforth embodiment) is described based on drawing.

Embodiment

9 is a schematic block diagram of a tone control circuit according to an embodiment of the present invention. This circuit is basically formed integrally on a semiconductor substrate as an integrated circuit (IC).

In this circuit, the original audio signal SIN is input to the boost filter 202 and the cut filter 204. This example shows an example of boosting or cutting the low range, and the boost filter 202 and the cut filter 204 are both constituted by a low pass filter (LPF). In addition, when boosting or cutting a high range, both the boost filter 202 and the cut filter 204 should just comprise a high pass filter (HPF).

In the case of this embodiment, the boost filter 202 and the cut filter 204 are LPF, and extract a predetermined | prescribed cutoff frequency (for example, a signal of about 100 Hz or less) from an original audio signal. Here, the cutoff frequency of the boost filter 202 is set to 100 Hz, but the cutoff frequency of the cut filter 204 is set to about 150 Hz.

The extraction signal obtained by the boost filter 202 and the cut filter 204 is supplied to the selector 206.

The selector 206 selects one of the two extraction signals supplied. That is, the control circuit 208 is connected to the selector 206, and selection of the selector 206 is controlled by the control signal from the control circuit 208. Here, the control circuit 208 is supplied with an instruction signal for boost or cut for a signal of a corresponding frequency band under control of a graphic equalizer, and the selector 206 is a boost for a signal of the frequency band. The extracted signal from the boost filter 202 is selected, and if it is cut with respect to the signal of the frequency band, the extracted signal from the cut filter 204 is selected and output.

The extraction signal from the selector 206 is supplied to the adjustment circuit 210. This adjustment circuit 210 is similar to the adjustment signal generation block 22 described later, and is composed of an attenuator and an amplifier, and compresses the amplitude of the extracted signal to generate an adjustment signal. Here, the amplitude of the adjustment signal is set by the gain of the amplifier and determined by the control signal from the control circuit 208.

The obtained adjustment signal is supplied to the synthesis circuit 212 and added or subtracted to the original audio signal. That is, in the case of boost, the adjustment signal obtained by amplitude compression by the adjustment circuit 210 with respect to the extraction signal obtained by the boost filter 202 is added to the original audio signal, and in the case of cut, the cut filter 204 The adjustment signal obtained by amplitude compression by the adjustment circuit 210 with respect to the extracted signal obtained by the reference) is subtracted from the original audio signal.

Thus, in this embodiment, it has two filters, the boost filter 202 and the cut filter 204 which differ slightly in cutoff frequency. In other words, the boost filter 202 extracts a signal having a frequency band below the cutoff frequency as shown in Fig. 10A. In the adjustment circuit 210, an adjustment signal obtained by compressing the amplitude as shown in Fig. 10B is obtained. In addition, the cut filter 204 extracts a signal having a frequency band of a relatively slightly lower cutoff frequency as shown in Fig. 10E, and shows the adjustment circuit 210 in Fig. 10F. An amplitude compressed signal is obtained as shown. In this way, two frequency characteristics extraction signals and adjustment signals are obtained.

On the other hand, in the synthesis circuit 212, two kinds of adjustment signals are added or subtracted from the original audio signal having a gain of 0 Hz. In the case where the amplitude-adjusted adjustment signal in Fig. 10A is added to the original audio signal, the obtained synthesized signal is a signal in which the adjustment signal is added as it is as shown in Fig. 10C. On the other hand, when the adjustment signal of FIG. 10 (b) whose amplitude is adjusted is subtracted from the original audio signal, the obtained synthesized signal shifts the frequency at which attenuation starts to the low frequency side as shown in FIG. 10 (d). do.

This is because the cutoff frequency in the filter is determined by the rotation of the phase, and in the case of inverting and adding later, the phase with respect to the original signal is different from that in which it is added as it is.

In the present embodiment, as shown in FIG. 10E, the cutoff frequency is shifted to the high frequency side in advance with respect to the extracted signal in the case of subtraction. As a result, a signal obtained by cutting low frequencies as shown in FIG. 10F can be obtained, and the frequency at which the burst starts and the frequency at which the cut starts can be made substantially the same. Therefore, the shift | offset | difference in a boost and a cut can be eliminated, and generation | occurrence | production of the discomfort in hearing can be prevented.

[Detailed configuration 1]

1 is a schematic block diagram of a tone control circuit according to a detailed configuration 1; The circuit comprises a filter block 20, an adjustment signal generation block 22, and a synthesis circuit 24. The original audio signal SIN is input to the input terminal IN, and the gain of the high and low ranges is adjusted to boost. The output audio signal SOUT subjected to the processing or the cut processing is output from the output terminal OUT.

In this circuit, switching of boost / cut and gain setting of boost or cut for each of the high range and the low range is performed based on an indication signal from an external circuit. As the LPF 30 of the filter block 20, two different cutoff frequencies are provided for boost and cut, and either one is selected based on the instruction of boost / cut.

The filter block 20 includes a high frequency extraction circuit for extracting and outputting a high frequency component SHO from a SIN, and a low frequency extraction circuit for extracting and outputting a low frequency component SLO. Specifically, the filter block 20 has an LPF 30, which constitutes a low frequency extraction circuit.

The filter block 20 further has an inverting circuit 32 and an adding circuit 34, and these and the LPF 30 constitute a high frequency extraction circuit. The SLO extracted by the LPF 30 is input to the inversion circuit 32. Inverting circuit 32 generates a signal SLR out of phase with respect to the input SLO. For example, the inversion circuit 32 is comprised using the inverting amplifier of 1 times the amplification factor. The output SLR of the inverting circuit 32 is added with the original audio signal SIN in the adding circuit 34. here,

SLR = -SLO

Therefore, in the addition circuit 34, the low range component SLO included in the original audio signal SIN is canceled by the output SLR of the inversion circuit 32. The addition circuit 34 outputs the remaining components obtained by removing SLO from the SIN as the high-frequency component SHO.

The adjustment signal generation block 22 has a high range adjustment circuit 36 and a low range adjustment circuit 38. The high-range adjustment circuit 36 and the low-range adjustment circuit 38 gain adjustment to the high-range component SHO and low-range component SLO output from the filter block 20, respectively, and generate | generate a high-range adjustment signal SHT and a low-range adjustment signal SLT.

2 is a schematic block diagram of the high-range adjustment circuit 36 and the low-range adjustment circuit 38. The high range adjustment circuit 36 and the low range adjustment circuit 38 have a configuration common to each other. Here, the high-range adjustment circuit 36 is described using FIG. 2 as an example.

The high frequency adjustment circuit 36 consists of an amplitude control block 40 and a phase control block 42. The amplitude control block 40 controls the amplitude ratio A (# | SHT / SHO |) of the high range adjustment signal SHT to the high range component SHO input to the high range adjustment circuit 36. The phase control block 42 controls whether the phase difference of the SHT with respect to the SHO is set to 0 degrees or 180 degrees, and determines whether the SHT is the same polarity or inversion with respect to the SHO. By these amplitude control block 40 and phase control block 42, the high-range adjustment circuit 36 adjusts the gain which combined amplitude ratio and polarity with respect to SHO, and produces | generates SHT.

The amplitude control block 40 comprises an attenuator 50 and an amplifier 52. The amplifier 52 sets the gain GC according to the adjustment range of the gain GOUT of the SOUT to the SIN, amplifies the input signal from the attenuator 50 with the corresponding gain GC to generate the signal SHB, and the phase control block 42 Output to. The gain GC corresponding to the desired adjustment width of the gain GOUT may be different from each other in the boost operation and the cut operation as described later. Accordingly, the amplifier 52 is configured to receive a mode signal DM for specifying boost / cut from an external circuit and to switch the set value of the GC in accordance with the signal DM.

The attenuator 50 receives a gain control signal DG indicating a gain adjustment amount from an external circuit, and attenuates the SHO according to the signal DG and outputs it to the amplifier 52. In the case where the attenuator 50 is configured to be attenuated to -∞ [Hz], for example, the amplitude control block 40 can adjust the amplitude ratio A in the range of GC to -∞ [Hz].

The phase control block 42 includes an inversion circuit 54 and a switch circuit 56. The inversion circuit 54 generates the signal SHC out of phase with respect to the SHB input from the amplitude control block 40. For example, the inversion circuit 54 is configured using an inverting amplifier having an amplification factor of 1 times.

As described above, in the present embodiment, the low pass filter is switched between the boost and the cut. Therefore, the frequencies of boost start and cut start can be matched.

The switch circuit 56 receives the SHB from the amplitude control block 40 and the SHC from the inversion circuit 54 and selectively outputs either. The selection is made based on the mode signal DM. At boost, SHB is output as SHT, and at cut, SHC is output as SHT.

As mentioned above, although the high range adjustment circuit 36 was demonstrated, the same process is performed also about the low range adjustment circuit 38, and the low range adjustment signal SLT is produced | generated from SLO. In other words, a signal SLB of varying amplitude is generated from the SLO at the time of boost while outputting it as SLT, while a signal SLC of inverting the polarity of the SLB is generated and output as SLT at the time of cutting.

As shown in FIG. 1, the high-range adjustment signal SHT and the low-range adjustment signal SLT output by the high-range adjustment circuit 36 and the low-range adjustment circuit 38 are input to the synthesis circuit 24. The synthesizing circuit 24 also receives the original audio signal SIN, adds and synthesizes these SIN, SHT, and SLT and outputs it as SOUT.

3 is a schematic diagram for explaining the principle of tone control in the present circuit. 3 (a) to 3 (e) each show a frequency spectrum, and the horizontal axis represents the signal gain G based on the frequency f and the vertical axis based on the SIN. In FIG. 3A, the spectra 60, 62, and 64 each represent an original audio signal SIN, a low range component SLO, and a high range component SHO.

FIG. 3B shows a spectrum 70 in which the high range is boosted. At the time of high frequency boost, the high frequency adjustment circuit 36 outputs SHB as SHT as described above. In this SHB synthesis circuit 24, an SOUT having a spectrum 70 is generated, which is superimposed on SIN.

FIG. 3C shows a spectrum 72 in which the high range is cut. At the high frequency cut, the high frequency adjustment circuit 36 outputs SHC as SHT. This SHC has a reverse polarity with the high-frequency component SHO of SIN. Therefore, when SHC and SIN are synthesized in the synthesis circuit 24, the high-band component SHO of SIN is canceled in accordance with the strength of the SHC, and SOUT having a spectrum 72 is generated.

FIG. 3D illustrates a spectrum 74 in which the low range is boosted. In the low range boost, the low range adjustment circuit 38 outputs SLB as SLT. This SLB is superimposed on SIN in the synthesis circuit 24, producing an SOUT with a spectrum 74.

FIG. 3E shows a spectrum 76 in which the low range is cut. In the low range cut, the low range adjustment circuit 38 outputs SLC as SLT. Since this SLC has a reverse polarity with the low frequency component SLO of SIN, by combining SLC and SIN in the synthesis circuit 24, the low frequency component SLO of SIN cancels according to the intensity of SLC, and has a spectrum 76. SOUT is generated.

Here, for example, a case where the gain GOUT is configured to be adjustable within a range of ± 12 Hz will be described in detail. Here, when the upper limit value or the lower limit value of the adjustment range of GOUT is expressed by Gmax [k], and the amplitude ratio SOUT / SIN between SIN and SOUT at that time is expressed by Am, the following equation is established.

At the maximum boost, as can be understood from FIGS. 3B and 3D, the output signal SHB or SLB of the amplifier 52 is (Am-1) times SIN. On the other hand, at the time of maximum cut, as can be understood from FIGS. 3C and 3E, the output signal SHB or SLB of the amplifier 52 is (1-Am) times SIN. During these maximum boost and maximum cut, the attenuation ratio of the attenuator 50 is set to 0 Hz, so the amplitude ratio | Am-1 | with respect to the SIN of SHB and SLB corresponds to the gain GC of the amplifier 52. In other words,

to be. From Equations 1 and 2, the setting value of GC for GOUT = + 12 ms corresponding to the maximum boost is about 9.5 ms, and the setting value of GC for GOUT = -12 ms for maximum cut is approximately. It becomes -2.5㏈. Switching of the setting values of the GCs which differ between these boost and cut operations is performed in conjunction with the mode signal DM as described above.

Next, the LPF 30 will be further described. 4 is a circuit diagram showing a schematic configuration of the LPF 30. The basic configuration of the LPF 30 used in this apparatus is an RC active filter, which includes an op amp 80, resistors 82 and 84, and a capacitor 86, which are integrally formed on a semiconductor substrate. The input signal SIN to the tone control circuit is input to the input terminal FIN, and the output terminal of the operational amplifier 80 becomes the output terminal FOUT. A resistor 82 is connected in series between the input terminal FIN and the inverting input terminal of the operational amplifier 80. In addition, the resistance 84 and the capacitor 86 are connected in parallel between the output terminal of the operational amplifier 80 and the inverting input terminal. For example, when the resistance values of the resistors 82 and 84 are RC and the capacitance values of the capacitor 86 are CC, the cutoff frequency fC of the LPF 30 is given by the following equation.

The resistors 82 and 84 are composed of a resistance circuit capable of realizing high resistance. For example, such a resistance circuit includes a MOSFET and the like, and by using such a circuit, the resistances 82 and 84 are compared with a general resistance element formed by using polysilicon or a diffusion layer on an IC. The high resistance can be achieved while the board | substrate occupation area of () is suppressed.

In the present tone control circuit, a switched capacitor circuit is employed as the resistor circuit configuring the resistors 82 and 84, respectively, and the LPF 30 is configured as the switched capacitor filter. 5 is a schematic circuit diagram of the LPF 30 in which the resistors 82 and 84 are constituted by switched capacitor circuits.

The switched capacitor circuit includes a capacitor CSC and switch elements SW1 to SW4. The capacitor CSC is inserted in series between the input terminal and the output terminal of the switched capacitor circuit, and the switch elements SW1 and SW2 are provided between the input terminal and the output terminal and the CSC. Both ends of the capacitor CSC can be connected to the earth serving as the reference voltage source by the switch elements SW3 and SW4, respectively. Each switch element is constructed using a transistor on a semiconductor substrate. The switched capacitor circuit charges and discharges the capacitor CSC by periodically opening and closing the pair of the switch elements SW1 and SW2 and the pair of the switch elements SW3 and SW4 alternately. As a result, charge transfer occurs and a pulsed current flows between both terminals of the switched capacitor circuit, and when the switching frequency fSC is sufficiently high, the average current becomes equivalent to the current passing through the resistance. In other words, the switched capacitor circuit equivalently functions as a resistance element. The resistance value RSC is expressed by the following equation.

As shown in Equation 4, the RSC can be increased in inverse proportion to the decrease in fSC. In other words, when the switched capacitor circuit is used, RC can be increased in accordance with fSC, CC can be reduced, and the capacitor 86 can be made a size that can be easily formed on a semiconductor substrate.

For example, the RSC of the switched capacitor circuit with fSC = 250 mW and CSC = 1 pF is 4 mW. In the case where the cutoff frequency fC of the LPF 30 is set to 1 kHz, when the RC is configured using this switched capacitor circuit, the CC becomes 40 pF. In other words, the capacitance required for the LPF 30 is about 40 pF even if the CC and the CSC constituting the switched capacitor circuit are combined, so that the LPF 30 can be integrally formed on the IC by including these capacitances.

As described above, by setting RC to a high resistance value, the LPF 30 incorporates the capacitor 86 into the IC, thereby reducing the number of external pins and component points. The resistors 82 and 84 having the high resistance value RC can be configured by suppressing the occupied area on the IC, for example, by using a switched capacitor circuit. Here, the resistance circuit is composed of a plurality of elements, and requires a certain size or more. Therefore, in the filter circuit including a plurality of resistance elements each having a relatively small resistance value, as in the circuit shown in Fig. 8, even if the resistance elements are replaced by resistance circuits, the area on the semiconductor substrate is suppressed. Merit to say is hard to get. However, since the LPF 30 is configured to include only a few resistance elements having a large resistance value as described above, the effect of area suppression by replacing with a resistance circuit can be increased. In addition, from this viewpoint, the structure of the LPF 30 is not limited to the structure shown in FIG. 4, The other circuit structure which can be miniaturized by capacitor | miniaturization of a few resistance elements can also be employ | adopted.

In addition, the tone control circuit of this detailed configuration is configured to generate a high range by the difference between the low range and the original audio signal extracted using the LPF 30, but on the contrary, the tone control circuit of the tone control circuit extracted by the HPF uses the difference between the high range and the original audio signal extracted using the HPF. It can also be set as the structure which produces a low range.

[Detailed configuration 2]

6 is a schematic block diagram of a graphic equalizer according to the detailed configuration 2. The tone control circuit of the first detailed configuration adjusts the gain of the two bands of the high range and the low range. On the other hand, the graphic equalizer of this detailed configuration differs from the tone control circuit of the first detailed configuration in that it adjusts the gain of three bands of high, mid and low ranges, but also has a common point. As the LPFs 110 and 112 of the filter block 100, two having a cutoff frequency different from each other for boost and cut are provided, and either one is selected based on the instruction of boost / cut.

This circuit is integrally formed on a semiconductor substrate as an IC. In this circuit, the original audio signal SIN is input to the input terminal IN, and a boost process and a cut process can be performed for each of the bands of the high, mid, and low ranges, and the output audio signal SOUT of which the gain of each band is respectively adjusted. Output from the output terminal OUT. In this circuit, switching of boost / cut for each band and gain setting of boost or cut are performed based on an indication signal from an external circuit.

The circuit comprises a filter block 100, an adjustment signal generation block 102 and a synthesis circuit 104. The filter block 100 includes the LPFs 110 and 112, the inversion circuits 114 and 116, and the addition circuits 118 and 120. The adjustment signal generation block 102 also includes a low range adjustment circuit 122, a mid range adjustment circuit 124, and a high range adjustment circuit 126.

The LPFs 110 and 112 can each be configured in the same manner as the first detailed configuration, and in particular, the switched capacitors can be used to provide a built-in capacitor. Here, the cutoff frequency fC1 of the LPF 110 is set lower than the cutoff frequency fC2 of the LPF 112.

Incidentally, the inverting circuits 114 and 116 are the same circuits as the inverting circuit 32 in the tone control circuit of the first detailed configuration, and the adding circuits 118 and 120 are similar to the adding circuit 34. to be. The low range adjustment circuit 122, the mid range adjustment circuit 124, and the high range adjustment circuit 126 can be configured as shown in FIG.

The filter block 100 includes an extraction circuit for each band, and extracts the high frequency component SHO, the midrange component SMO, and the low frequency component SLO from the SIN. Specifically, the LPF 110 constitutes a low range extraction circuit. In addition, the LPFs 110 and 112, the inversion circuit 114 and the addition circuit 118 constitute a midrange extraction circuit. In addition, the LPF 112, the inversion circuit 116, and the addition circuit 120 constitute a high frequency extraction circuit.

7 is a schematic diagram for explaining the principle of extraction processing of each band component of the present circuit. (A) and (b) of FIG. 7 respectively show the frequency spectrum, and the horizontal axis represents the signal gain G based on the frequency f and the vertical axis based on SIN. In FIG. 7A, the spectra 130, 132, and 134 represent the original audio signals SIN and the output signals SLPF1 of the LPF 110 and the output signals SLPF2 of the LPF 112, respectively. In addition, the spectrums 136, 138, and 140 shown in Fig. 7B show low-band component SLO, mid-range component SMO, and high-band component SHO included in the original audio signal SIN, respectively.

The output signal SLPF1 of the LPF 110 is output from the filter block 100 as the low range component SLO, and is input to the low range adjustment circuit 122. In other words, the spectrum 130 and the spectrum 136 are common. In addition, the SLO is inverted by the inversion circuit 114 and then input to the addition circuit 118. The addition circuit 118 further receives SLPF2 from the LPF 112, obtains the difference between SLPF2 and SLPF1, and extracts the midrange component SM0 represented by the spectrum 138, as shown in the following equation. The extracted SM0 is input from the filter block 100 to the midrange adjustment circuit 124.

The output signal SLPF2 of the LPF 112 is input to the addition circuit 118 described above, and also to the inversion circuit 116. The inversion circuit 116 inverts SLPF2 and inputs it to the addition circuit 120. The addition circuit 120 is further inputted with the original audio signal SIN, obtains the difference between SIN and SLPF2, and extracts the high-frequency component SHO represented by the spectrum 140, as shown by the following equation. The extracted SHO is input from the filter block 100 to the high voice adjustment circuit 126.

In the adjustment signal generation block 102, the low range adjustment circuit 122, the mid range adjustment circuit 124, and the high range adjustment circuit 126 respectively perform gain adjustments to the low range component SLO, the mid range component SMO, and the high range component SHO, A low range adjustment signal SLT, a mid range adjustment signal SMT, and a high range adjustment signal SHT are generated.

The low range adjustment signal SLT, the mid range adjustment signal SMT, and the high range adjustment signal SHT output from the adjustment signal generation block 102 are input to the synthesis circuit 104. The synthesis circuit 104 also receives the original audio signal SIN, and adds and synthesizes these SINs, SLTs, SMTs, and SHTs, and outputs them as SOUT.

As described above, each adjustment signal SLT, SMT, SHT is generated as a positive signal at the time of boost in accordance with the mode signal DM in the circuit shown in FIG. It is generated as a signal of polarity. The synthesizing circuit 104 combines these adjustment signals with the original audio signal SIN so that boost processing is performed in the frequency band where the positive adjustment signal overlaps, and cut processing is performed in the frequency band canceled by the negative adjustment signal. Creates a SOUT.

In this detailed configuration, an example of a graphic equalizer for dividing an original audio signal into three frequency bands for adjustment is described as the simplest case. Applicable In that case, (n-1) LPFs are used. When the k-th LPF (1≤k≤n-1) cutoff frequency is represented by fCk, fCk is set corresponding to the boundary between the k-th frequency band and the (k + 1) th frequency band.

This holds true.

The first extraction circuit extracts, by the first LPF, the component of the lowest first frequency band from the original audio signal. In the above detailed configuration, the LPF 110 corresponds to the first LPF.

The k-th extraction circuit (2≤k≤n-1) generates a difference between the output signal of the k-th LPF and the output signal of the (k-1) th LPF with respect to the original audio signal, and outputs it as a component of the k-th frequency band. do. In the above detailed configuration, the process represented by the expression (5) when generating the SMO corresponds to the process of generating this difference.

The nth extraction circuit generates a difference between the original audio signal and the (n-1) th LPF output signal and outputs the difference as the component of the nth frequency band. In the above detailed configuration, the process represented by the equation (6) when generating the SHO corresponds to the process of generating this difference.

In addition, although the graphic equalizer of this detailed structure was taken as the structure which extracts the component of each frequency band using LPF (110, 112), it can also be set as the structure which extracts the component of each frequency band using HPF.

The detailed configuration described above was described with respect to a sound quality adjustment circuit that adjusts the characteristics of the audio signal as an original signal. However, the present invention can also be applied to a signal characteristic adjusting circuit which receives other than an audio signal as an original signal and performs gain adjustment for each frequency band. For example, such a signal characteristic adjusting circuit may be a video signal as an original signal. For example, the present invention can be applied to a signal characteristic adjustment circuit which boosts / cuts each of a high pass component and a low pass component with respect to a luminance signal constituting a video signal.

1 is a schematic block diagram of a tone control circuit as a first detailed configuration of the present invention;

2 is a schematic block diagram of an adjustment circuit for performing gain adjustment for components in each band.

3 is a schematic diagram for explaining the principle of tone control in the first detailed configuration of the present invention;

4 is a circuit diagram showing a schematic configuration of an LPF used in the detailed configuration of the present invention.

FIG. 5 is a schematic circuit diagram of an LPF in which the resistor shown in FIG. 4 is composed of a switched capacitor circuit. FIG.

6 is a schematic block diagram of a graphic equalizer as a second detailed configuration of the present invention.

It is a schematic diagram for demonstrating the principle of the extraction process of each band component in the 2nd detailed structure of this invention.

8 is a circuit diagram showing a basic configuration of a conventional tone control circuit.

9 is a schematic block diagram of a tone control circuit according to an embodiment of the present invention;

10 is a view for explaining the operation of the tone control.

<Explanation of symbols for the main parts of the drawings>

20, 100: filter block

22, 102: adjustment signal generation block

24, 104: synthetic circuit

30, 110, 112: LPF

32, 54, 114, 116: inversion circuit

34, 118, 120: addition circuit

36, 126: high range adjustment circuit

38, 122: bass adjustment circuit

40: amplitude control block

42: phase control block

50: attenuator

52: amplifier

56: switch circuit

124: midrange adjustment circuit

Claims (2)

In a sound quality adjustment circuit for adjusting the gain for a specific frequency band with respect to the original audio signal, An extraction circuit for extracting components of a specific frequency band of the original audio signal to obtain an extraction signal; A gain adjustment circuit which performs attenuation processing on the extraction signal of the extraction circuit to generate a range adjustment signal; A synthesis circuit for adding or subtracting a sound range adjustment signal from the gain adjustment circuit to the original audio signal Has, The extraction circuit obtains two extraction signals using two kinds of cutoff frequencies, and in the synthesis circuit, the sound range obtained from any one of the two extraction signals when adding and subtracting the sound range adjustment signal. The adjustment signal is switched or not, The synthesis circuit uses a range adjustment signal obtained by using a cutoff frequency having a lower frequency among the two extraction signals when adding the range adjustment signal, and subtracts the two extraction signals when the range adjustment signal is subtracted. A sound quality adjustment circuit using a sound range adjustment signal obtained by using a cutoff frequency having a high frequency. delete

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