KR100996017B1 - Page buffer for flash memory apparatus - Google Patents

Abstract

The present invention relates to a page buffer of a flash memory device, wherein a page buffer is positioned above and below a flash memory cell, and a corresponding page buffer is shared between four bit lines at an upper portion and a lower portion thereof. The time required for precharging can be shortened, and the page buffer layout problem due to the high integration of flash memory cells can be solved.

Page Buffer, Precharge, Precharge Time, Flash Memory Cell

Description

Page buffer for flash memory apparatus             

1 is a page buffer circuit diagram of a flash memory device of the present invention.

2 is a circuit diagram of a latch unit of the present invention.

<Explanation of symbols for main parts of the drawings>

100: flash memory cell 200, 300: page buffer

210, 310: Latch

The present invention relates to a page buffer of a flash memory device, and more particularly to a page buffer of a flash memory device capable of reducing the precharging time of a bit line.

In the NAND flash device, the bit line data sensing method applies a constant voltage to the bit line, and then changes the bit line low voltage according to the ON / OFF state of the cell. Use the way. As the cell directivity increases, the bit line precharge time consumes a lot of time due to the large RC value.

Accordingly, the present invention can reduce the time to precharge the bit line by placing the page buffer in the upper and lower memory cells, and sharing the bit line between the page buffer corresponding to the upper and lower, respectively, to solve the above problems Provides a page buffer for a flash memory device.

A plurality of upper page buffers disposed above the flash memory cell array according to the present invention; And a plurality of lower page buffers disposed under the flash memory cell array, each of the upper and lower page buffers sharing at least four bit lines among the plurality of bit lines included in the flash memory cell array. The upper and lower page buffers sharing the same bit lines may simultaneously precharge the selected bit line during the precharge operation.

Preferably, the upper and lower page buffers sharing the four bit lines, respectively, a precharge node; A PMOS transistor applying a precharge voltage to the precharge node according to a precharge signal; A latch unit connected to the precharge node to latch predetermined data according to an external latch signal and the precharge voltage; And first to fourth NMOS transistors connected between the four bit lines and the precharge node, wherein the first and third NMOS transistors are selected from the four bit lines according to an odd bit line selection signal. Two bit lines are selected to supply the precharge voltage, and the second and fourth NMOS transistors select the other two bit lines among the four bit lines according to the even bit line selection signal, thereby providing the precharge voltage. It characterized in that the supply.

Preferably, the latch unit includes a first latch for sensing and latching predetermined data, and fifth and sixth terminals connected between one input terminal of the first latch and a ground power source, respectively, for driving according to the precharge voltage and the latch signal. And a seventh NMOS transistor connected between the NMOS transistor and the other input terminal of the first latch and the output terminal of the latch unit, and driven according to a program signal.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It will be apparent to those skilled in the art that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, It is provided to let you know. Like numbers refer to like elements in the figures.

1 is a page buffer circuit diagram of a flash memory device of the present invention.

Referring to FIG. 1, a flash memory cell array 100 including a plurality of bit lines BL <1: Z> and first to fourth bit lines BL1 according to bit line selection signals BLOS and BLES. First to Nth upper page buffers 200-1 to 200 -K precharging two bit lines among the blocks BL4 to BL4 and the first to fourth bit lines BL1 according to the bit line selection signals BLOS and BLES. 1 to N-th lower page buffers 300-1 to 300-K for precharging two bit lines identical to the first to N-th upper page buffers 200-1 to 200-K. .

The first to Nth upper page buffers 200-1 to 200 -K supply a precharge voltage (power supply voltage) to the precharge node Q1 according to the precharge node Q1 and the precharge signal PRES. A first latch unit 210 connected to a first PMOS transistor P1, a precharge node Q1, and latching predetermined data according to an external latch signal LCS and a precharge voltage, and a first latch unit 210. To the fourth bit lines BL1 to BL4 and the precharge node Q1, and precharge voltages are applied to the first and third bit lines BL1 and BL3 according to the odd bit line selection signals BLOS1 and BLOS3. Second and fifth supplies precharge voltages to the second and fourth bit lines BL2 and BL4 according to the first and third NMOS transistors N1 and N3 and the even bit line selection signals BLES2 and BLES4. 4 NMOS transistors N2 and N4. Preferably, the first NMOS transistor N1 is driven according to the first odd bit line selection signal BLOS1, and the second NMOS transistor N2 is driven according to the second even bit line selection signal BLES2, and the third NMOS transistor N1 is driven. It is effective to drive the NMOS transistor N3 according to the third odd bit line selection signal BLES3 and to drive the fourth NMOS transistor N4 according to the fourth even bit line selection signal BLOS4.

2 is a circuit diagram of a latch unit of the present invention.

Referring to FIG. 2, the first latch unit 210 is connected between a first latch L1 for sensing and latching predetermined data, and one input terminal of the first latch L1 and the ground power source Vss, respectively. Connected between the fifth and sixth NMOS transistors N5 and N6 driven according to the precharge voltage and the latch signal LCS, the other input terminal of the first latch L1, and the output terminal of the first latch unit 210. , The seventh NMOS transistor N7 is driven according to the program signal PGM.

The first to Nth lower page buffers 300-1 to 300-K have the same configuration as the above-described first to Nth upper page buffers 200-1 to 200-K, and thus description thereof will be omitted.

The operation of the page buffer of the present invention having the above-described configuration will now be described with reference to the drawings.

NAND flash memory, like DRAM, requires high capacity and high density. Due to the high level of integration, it is difficult to draw the sense and latch page buffers on the bit line pitch, so that the upper and lower page buffers are located above and below the flash memory cell array, respectively. . Of course, by connecting the odd and even bit lines to one page buffer, one bit line can be selected and pre-filled according to the odd bit line selection signal and the even bit line selection signal. According to the present invention, the page buffers facing each other at the top and the bottom share four bit lines at the same time, and simultaneously apply the precharge voltage to the bit lines at the top and bottom according to the bit line selection signal, thereby applying the bit line pre-autonomous time (Bit). Line Precharge Time can be improved.

Reading a selected cell in a flash memory cell array includes precharging the selected bit line first, evaluating the cell, and sensing and latching the cell.

When the precharge signal PRES becomes logic low, the upper and lower first and 101th PMOS transistors P1 and P101 are driven to supply power voltages Vcc to the first and 100th precharge nodes Q1 and Q101. Apply a precharge voltage. The latch signal LCS becomes logic high to set the latches of the first and 101th latch units 210 and 310 to 0, which is a logic low. When the first and third odd bit line selection signals BLOS1 and BLOS3 become logic high, the first, third, 101, and 103 NMOS transistors N1, N3, N101, and N103 are driven to drive the first and third bit lines. The precharge voltage is applied to the three bit lines BL1 and BL3. Meanwhile, when the second and fourth even bit line selection signals BLES2 and BLES4 become logic high, the second, fourth, 102th and 104th NMOS transistors N2, N4, N102, and N104 are driven to drive the second. And a precharge voltage is applied to the fourth bit lines BL2 and BL4. By precharging two bit lines simultaneously in the upper and lower page buffers, the precharge time of the bit lines can be reduced.                     

After the cell evaluation, the sensing and latching operation using the change of the precharge voltage applied to the bit line is performed to read whether the selected cell is programmed or erased.

As described above, the present invention pre-charges bit lines by placing page buffers at the top and bottom of a flash memory cell array, and allowing corresponding page buffers at the top and bottom to share four bit lines. Can shorten the time required.

In addition, the page buffer layout problem due to high integration of flash memory cells can be solved.

Claims (3)

A plurality of upper page buffers disposed above the flash memory cell array; And A plurality of lower page buffers disposed under the flash memory cell array; Each of the upper and lower page buffers shares at least four bit lines among the plurality of bit lines included in the flash memory cell array, and the upper and lower page buffers sharing the same bit lines are selected during the precharge operation. Simultaneously precharging the page buffer of the flash memory device. The method of claim 1, wherein the upper and lower page buffers sharing the four bit lines, respectively, Precharge node; A PMOS transistor applying a precharge voltage to the precharge node according to a precharge signal; A latch unit connected to the precharge node to latch predetermined data according to an external latch signal and the precharge voltage; And First to fourth NMOS transistors connected between the four bit lines and the precharge node, wherein the first and third NMOS transistors each include two of the four bit lines according to an odd bit line selection signal; Selects one bit line to supply the precharge voltage, and the second and fourth NMOS transistors select another two bit lines of the four bit lines according to an even bit line selection signal to obtain the precharge voltage. Supplying a page buffer of a flash memory device. The method of claim 2, wherein the latch unit, A first latch for sensing and latching predetermined data; Fifth and sixth NMOS transistors connected between one input terminal of the first latch and a ground power source to drive according to the precharge voltage and the latch signal, respectively; And And a seventh NMOS transistor connected between another input terminal of the first latch and an output terminal of the latch unit, and driven according to a program signal.

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