KR100994549B1 - Splitter circuit - Google Patents

Abstract

The present invention improves the isolation between the output ports. To this end, the present invention is located between the input port (1), the output port (2), the output port (3), between the input port (1) and the output port (2), the signal of the input port (1) FET 6 which amplifies and outputs to the output port 2 and between the input port 1 and the output port 3, the FET to amplify the signal of the input port (1) to output to the output port (3) (11) and an impedance circuit connected between the output ports (2, 3). The impedance circuit includes a series circuit including an inductor 15 and a diode 17 in series form, one end of which is connected to the output port 2, and an inductor 16 and a diode connected to the one end of the output port 3. A series circuit including (18) in series and a resistance element 19 connected between the other ends of the two series circuits and ground. The diodes 17 and 18 are connected so that a current flows in the forward direction when the voltage of the power supply is applied to the FETs 6 and 11.

Isolation, Impedance Circuit

Description

Splitter circuit

The present invention relates to a splitter circuit, in particular to a splitter circuit comprising an active element.

Splitter circuits are widely used in STB (Set-Top-Box) / TV for CATV / Digital TV. A splitter circuit (active splitter circuit) including an active element such as an FET is used when gain is needed. One important performance of such splitter circuits is isolation between the output ports. In general, since a feedback circuit from an output to an input is mounted for widening, sufficient performance cannot be obtained simply by improving the isolation of the FET as an active element, and the isolation is improved in the circuits around the FET. Needs to be.

9 is a circuit diagram of a splitter circuit described in Patent Document 1. FIG. The input terminal 116 is connected to the gates of the FETs Q1 and Q2 via the inductor L1 while being grounded via the capacitor C. The FET Q1 grounds the source, connects the drain to the output port 118, and connects a feedback circuit 121 composed of the inductor L2 and the resistor R1 between the drain and the gate. The FET Q2 grounds the source, connects the drain to the output port 120, and connects a feedback circuit 123 composed of the inductor L3 and the resistor R2 between the drain and the gate. Also, in order to improve the isolation of the output port 118 and the output port 120, a circuit 114 composed of a resistor R3 and an inductor L4 is connected between the output ports 118, 120.

In the splitter circuit having the above-described configuration, when the FET Q1 and the FET Q2 are operating, the RF signal input from the output port 118 is a signal passing through the circuit 114 and the feedback circuit 121 of the FET Q1. Or branch to signal passing through FET Q1. The signal passing through the circuit 121 or the FET Q1 further passes through the paths 110 and 112 and is input to the FET Q2 and amplified. At this time, the phase is shifted by 180 degrees and output to the output port 120. On the other hand, the signal passing through the circuit 114 arrives at the output port 120 without being phase shifted. Therefore, the output port 120 is canceled by a signal whose phase is not shifted and a signal shifted by 180 degrees, respectively, so that the signal at the output port 120 is attenuated, and the isolation is improved.

Moreover, the circuit which operates similarly is also described in patent document 2. As shown in FIG.

Patent Document 1: US Patent No. 5045822

Patent Document 2: US Patent No. 6577198

 The following analysis is given in the present invention.

 In Fig. 9, the isolation is improved when the FETs Q1 and Q2 are in the ON state. However, when the FETs Q1 and Q2 are in the OFF state, the FETs Q1 and Q2 are almost open to the RF signal, and the signal input from the output port 118 passes through the circuit 114 to output the output port 120. The output is deteriorated. Therefore, when the power supply of the splitter circuit is OFF, the circuits and devices connected to the output ports 118 and 120 are affected by each other.

Fig. 10 is a diagram showing isolation characteristics in a conventional circuit. In Fig. 10, curve A is a characteristic when FETs Q1 and Q2 are in operation, and curve B is a characteristic when FETs Q1 and Q2 are OFF. As shown by curve B in Fig. 10, it can be seen that the isolation is deteriorated when the FET is off.

A splitter circuit according to one aspect (side) of the present invention is located between an input terminal, a first output terminal, a second output terminal, and an input terminal and a first output terminal. And a first amplifier for amplifying the signal of the input terminal and outputting the signal to the first output terminal, and between the input terminal and the second output terminal. And a second amplifier and an impedance circuit connected between the first and second output terminals. The impedance circuit is configured to have a predetermined impedance when the first power supply is supplied to the first and second amplifiers, and to be open when the first power supply is not supplied to the first and second amplifiers. do.

The splitter circuit according to another aspect (side) of the present invention includes an input terminal, an output terminal of the i th (an integer of i = 1 to n, n is an integer of 2 or more), an input terminal and an i th output terminal, The i-th amplifier which amplifies the signal of the input terminal and outputs it to the i-th output terminal, and j (an integer of j = 1 to n-1) and k (an integer of k = j + 1 to n). And an impedance circuit connected between the output terminals of < RTI ID = 0.0 >) < / RTI > and the impedance circuit becomes a predetermined impedance when the first power source is supplied to the jth and kth amplifiers, and the first power source is the jth and It is configured to be open when it is not supplied to the amplifier of k.

A splitter circuit according to still another aspect (side face) of the present invention includes an input terminal, an output terminal of i-th (an integer of i = 1 to n, n is an integer of 2 or more), an input terminal, and an i-th output terminal. And an i-th amplifier which amplifies the signal of the input terminal and outputs it to the i-th output terminal, and an impedance circuit connected to two or more output terminals of the first to n-th output terminals, In the impedance circuit, when a first power source is supplied to an amplifier corresponding to two or more output terminals, respectively, a predetermined impedance is established between two output terminals selected from two or more output terminals, and the first power source is turned on. When not supplied, the impedance at the two output terminals to be selected is configured to be in an open state.

According to the present invention, the isolation between the first and second output terminals can be improved regardless of the power supply in the amplifier.

The splitter circuit according to the embodiment of the present invention is located between an input terminal (input port), a first output terminal (output port), a second output terminal, and an input terminal and a first output terminal. And a first amplifier for amplifying the signal of the input terminal and outputting the signal to the first output terminal, and between the input terminal and the second output terminal. And a second amplifier and an impedance circuit connected between the first and second output terminals. The impedance circuit is configured to have a predetermined impedance when the first power supply is supplied to the first and second amplifiers, and to be open when the first power supply is not supplied to the first and second amplifiers. do.

In the splitter circuit of the present invention, the impedance circuit includes a first series circuit including a first inductor and a first diode in series with one end connected to a first output terminal, and one end connected to a second one. A resistor connected between a second series circuit including a second inductor and a second diode in series, connected to an output terminal, and the other end of the first and second series circuits and a second power supply; An element is provided. It is preferable that the 1st and 2nd diodes are connected so that a current may flow in a forward direction, when the voltage of a 1st power supply and a 2nd power supply differs.

In the splitter circuit of the present invention, the voltage of the first power supply is set higher than the voltage of the second power supply, and the first diode connects an anode to the first output terminal via the first inductor. Connect a cathode to one end of the resistor, the second diode connects the anode to the second output terminal via the second inductor, and connects the cathode to one end of the resistor, It is preferable to connect the other end of the resistance element to the second power source.

In the semiconductor device of the present invention, the splitter circuit is preferably included.

In the splitter device of the present invention, the semiconductor device including the above-described splitter circuit except for the resistance element may be provided outside the semiconductor device and connected to the semiconductor device via a bonding wire.

In the splitter circuit as described above, when the first power source is supplied to the first and second amplifiers, cancellation occurs due to a signal without phase shift and a signal shifted by 180 degrees at the output terminal. In addition, when the first power source is not supplied to the first and second amplifiers, it is interrupted by an impedance circuit in which the output terminals are open. Therefore, the isolation between the output terminals can be maintained regardless of whether the first power is supplied.

EMBODIMENT OF THE INVENTION Hereinafter, it demonstrates in detail with reference to drawings, in response to an Example.

(Example 1)

1 is a circuit diagram of a splitter circuit according to a first embodiment of the present invention. In Fig. 1, 1 denotes an input port, and 2 and 3 denote an output port. The input port 1 is connected to the gates of the amplification FETs 6 and 11 via the DC cut capacitors 5 and 10. The sources of the FETs 6 and 11 are source circuits 20, respectively. And the ground of the FETs 6 and 11 are connected to the input port 1 via the feedback circuits 4 and 9, respectively, and the output ports 2 and 3 respectively. Is also connected. In addition, in order to supply the DC voltage, the gates of the FETs 6 and 11 are connected to the power supply 8 via the gate bias circuits 7 and 12, respectively, and the drains thereof are also connected to the drain bias circuits 13 and 14. It is connected to the power supply 8 via. The gate bias circuits 7 and 12 and the drain bias circuits 13 and 14 are composed of a circuit which does not pass the RF signal, for example, an inductor, a resistance element, a combination thereof, or the like.

The anodes of the diodes 17 and 18 are connected to the output ports 2 and 3 via the inductors 15 and 16, respectively. The cathode of the diode 17 and the cathode of the diode 18 are connected in common and are grounded via the resistance element 19. Here, the resistance of the resistance element 19 is set to be sufficiently large as compared with the ON resistance of the diodes 17 and 18. In addition, the resistance value of the resistance element 19 is the anode so that the diodes 17 and 18 are turned on when the FETs 6 and 11 are operated, that is, when a voltage of 5 V is supplied from the power supply 8, for example. It is assumed that the voltage is optimized to apply a voltage between the cathodes.

In Fig. 1, when the FETs 6 and 11 are in an operating state, that is, when a voltage of, for example, 5 V is supplied from the power supply 8, the operation is performed as follows. At this time, the diodes 17 and 18 are turned ON by the optimized resistance element 19.

The RF signal input from the output port 2 is branched into a signal passing through the feedback circuit 4 or the FET 6 and a signal passing through the inductor 15. The signal passing through the feedback circuit 4 or the FET 6 is input to the gate of the FET 11, amplified and output to the output port 3, and the phase is shifted 180 degrees at this time. On the other hand, when the values of the inductors 15 and 16 are small and the resistance of the resistance element 19 is sufficiently larger than the ON resistance of the diodes 17 and 18, the signal passing through the inductor 15 is not phase shifted. The diodes 17 and 18 pass through the inductor 16 and are output to the output port 3. Therefore, by optimizing the ON resistance of the diodes 17 and 18, in the output port 3, cancellation occurs between a signal whose phase is shifted 180 degrees and a signal without phase shift, and the output is performed. Since the signal from port 3 is attenuated, the isolation between ports 2 and 3 is improved. In addition, when the phase difference between two canceled signals does not become 180 degrees due to the influence of wiring and FET characteristics, the inductance of the inductors 15 and 16 is adjusted so that the phase difference becomes 180 degrees and is cancelled. In addition, the RF signal input from the port 3 is similarly canceled by the output port 2.

On the other hand, in Fig. 1, when the FETs 6 and 11 are in the OFF state, that is, when the power source 8 is 0V, for example, the operation is performed as follows. At this time, the diodes 17 and 18 are in an OFF state because no voltage is applied between the anode and the cathode.

Since the FET 6 and the diode 17 are in the OFF state, most of the RF signals input from the output port 2 are output from the output port 3 via the feedback circuits 4 and 9. In this case, since the feedback circuits 4 and 9 are generally high in resistance, the signal at the output port 3 is small and the isolation does not deteriorate. In addition, for the RF signal input from the output port 3, the signal is small at the port 2, and isolation is not deteriorated.

Fig. 2 is a diagram showing the isolation characteristics in the splitter circuit according to the first embodiment of the present invention. Curve A is a characteristic when the FET is in an operating state, and curve B is a characteristic when the FET is in an OFF state, and it shows that good isolation characteristics are maintained regardless of ON or OFF. That is, in the present embodiment, the resistance R3 between the output ports in the conventional splitter circuit is replaced with the diodes 17 and 18 which are turned OFF in accordance with the OFF state of the FET, thereby greatly improving the isolation characteristics at the OFF time. (Curve B in FIG. 10 vs. curve B in FIG. 2).

(Example 2)

3 is a circuit diagram of a splitter circuit according to a second embodiment of the present invention. In Fig. 3, the same reference numerals as those in Fig. 1 are represented by the same elements, and the description thereof is omitted. The resistive element 19a of FIG. 3 is the same as the resistive element 19 of FIG. 1, but differs from the first embodiment in that it is configured as an external component of the IC. 22 is a bonding wire for connecting the IC and the resistor 19a serving as an external component, and connects the cathodes of the diodes 17 and 18 and one end of the resistor 19a. The operation of the splitter circuit according to the second embodiment is the same as that of the first embodiment, and has the same effect.

In this embodiment, by using the resistance element 19a as an external component, adjustment of the resistance value of the resistance element 19a for changing the isolation characteristics between the output ports 2 and 3 can be easily adjusted externally. . In addition, by using a component having appropriate temperature characteristics as the resistance element 19a, it is possible to improve the temperature characteristics in the isolation characteristics between the output ports.

(Example 3)

4 is a circuit diagram of a splitter circuit according to a third embodiment of the present invention. 4, input ports IN, output ports OUT1 to OUTn, capacitors C1 to Cn, FET MN1 to MNn, source circuits SC1 to SCn, feedback circuits FC1 to FCn, gate bias circuits GC1 to GCn, drain bias circuits DC1 to DCn, the power supply VDD, the diodes D12 to Dnn-1, the inductors L12 to Lnn-1, and the resistance elements R12 to Rn-1n are the input ports 1, the output ports 2 and 3 of FIG. 10, FETs 6, 11 source circuits 20, 21, feedback circuits 4, 9, gate bias circuits 7, 12, drain bias circuits 13, 14, power supplies 8, diodes Corresponding to (17, 18), the inductors 15, 16, and the resistive elements 19, respectively, they operate similarly.

In the splitter circuit of FIG. 1, two amplification units having input terminals in common exist. On the other hand, in the splitter circuit of Fig. 4, n amplification sections having input terminals in common exist, and an impedance circuit is disposed between output terminals of the two amplification sections. These impedance circuits, like the first embodiment, cancel when a FET in the amplifier is in an operating state, between a signal whose phase is shifted by 180 degrees and a signal without phase shift, at the output port, The signal from the output port is attenuated. Thus, the isolation between the output terminals of the two amplifiers is improved. On the other hand, when the FETs in the two amplifier sections are in the OFF state, the impedance circuit becomes high impedance, and the isolation between the output terminals of the two amplifier sections does not deteriorate.

Fig. 5 is a diagram showing the isolation characteristics in the splitter circuit according to the third embodiment of the present invention. Curve A is a characteristic when the FET is in the operating state, and curve B is a characteristic when the FET is in the OFF state, and it shows that good isolation characteristics are maintained regardless of ON or OFF.

According to the splitter circuit according to the third embodiment, even if the configuration is three or more quarters, isolation between output terminals can be maintained similarly to the first embodiment. In addition, the resistance elements R12 to Rn-1n may be external components, and they may be connected by bonding wires in the same manner as in the second embodiment. In addition, when n = 2, it corresponds with FIG.

(Example 4)

6 is a circuit diagram of a splitter circuit according to a fourth embodiment of the present invention. In FIG. 6, the same code | symbol as FIG. 4 represents the same thing, and the description is abbreviate | omitted. The splitter circuit shown in FIG. 6 is replaced with diodes D12 to Dnn-1, inductors L12 to Lnn-1, resistors R12 to Rn-1n in FIG. 4, and includes diodes D1 to Dn, inductors L1 to Ln, and resistors R0. do.

A series circuit composed of an inductor Li and a diode Di is provided between the output port OUTi and one end of the resistor R0. One end of the resistor R0 is commonly connected to the cathodes of the diodes D1 to Dn, and the other end is grounded.

In the splitter circuit having such a configuration, there are n amplification parts having common input terminals, and between two amplification parts each having a portion of an impedance circuit (series of diodes and inductors) arranged at the output terminals of the n amplification parts. One impedance circuit is formed. In the impedance circuit, as in the first embodiment, when the FET in the amplifier is in an operating state, cancellation occurs between the signal whose phase is shifted by 180 degrees and the signal without phase shift in the output port. The signal from the output port is attenuated. Thus, the isolation between the output terminals of the two amplifiers is improved. On the other hand, when the FETs in the two amplifier sections are in the OFF state, the impedance circuit becomes high impedance, and the isolation between the output terminals of the two amplifier sections does not deteriorate.

Fig. 7 is a diagram showing isolation characteristics in the splitter circuit according to the fourth embodiment of the present invention. Curve A is a characteristic when the FET is in an operating state, and curve B is a characteristic when the FET is in an OFF state, and it shows that good isolation characteristics are maintained regardless of ON or OFF.

According to the splitter circuit according to the embodiment of FIG. 4, even in the case of three or more quarters, isolation between output terminals can be maintained similarly to the first embodiment. In addition, it is the same as that of 2nd Example that resistance element R0 may be made into an external component, and these may be made to ground with a bonding wire. In addition, when n = 2, it corresponds with FIG.

(Example 5)

8 is a circuit diagram of a splitter circuit according to a fifth embodiment of the present invention. In FIG. 8, the same code | symbol as FIG. 6 represents the same thing, and the description is abbreviate | omitted. The splitter circuit shown in FIG. 8 is a circuit in which diodes D2, D4-Dn, impedance L2, and L4-Ln of FIG. 6 are omitted. This splitter circuit has the same configuration as the splitter circuit according to the first embodiment with respect to the output ports OUT1 and OUT3.

If good isolation characteristics between all output ports are not required, and only isolation between output ports OUT1 and OUT3 is required, for example, inductors L1, L3 and diodes D1, D3 are connected to only output ports OUT1, OUT3. According to such a structure, a circuit can be simplified compared with Example 3, 4.

In addition, each indication, such as the above-mentioned patent document, shall be quoted in this book. Changes and adjustments of the embodiments to the examples are possible within the scope of the entire disclosure of the present invention (including the claims) and based on the basic technical idea. In addition, various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, of course, this invention includes the various deformation | transformation and correction which a person skilled in the art can make according to the prior indication and technical idea including the Claim of this invention.

1 is a circuit diagram of a splitter circuit according to a first embodiment of the present invention.

Fig. 2 is a diagram showing isolation characteristics in the splitter circuit according to the first embodiment of the present invention.

3 is a circuit diagram of a splitter circuit according to a second embodiment of the present invention.

4 is a circuit diagram of a splitter circuit according to a third embodiment of the present invention.

Fig. 5 is a diagram showing the isolation characteristics in the splitter circuit according to the third embodiment of the present invention.

6 is a circuit diagram of a splitter circuit according to a fourth embodiment of the present invention.

Fig. 7 is a diagram showing the isolation characteristics in the splitter circuit according to the fourth embodiment of the present invention.

8 is a circuit diagram of a splitter circuit according to a fifth embodiment of the present invention.

9 is a circuit diagram of a conventional splitter circuit.

10 is a diagram showing isolation characteristics in a conventional splitter circuit.

* Description of the symbols for the main parts of the drawings *

1: input port 2, 3: output port

4, 9: feedback circuit 5, 10: capacitive element

6, 11: FET 7, 12: gate bias circuit

8: power supply 13, 14: drain bias circuit

15, 16: inductor 17, 18: diode

19, 19a: resistor elements 20, 21: source circuit

22: bonding wire C1 ~ Cn: capacitor

C1 ~ Cn, D12 ~ Dnn-1: Diode DC1 ~ DCn: Drain bias circuit

FC1 to FCn: Feedback circuit GC1 to GCn: Gate bias circuit

IN: Input port L1 ~ Ln, L12 ~ Lnn-1: Inductor

MN1 ~ MNn: FET OUT1 ~ OUTn: Output port

R0, R12 to Rn-1n: Resistor elements SC1 to SCn: Source circuit

VDD: Power

Claims (11)

With input terminals, A first output terminal, A second output terminal, A first amplifier between the input terminal and the first output terminal, the first amplifier amplifying a signal of the input terminal and outputting the signal to the first output terminal; A second amplifier between the input terminal and the second output terminal, the second amplifier amplifying a signal of the input terminal and outputting the signal to the second output terminal; An impedance circuit connected between the first and second output terminals, The impedance circuit becomes a predetermined impedance when a first power supply is supplied to the first and second amplifiers, and is opened when the first power supply is not supplied to the first and second amplifiers. A splitter circuit, configured to be in a state. The method of claim 1, wherein the impedance circuit, A first series circuit comprising a first inductor and a first diode in series form connecting one end to said first output terminal, A second series circuit comprising a second inductor and a second diode in series form connecting one end to the second output terminal; A resistance element connected between the other end of said first and second series circuits and a second power source; And the first and second diodes are connected so that current flows in a forward direction when the voltages of the first power supply and the second power supply are different. The voltage of the first power supply is set higher than the voltage of the second power supply. The first diode connects an anode to the first output terminal via the first inductor, a cathode to one end of the resistance element, The second diode connects an anode to the second output terminal via the second inductor, and connects a cathode to one end of the resistance element, A splitter circuit, wherein the other end of the resistor is connected to the second power supply. With input terminals, An output terminal of the ith (an integer of i = 1 to n, n being an integer of 2 or more), An i-th amplifier between the input terminal and the i-th output terminal, for amplifying a signal of the input terminal and outputting it to an i-th output terminal; An impedance connected between the output terminals of j-th (an integer of j = 1 to n-1) and k (an integer of k = j + 1-n), The impedance circuit has a predetermined impedance when the first power is supplied to the j-th and k-th amplifiers, and the open state is maintained when the first power is not supplied to the j-th and kth amplifiers. The splitter circuit, characterized in that configured to. The method of claim 4, wherein the impedance circuit, A j-th series circuit comprising a j-th inductor and a j-th diode in series with one end connected to the j-th output terminal; A k-th series circuit comprising a k-th inductor and a k-th diode in series, connecting one end to said k-th output terminal, A resistance element connected between the second end of the j-th and k-th series circuits and a second power source; The j-th and k-th diodes are connected so that current flows in the forward direction when the voltages of the first power supply and the second power supply are different. The voltage of the first power supply is set higher than the voltage of the second power supply. The jth diode connects an anode to the jth output terminal via the jth inductor, and connects a cathode to one end of the resistance element. The k-th diode connects an anode to the k-th output terminal via the k-th inductor, and connects a cathode to one end of the resistance element, A splitter circuit, wherein the other end of the resistor is connected to the second power supply. With input terminals, An output terminal of the ith (an integer of i = 1 to n, n is an integer of 2 or more), An i-th amplifier between the input terminal and the i-th output terminal, for amplifying a signal of the input terminal and outputting it to an i-th output terminal; An impedance circuit connected to two or more output terminals of the first to nth output terminals, The impedance circuit has a predetermined impedance between two output terminals selected from the two or more output terminals when a first power source is supplied to an amplifier corresponding to the two or more output terminals, respectively. A splitter circuit, characterized in that the impedance at the two output terminals to be selected is in an open state when the power supply of 1 is not supplied. The method of claim 7, wherein the impedance circuit, Respective series circuits each comprising an inductor and a diode in series, respectively corresponding to the two or more output terminals and connecting one end thereof; A resistance element connected between the other end of each series circuit and a second power supply; And the diode is connected so that current flows in the forward direction when the voltages of the first power supply and the second power supply are different. The voltage of the first power supply is set higher than the voltage of the second power supply. Each said diode connects an anode to each of said at least two output terminals via said inductor, and connects a cathode to one end of said resistance element, A splitter circuit, wherein the other end of the resistive element is connected to the second power supply. The semiconductor device containing the splitter circuit of any one of Claims 1-9. Including a semiconductor device comprising the splitter circuit of any one of claims 2, 3, 5, 6, 8, 9 except for the resistance element, The resistance element is outside the semiconductor device, One end of the resistance element is connected to the other end of each series circuit of the semiconductor device via a bonding wire.

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