KR100994212B1 - Pulse-width modulation signal generator - Google Patents

Abstract

PURPOSE: A pulse-width modulation signal generator is provided to improve the resolution without increase bit number of data by using the phase difference between a first to a fourth clock signal. CONSTITUTION: A clock signal generator(110) generates a plurality of clock signals having different phases. An up counter(130) generates a first PWM signal in response to a first clock signal from clock signals. A multiplexer(160) selects one of a plurality of clock signals. A down-counter(170) generates a second PWM signal having delayed phased from the first PWM signal in response to the clock signal which is selected from the multiplexer.

Description

Pulse-Width Modulation Signal Generator {PULSE-WIDTH MODULATION SIGNAL GENERATOR}

TECHNICAL FIELD The present invention relates to signal generators, and more particularly to pulse-width modulation signal generators.

The power supply includes a DC power supply and an AC power supply. The DC power supply includes an AC-DC converter for converting AC power to DC power or a DC-DC converter for converting DC power to DC power.

DC-DC converter converts DC input voltage to DC output voltage by stepping up or down. First, the DC input voltage is converted into an AC voltage. In this case, the DC input voltage may be converted into an AC voltage by a full-bridge circuit inside the DC-DC converter. The converted AC voltage is boosted or reduced by a transformer and then converted back to a DC output voltage.

In general, a full-bridge circuit may consist of four power switches. Here, each power switch may be controlled by a pulse-width modulation signal. In particular, the power switch of a phase-shifted full-bridge DC-DC conveter can be controlled by adjusting the phase delay between pulse-width modulated signals. At this time, zero voltage switching (ZVS) of the phase-shift full-bridge DC-DC converter is performed, thereby reducing switching loss during the high frequency switching operation. Therefore, the efficiency of the phase shift full-bridge DC-DC converter can be increased. To do this, the phase delay between the pulse-width modulated signals must be precisely adjusted.

It is an object of the present invention to improve the resolution for phase delay between pulse-width modulated signals while maintaining the frequency of the generated clock signal and pulse-width modulation signal. A pulse-width modulation signal generator is provided.

Pulse-width modulated signal generator according to an embodiment of the present invention includes a clock signal generator for generating a plurality of clock signals; An up-counter configured to generate a first pulse-width modulated signal in response to a first clock signal of which the phase is most advanced among the plurality of clock signals; A multiplexer for selecting one of the plurality of clock signals; And a down-counter for generating a second pulse-width modulated signal having a delayed phase relative to the first pulse-width modulated signal in response to a clock signal selected by the multiplexer.

In example embodiments, the down-counter receives a first command signal from an external source and down-counts the data value transmitted by the first command signal from the first rising edge of the clock signal selected by the multiplexer. To start.

The pulse-width modulated signal generator according to an embodiment of the present invention may further include a comparator for generating a pulse signal whenever the up-counting value of the up-counter reaches a first reference value. At this time, the down-counter updates the data value every time the pulse signal is input.

The pulse-width modulated signal generator according to the embodiment of the present invention receives the first and second pulse-width modulated signals and inverts the first and second pulse-width modulated signals, respectively. Generating a width modulated signal and setting dead time between the first and third pulse-width modulated signals and between the second and fourth pulse-width modulated signals to output the first to fourth pulse-width modulated signals; It may further include a dead time generator.

At this time, the up-counter resets the up-counting value to a second reference value smaller than the first reference value when the up-counting value reaches the first reference value. The down-counter resets the down-counting value to the first reference value when the data value reaches the second reference value.

In addition, the up-counter is configured to reset the up-counting value and when the up-counting value reaches a third reference value that is less than the first reference value and greater than the second reference value, the first pulse- Change the voltage level of the width modulated signal. The down-counter then changes the voltage level of the second pulse-width modulated signal when resetting the down-counting value and when the down-counting value reaches the third reference value.

Here, the first reference value may be 2 ⁿ −1 (n is a natural number), and the second reference value may be 0. The third reference value may be an intermediate value between the first reference value and the second reference value.

In an embodiment, the multiplexer receives second to fourth clock signals having a phase delayed by 90 °, 180 °, and 270 ° from the clock signal generator, respectively, relative to the first clock signal and the first clock signal. One of the first to fourth clock signals may be selected.

The pulse-width modulated signal generator according to an embodiment of the present invention receives a second command signal from an external source and generates a first flip-flop in response to the second command signal and the fourth clock signal. ; And a second flip-flop configured to receive a third command signal from the outside and generate a second selection signal in response to the third command signal and the fourth clock signal. In this case, the multiplexer may select one of the first to fourth clock signals according to the first and second selection signals. The first and second flip-flops are activated by the pulse signal.

Pulse-width modulated signal generator according to an embodiment of the present invention includes a first delay circuit for delaying the first clock signal to the up-counter; And a second delay circuit for delaying the fourth clock signal and transferring the fourth clock signal to the first and second flip-flops.

According to the pulse-width modulation signal generator according to an embodiment of the present invention, the precision and stability of the control of a full-bridge DC-DC conveter using the same Can increase.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

1 is a block diagram illustrating a pulse-width modulated signal generator according to an exemplary embodiment of the present invention. Referring to FIG. 1, a pulse-width modulation signal generator 100 includes a clock signal generator 110, first and second delay circuits 121 and 122, Up-counter 130, comparator 140, first and second flip-flops 151, 152, multiplexer 160, down-counter , 170), and a dead-time generator (180).

The pulse-width signal generator 100 receives the first to third command signals CMD1 to CMD3 from an external controller 1200 (see FIG. 4 below). The first command signal CMD1 is provided to the down-counter 170 with an n-bit data value. The second and third command signals CMD2 and CMD3 are provided to the first and second flip-flops 151 and 152, respectively.

The clock signal generator 110 generates the first to fourth clock signals CLK1 to CLK4. Here, the first clock signal CLK1 corresponds to the reference clock signal. The second to fourth clock signals CLK2 to CLK4 have phases delayed by 90 °, 180 °, and 270 °, respectively, compared to the first clock signal CLK1. The clock signal generator 110 transmits the first clock signal CLK1 to the first delay circuit 121 and the fourth clock signal CLK4 to the second delay circuit 122. In addition, the clock signal generator 110 transmits the first to fourth clock signals CLK1 to CLK4 to the multiplexer 160.

The first delay circuit 121 generates a predetermined time delay with respect to the first clock signal CLK1. The first clock signal CLK1 delayed by the first delay circuit 121 is provided to the up-counter 150.

The second delay circuit 122 generates a constant time delay with respect to the fourth clock signal CLK4. The fourth clock signal CLK4 timed by the second delay circuit 122 is provided to the first and second flip-flops 151 and 152.

The first to fourth clock signals CLK1 to CLK4 may have time delays due to transmission path differences. The first and second delay circuits 121 and 122 generate additional time delays for the first and fourth clock signals CLK1 and CLK4 to compensate for this time delay.

The up-counter 130 up-counts in response to the first clock signal passing through the first delay circuit 121. At this time, the up-counter 130 up-counts from the minimum counting value to the maximum counting value. The up-counter 130 resets the up-counting value to the minimum counting value as soon as the up-counting value reaches the maximum counting value.

For example, assuming n bits of up-counter 130 (where n is an integer greater than or equal to 1), the minimum counting value will be 0 and the maximum counting value will be 2 ⁿ -1. Thus, up-counter 130 up-counts from 0 to 2 ⁿ −1. The up-counter 130 resets the up-counting value to zero at the moment the up-counting value reaches 2 ⁿ −1.

For reference, the maximum and minimum counting values are predetermined values. However, it is obvious to those who have acquired common knowledge in this field that the value can be changed.

The up-counter 130 periodically generates the first pulse-width modulated signal PWM1 while repeating up-counting and reset. The generation of the first pulse-width modulated signal PWM1 by the up-counter 130 will be described in more detail in FIG. 2 below.

Comparator 140 senses an up-counting value of up-counter 130. At this time, the comparator 130 generates a pulse signal PS at the time when the up-counting value reaches the maximum counting value. The pulse signal PS is provided to the first and second flip-flops 151 and 152 and the down-counter 170, respectively.

The first flip-flop 151 is activated by the pulse signal PS. The activated first flip-flop 151 generates the first selection signal SEL1 in response to the fourth clock signal CLK4 and the second command signal CMD2 that have passed through the second delay circuit 122. Here, the logic level of the first selection signal SEL1 is determined according to the second command signal CMD2.

The second flip-flop 152 is activated by the pulse signal PS. The activated second flip-flop 152 generates the second selection signal SEL2 in response to the fourth clock signal CLK4 and the third command signal CMD3 that have passed through the second delay circuit 122. Here, the logic level of the second selection signal SEL2 is determined according to the third command signal CMD3.

The multiplexer 160 selects one of the first to fourth clock signals CLK1 to CLK4 in response to the first and second selection signals SEL1 and SEL2. For example, if (SEL1, SEL2) = (0, 0), the first clock signal CLK1 will be selected. If (SEL1, SEL2) = (0, 1), the second clock signal CLK2 will be selected. If (SEL1, SEL2) = (1, 0), the third clock signal CLK3 will be selected. If (SEL1, SEL2) = (1, 1), the fourth clock signal CLK4 will be selected.

The down-counter 170 down-counts in response to the clock signal selected by the multiplexer 160. At this time, the down-counter 170 down-counts from the maximum counting value to the minimum counting value. Here, the maximum and minimum counting values of the down-counter 170 are set equal to the maximum and minimum counting values of the up-counter 130. Thus, down-counter 170 down-counts from 2 ⁿ −1 to 0.

The down-counter 170 loads n-bit data values transmitted by the first command signal when the pulse signal PS generated by the comparator 140 is input during down-counting. At this time, the down-counter 170 updates the down-counting value with an n-bit data value. Therefore, from this point on, n-bit data values are down-counted. The down-counter 170 resets the down-counting value to the maximum counting value as soon as the down-counting value reaches the minimum counting value.

The down-counter 170 periodically generates the second pulse-width modulated signal PWM2 while repeating down-counting and reset. The generation of the second pulse-width modulated signal PWM2 by the down-counter 170 will be described in more detail in FIG. 2 below. In this case, the second pulse-width modulated signal PWM2 has a delayed phase compared to the first pulse-width modulated signal PWM1. This will be explained in more detail in FIGS. 2 and 3 below.

The dead time generator 180 receives the first and second pulse-width modulation signals PWM1 and PWM2 and inverts the first and second pulse-width modulation signals PWM1 and PWM2, respectively. Generate the width modulated signals PWM3 and PWM4.

The dead time generator 180 sets a dead time between the first and third pulse-width modulated signals PWM1 and PWM3. Therefore, it is possible to prevent the voltages of the first and third pulse-width modulated signals PWM1 and PWM3 from going to a high level at the same time.

The dead time generator 180 also sets a dead time between the second and fourth pulse-width modulated signals PWM2 and PWM4. Therefore, it is possible to prevent the voltages of the second and fourth pulse-width modulated signals PWM2 and PWM4 from going to a high level at the same time.

As described above, the pulse-width modulated signal generator 100 according to the embodiment of the present invention generates the first to fourth pulse-width modulated signals PWM1 to PWM4. The first to fourth pulse-width modulated signals PWM1 to PWM4 may be used as control signals of the power supply. In particular, the pulse-width modulated signal generator 100 can be used to control a phase-shifted full-bridge DC-DC converter. This will be explained in more detail in FIGS. 4 and 5 below.

Here, the first and third pulse-width modulation signals PWM1 and PWM3 are leading signals, and the second and fourth pulse-width modulation signals PWM2 and PWM4 are lagging signals. The resolution of the phase delay between the fastening signals PWM1 and PWM3 and the ground signals PWM1 and PWM4 affects the precision and stability of the control of the phase shifting full-bridge DC-DC converter.

Here, the resolution means the degree to which the phase delay between the fastening signals PWM1 and PWM3 and the ground signals PWM2 and PWM4 changes. Thus, increasing resolution may result in more precise phase delay. The resolution may be expressed as the number of bits (n bits) counted by the up-counter 130 and the down-counter 170.

Equation 1 below shows the relationship between the frequency (f _S ), the clock signal frequency (f _C ), and the resolution (n bit) of the pulse-width modulated signal generated by the up-counter 130 and the down-counter 170. Explain. Referring to Equation 1, in order to increase the frequency f _S of the pulse-width modulated signal, it is necessary to increase the clock signal frequency f _C or reduce the resolution (n bits).

According to the pulse-width modulated signal generator 100 according to an embodiment of the present invention, even if the resolution is increased by two bits without increasing the clock signal frequency f _C , the frequency f _S of the pulse-width modulated signal can be maintained. have. This will be explained in more detail in FIGS. 2 and 3 below.

FIG. 2 is a timing diagram for a pulse-width modulated signal generated in the pulse-width modulated signal generator of FIG. 1. Referring to FIG. 2, the first pulse-width modulated signal PWM1 is changed from a low level to a high level as soon as the up-counting value is reset from the maximum counting value to the minimum counting value. Then, during the up-counting, the first pulse-width modulated signal PWM1 is changed from the high level to the low level as soon as the up-counting value reaches the middle value of the maximum counting value. This is exemplary and the voltage level of the first pulse-width modulated signal PWM1 may be changed as soon as an arbitrary value between the maximum count value and the minimum count value is reached. That is, any value between the maximum count value and the minimum count value determines the duty ratio of the first pulse-width modulated signal PWM1. However, the pulse-width modulated signal generator according to the embodiment of the present invention uses a duty ratio of 50%. And, a pulse-width modulated signal having a duty ratio of 50% has the same waveform as the waveform corresponding to the most significant bit of the n-bit up-counter.

The first pulse-width modulated signal PWM1 is periodically generated by repeating up-counting and reset. Here, as the maximum counting value increases, the period Ts of the first pulse-width modulated signal PWM1 also increases. This maximum counting value is determined by the resolution. In other words, as the resolution increases, the maximum value that can be counted up also increases.

The third pulse-width modulated signal PWM3 is generated by inverting the first pulse-width modulated signal PWM1 by the dead time generator 180 (see FIG. 1). However, a dead time is set between the first and third pulse-width modulated signals PWM1 and PWM3. This is to prevent the voltages of the first and third pulse-width modulated signals PWM1 and PWM3 from going to a high level at the same time.

As described with reference to FIG. 1, the pulse signal PS is input to the down-counter 170 (see FIG. 1) when the up-counting value is reset. In this case, the down-counting value is updated to n-bit data value DATA transmitted by the first command signal CMD1. Thereafter, the n-bit data value DATA is down-counted.

As soon as the down-counting value is reset from the maximum counting value to the minimum counting value, the second pulse-width modulated signal PWM2 is changed from the low level to the high level. As a result, the second pulse-width modulated signal PWM2 is delayed as long as the n-bit data value DATA is down-counted. That is, the phase delay between the first and second pulse-width modulated signals PWM1 and PWM2 will vary according to the n-bit data value DATA.

Thereafter, during the down-counting, the second pulse-width modulated signal PWM2 is changed from the high level to the low level as soon as the down-counting value reaches the middle value of the maximum counting value.

This is exemplary and the voltage level of the second pulse-width modulated signal PWM2 may be changed at the moment it reaches any value between the maximum count value and the minimum count value. That is, any value between the maximum count value and the minimum count value determines the duty ratio of the second pulse-width modulated signal PWM2. However, the pulse-width modulated signal generator according to the embodiment of the present invention uses a duty ratio of 50%. And, a pulse-width modulated signal having a duty ratio of 50% has the same waveform as the waveform corresponding to the most significant bit of the n-bit down-counter.

The second pulse-width modulated signal PWM2 is periodically generated by repeating the down-counting, reset and update of the down-counting value with n-bit data value DATA. The second pulse-width modulated signal PWM2 is generated to have the same period TS as the first pulse-width modulated signal PWM1 by the pulse signal PS. However, as described above, the second pulse-width modulated signal PWM2 has a phase delayed as much as n-bit data value DATA is down-counted compared to the first pulse-width modulated signal PWM1.

The fourth pulse-width modulated signal PWM4 is generated by inverting the second pulse-width modulated signal PWM1 by the dead time generator 180 (see FIG. 1). However, a dead time is set between the second and fourth pulse-width modulated signals PWM2 and PWM4. This is to prevent the voltages of the second and fourth pulse-width modulated signals PWM2 and PWM4 from going to a high level at the same time.

The number of bits (n bits) of the data value DATA refers to the resolution of the phase delay between the advance signals PWM1 and PWM3 and the ground signals PWM2 and PWM4. As the resolution increases, the period Ts of the first to fourth pulse-width modulated signals PWM1 to PWM4 increases. This means that the frequencies of the first to fourth pulse-width modulated signals PWM1 to PWM4 are decreased.

The pulse-width modulated signal generator 100 according to the embodiment of the present invention maintains the frequency of the clock signal and increases the resolution by 2 bits without reducing the frequencies of the first to fourth pulse-width modulated signals PWM1 to PWM4. You can. This will be explained in more detail in FIG. 3 below.

3 is a timing diagram illustrating a method of increasing the resolution by 2 bits by the pulse-width modulated signal generator of FIG. 1. Referring to FIG. 3, the first clock signal CLK1 corresponds to a reference clock signal. The second to fourth clock signals CLK2 to CLK4 have phases delayed by 90 °, 180 °, and 270 °, respectively, compared to the first clock signal CLK1.

The up-counting value increases by one step for each rising edge of the first clock signal CLK1. The down-counting value decreases by one step for each rising edge of the selected one of the first to fourth clock signals CLK1 to CLK4.

Assume that the starting point at which the up-counting value is reset is the first starting point S1. At the first start point S1, the first pulse-width modulated signal PWM1 is changed from a low level to a high level.

It is assumed that a time point at which the first rising edge of the second clock signal CLK2 occurs after the first start point S1 is the second start point S2. It is assumed that a time point at which the first rising edge of the third clock signal CLK3 occurs after the first start point S1 is the third start point S3. It is assumed that a time point at which the first rising edge of the fourth clock signal CLK4 occurs after the first start point S1 is a fourth start point S4.

One of the first to fourth clock signals CLK1 to CLK4 is selected by the multiplexer 140 (see FIG. 1) and transferred to the down-counter 170 (see FIG. 1). One of the first to fourth clock signals CLK1 to CLK4 should be selected within a quarter time Tx of the clock signal period before the up-counting value is reset.

At this time, when the first clock signal CLK1 is selected, the n-bit data value DATA is down-counted from the first start point S1. When the second clock signal CLK2 is selected, the n-bit data value DATA is down-counted from the second start point S2. When the third clock signal CLK3 is selected, the n-bit data value DATA is down-counted from the third start point S3. When the fourth clock signal CLK4 is selected, the n-bit data value DATA is down-counted from the first start point S4.

Accordingly, by selecting the first to fourth clock signals CLK1 to CLK4, the n-bit data value DATA may be down-counted every quarter time Tx of the clock signal period. That is, the number of down-counting for the same n-bit data value DATA increases by four times as compared to the case of down-counting every clock signal period. After all, this means that the data resolution DATA of the bit increased by two bits more than n bits per clock signal period has the same resolution as that of down-counting.

In summary, according to the pulse-width modulated signal generator 100 according to the embodiment of the present invention, the number of bits of the data value DATA is increased by using a phase difference between the first to fourth clock signals CLK1 to CLK4. You can achieve the same effect by increasing the resolution by 2 bits without turning it on.

4 is a circuit diagram illustrating a power supply using the pulse-width modulated signal generator of FIG. 1. Referring to FIG. 4, the power supply device 1000 includes a pulse-width modulated signal generator 1100, a control device 1200, and a full-bridge DC-DC converter 1300.

The pulse-width modulated signal generator 1100 has already been described in FIG. 1. Therefore, description thereof is omitted.

The controller 1200 generates the first to third command signals CMD1 to CMD3 according to the output of the full-bridge DC-DC converter 1300. The first to third command signals CMD1 to CMD3 are transmitted to the pulse-width modulated signal generator 1100. The first to third command signals CMD1 to CMD3 have already been described with reference to FIG. 1. Therefore, description thereof is omitted.

The full-bridge DC-DC converter 1300 includes first to fourth switches Q1 to Q4, first to eighth diodes D1 to D8, a transformer T, an LC filter 1310, and a load resistor R. _L )

The first to fourth switches Q1 to Q4 and the first to fourth diodes D1 to D4 form a full-bridge circuit for converting the DC input voltage V _IN into an AC voltage. The first to fourth switches Q1 to Q4 may be configured as MOSFETs. In this case, the first to fourth pulse-width modulated signals PWM1 to PWMM4 provided by the pulse-width modulated signal generator 1100 control the first to fourth switches Q1 to Q4, respectively.

The first to fourth diodes D1 to D4 are connected in parallel with the first to fourth switches Q1 to Q4 in opposite directions. That is, the anodes of the first to fourth diodes D1 to D4 are connected to the sources of the first to fourth switches Q1 to Q4. The cathodes of the first to fourth diodes D1 to D4 are connected to the drains of the first to fourth switches Q1 to Q4.

When the first to fourth switches Q1 to Q4 are turned off, the parasitic capacitors (not shown) of the first to fourth switches Q1 to Q4 are stored in the leakage inductor (not shown) of the transformer T. Is filled by. When each parasitic capacitor is charged to a predetermined voltage, a forward bias voltage is provided to the first to fourth diodes D1 to D4. Therefore, the source and the drain of the first to fourth switches Q1 to Q4 are connected to each other by the first to fourth diodes D1 to D4. At this time, as the first to fourth switches Q1 to Q4 are turned on, the full-bridge DC-DC converter 1300 performs zero voltage switching (ZVS).

The transformer T changes the AC voltage on the primary side to an AC voltage on the secondary side. At this time, the AC voltage of the secondary side will be boosted or reduced compared to the AC voltage of the primary side.

The fifth to eighth diodes D5 to D8 constitute a bridge rectifier for rectifying the AC voltage on the secondary side. In addition, the LC filter 1310 smoothes the output voltage V _R of the bridge rectifier. Therefore, the DC output voltage V _OUT appears between the load resistors R _L.

The controller 1200 generates the first to third command signals CMD1 to CMD3 so that the full-bridge DC-DC converter 1300 performs zero voltage switching. The pulse-width modulated signal generator 1100 generates the first to fourth pulse-width modulated signals PWM1 to PWM1 in response to the first to third command signals CMD1 to CMD3.

As described above, the first and third pulse-width modulated signals PWM1 and PWM1 correspond to fastening signals. On the other hand, the second and fourth pulse-width modulated signals PWM1 and PWM1 correspond to ground signals.

In order for zero voltage switching of the full-bridge DC-DC converter 1300 to occur, the phase delay between the phase signals PWM1 and PWM1 and the ground signals PWM1 and PWM1 must be adjusted. The phase delay between the advance signals PWM1 and PWM1 and the ground signals PWM1 and PWM1 may be controlled by the first to third command signals CMD1 to CMD3. Here, the degree of change in the phase delay between the advance signals PWM1 and PWM1 and the ground signals PWM1 and PWM1 is related to the precision and stability of the control of the full-bridge DC-DC converter 1300. And this is determined by the resolution.

According to the pulse-width modulated signal generator 1100 according to an embodiment of the present invention, the frequencies of the first to fourth clock signals CLK1 to CLK4 and the first to fourth pulse-width modulated signals PWM1 to PWM4 are maintained. The same effect can be achieved with a 2-bit increase in resolution. Therefore, the full-bridge DC-DC converter 1300 can be more precisely controlled without reducing the switching frequencies of the first to fourth switches Q1 to Q4.

FIG. 5 is a timing diagram for describing a switching operation of the full-bridge DC-DC converter of FIG. 4. Referring to FIG. 5, the first to fourth switches Q1 to Q4 (see FIG. 4) are turned on / off at regular intervals Ts by the first to fourth pulse-width modulation signals PWM1 to PWM4. Switching). At this time, the duty ratio of the output voltage V _R of the bridge rectifier is determined by the phase delay between the advance signals PWM1 and PWM3 and the ground signals PWM2 and PWM4. The frequency of the output voltage V _R of the bridge rectifier is twice the switching frequency of the first to fourth switches Q1 to Q4 (see FIG. 4).

It will be apparent to those skilled in the art that the structure of the present invention can be variously modified or changed without departing from the scope or spirit of the present invention. In view of the foregoing, it is intended that the present invention cover the modifications and variations of this invention provided they fall within the scope of the following claims and equivalents.

1 is a block diagram illustrating a pulse-width modulated signal generator according to an exemplary embodiment of the present invention.

FIG. 2 is a timing diagram for a pulse-width modulated signal generated in the pulse-width modulated signal generator of FIG. 1.

3 is a timing diagram illustrating a method of increasing the resolution by 2 bits by the pulse-width modulated signal generator of FIG. 1.

4 is a circuit diagram illustrating a power supply using the pulse-width modulated signal generator of FIG. 1.

FIG. 5 is a timing diagram for describing a switching operation of the full-bridge DC-DC converter of FIG. 4.

Claims (12)

A clock signal generator for generating a plurality of clock signals having different phases; An up-counter configured to generate a first pulse-width modulated signal in response to a first clock signal of which the phase is most advanced among the plurality of clock signals; A multiplexer for selecting one of the plurality of clock signals; And And a down-counter for generating a second pulse-width modulated signal having a delayed phase relative to the first pulse-width modulated signal in response to a clock signal selected by the multiplexer. The method of claim 1, The down-counter receives a first command signal from the outside and starts to count down the data value transmitted by the first command signal when the first rising edge of the clock signal selected by the multiplexer occurs. Width modulated signal generator. The method of claim 2, And a comparator for generating a pulse signal whenever the up-counting value of the up-counter reaches a first reference value. And the down-counter updates the data value each time the pulse signal is input. The method of claim 3, wherein Receiving the first and second pulse-width modulated signals and generating third and fourth pulse-width modulated signals inverting the first and second pulse-width modulated signals, respectively, and generating the first and third pulses. And a dead time generator for setting the dead time between the width modulated signal and the second and fourth pulse width modulated signals to output the first to fourth pulse width modulated signals. . The method of claim 4, wherein The up-counter resets the up-counting value to a second reference value that is less than the first reference value when the up-counting value reaches the first reference value, The down-counter resets the down-counting value to the first reference value when the data value reaches the second reference value. The method of claim 5, The up-counter modulates the first pulse-width modulation when resetting the up-counting value and when the up-counting value reaches a third reference value that is less than the first reference value and greater than the second reference value. Change the voltage level of the signal, The down-counter changes the voltage level of the second pulse-width modulated signal when the down-counting value is reset and when the down-counting value reaches the third reference value. . The method of claim 6, Wherein the first reference value is 2 ⁿ −1 (n is a natural number) and the second reference value is zero. The method of claim 7, wherein And the third reference value is an intermediate value between the first reference value and the second reference value. The method of claim 4, wherein The multiplexer receives second to fourth clock signals having a phase delayed by 90 °, 180 °, and 270 ° from the first clock signal and the first clock signal, respectively, from the clock signal generator. And a pulse-width modulated signal generator for selecting one of the fourth clock signals. The method of claim 9, A first flip-flop that receives a second command signal from an external source and generates a first selection signal in response to the second command signal and the fourth clock signal; And A second flip-flop that receives a third command signal from the outside and generates a second selection signal in response to the third command signal and the fourth clock signal, And the multiplexer selects one of the first to fourth clock signals in accordance with first and second selection signals. The method of claim 10, And the first and second flip-flops are activated by the pulse signal. The method of claim 10, A first delay circuit for delaying the first clock signal and delivering it to the up-counter; And And a second delay circuit for delaying said fourth clock signal and delivering it to said first and second flip-flops.

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