KR100992834B1 - Manufacturing method for nanowire multichannel FET devices - Google Patents

Abstract

The present invention relates to a method for manufacturing a nanowire multichannel field effect transistor device, and more particularly, to the current carrying capacity in the FET device using a conventional nanostructure material (nanotube, nanowire), and chemical sensors and biosensors using the same. A method of manufacturing a nanowire multichannel field effect transistor device capable of improving overcharge (electron or hole) mobility.

To this end, the present invention comprises the steps of preparing a nanowire array through a laser interference lithography process; Self-assembling nanomaterials through a solution process on the nanowire array; And manufacturing a multi-channel field effect transistor device using the nanowire array in which the nanomaterials are self-assembled.

Carbon nanotube, multichannel, nanowire array, laser interference lithography, solution process

Description

Manufacturing method for nanowire multichannel FET devices

The present invention relates to a method for manufacturing a nanowire multichannel field effect transistor device, and more particularly, to the current carrying capacity in the FET device using a conventional nanostructure material (nanotube, nanowire), and chemical sensors and biosensors using the same. A method of manufacturing a nanowire multichannel field effect transistor device capable of improving overcharge (electron or hole) mobility.

Electronic devices based on one-dimensional semiconductor materials capable of solution processing and their arrays are of great interest for applications requiring low cost manufacturing, large area coverage, and low temperature processing on flexible substrates. It raises [document 1].

Semiconductor single-wall carbon nanotubes (SWNTs) are expected to be utilized to manufacture high-performance thin-film transistors (TFTs).

The reason is that SWNTs have potentially high charge mobility and large current carrying capacity [2]. However, because the current carrying capacity is limited in individual SWNTs, the random network or parallel array of SWNTs can give the device the required current density.

The performance of CNT (carbon nanotube) TFTs can be improved by increasing the surface density and evenly aligning the CNTs. Many approaches have been studied to align CNTs using solution-based techniques [3]. Most applications, however, have limited applicability because of the low surface density of the formed CNT arrays.

While other solution based approaches have been attempted to make very dense CNTs, the result is that the CNT layers are arranged in an arbitrary direction [4]. Although inherent high charge mobility is limited due to the contact resistance between nanotubes in many overlapping nanotubes, very dense and oriented CNTs have recently been used as efficient semiconductors for TFTs [5].

Recently, an assembly pattern of nanomaterials with a line width of 3-4 μm has been reported using photolithography and self-assembly of carbon nanotubes to make large-scale patterns of aligned nanostructures (nanotubes and nanowires). 6]. However, since the carbon nanotubes used in the solution process are several nm in diameter and 1-2 μm in length, it is practically impossible to manufacture a pattern arranged in a single nanotube.

Thus, in order to achieve greater current carrying capability than single channel FET devices and greater charge mobility than random network FET devices, the line width at which nanomaterials are assembled must be smaller than submicrons.

As scientific exploration and engineering applications explore nanometer sizes, there is an increasing need to create nanostructures that not only have good regularity but also can be well controlled in pattern, size and shape.

In many applications, nanostructures are not useful unless they occupy a fairly large area and manufacturing costs are not within an acceptable range. Although the line width of the photomask for photolithography can be up to 500 nm, it is not easy to manufacture an array having a line width of 500 nm in large areas, and there is a disadvantage in that the manufacturing cost of the photomask of the submicron line width is expensive. In addition, arrays with line widths below 500 nm cannot be made.

Another method of making a sub-micron pattern is electron-beam lithography (EBL), which is a slow and expensive process because of the serial method. Also typically only small areas of less than 1 mm 2 can be produced.

Parallel x-ray lithography, on the other hand, can produce large area patterns but is too expensive.

In recent years, much research has focused on nanoimprinting, which replicates patterns in a parallel fashion, but the disadvantage is that the master mold is made by electron beam or x-ray lithography.

Currently, laser interference lithography is considered to be the most effective way to create periodic patterns of submicron size over a large area while controlling the regularity of the pattern well [Ref. 7]. It uses simple, fairly inexpensive optics to create regular interference patterns, such as lines or dots, on a substrate without any photomasks.

Interference lithography thus provides a technique for creating intrinsically infinite depth-of-field, large area, submicrometer patterns. Because of the periodic nature of interference lithography, many useful patterns and structures have been fabricated, such as optical diffraction gratings [8] and field emmiter arrays [9].

However, there has not yet been provided a means for producing nanowire arrays using interference lithography and manufacturing nanowire arrays in which one nanomaterial is aligned in the width direction of the nanowires by adjusting the line widths of the unit nanowires constituting the nanowire arrays. .

Furthermore, by fabricating a multichannel FET device using the nanowire array, no means has been provided to overcome the existing problems of low current carrying capacity and low charge mobility.

In particular, FET devices using nanostructured materials (nanotubes, nanowires) that have been developed to satisfy intellectual curiosity at the laboratory level, and problems of chemical sensors and biosensors using the same are as follows.

First, a single channel FET device manufactured using SWNT or nanowire having only one channel connecting a source-drain electrode has a disadvantage of low current carrying capacity while high charge mobility.

Second, the FET device using the proposed random network as a channel to improve the low current carrying capacity has a disadvantage in that the charge mobility is much lower than that of the single channel FET, and the current carrying ability is not significantly improved.

Third, the FET device using a single pattern with a line width of 3-4 μm as a channel using photolithography and solution process reduced the channel width by about 1/10 than the random network FET (channel width = 35 μm) device. Many nanomaterials are distributed randomly in the channel.

Therefore, there is an advantage that the large area can be manufactured using the semiconductor process, but there is a disadvantage that the improvement of the charge mobility and the current density is insufficient.

D. B. Mitzi, “Solution-processed inorganic semiconductors,” J. Mater. Chem., Vol. 14, p. 2355 (2004).

[2] T. Durkop, S. A. Getty, E. Cobas, and M. S. Fuhrer, "Extraordinary Mobility in Semiconducting Carbon Nanotubes," Nano Lett., Vol. 4, p. 35 (2004).

RS Mclean, X. Huang, C. Khripin, A. Jagota, and M. Zheng, "Controlled Two-Dimensional Pattern of Spontaneously Aligned Carbon Nanotubes," Nano Lett., Vol. 6, p.55 (2006 ).

Document 4 J.-U. Park, M. A. Meitl, S.-H. Hur, M. L. Usrey, M. S. Strano, P. J. A. Kenis, J. A. Rogers, "In Situ Deposition and Patterning of Single-Walled Carbon Nanotubes by Laminar Flow and Controlled Flocculation in Microfluidic Channels," Angew. Chem., Int. Ed., Vol. 45, p. 581 (2006).

[5] E. S. Snow, J. P. Novak, P. M. Campbell, and D. Park, "Random networks of carbon nanotubes as an electronic material," Appl. Phys. Lett., Vol. 82, p. 2145 (2003).

[Reference 6] M. Lee, J. Im, B. Y. Lee, S. Myung, J. Kang, L. Huang, Y.-K. Kwon & S. Hong, “Linker-free directed assembly of high-performance integrated devices based on nanotubes and nanowires” Nanotechnology, Vol. 1, p.66 (2006).

[7] B. H. Sohn, X. M. Yang, and P. Nealey, “Exposure of 38 nm period grating patterns with extreme ultraviolet interferometric lithography,” Appl. Phys. Lett., Vol. 75, p. 2328 (1999).

8 Salem H. Zaidi, An-Shyang Chu, and S. R. J. Brueck, “Optical properties of nanoscale, one-dimensional silicon grating structures,” J. Appl. Phys., Vol. 80, p. 6997 (1996).

9. X. Chen, S. H. Zaidi, S. R. J. Brueck, and D. J. Devine “Interferometric lithography of sub-micrometer sparse hole arrays for field-emission display applications,” J. Vacuum Sci. & Techno. B, Vol. 14, p. 3339 (1996).

The present invention has been made in view of the above, by using a laser interference lithography to create a nanowire array having a periodic pattern of submicron size in the width direction of the channel, and nanomaterials using a solution process method It is an object of the present invention to provide a method for manufacturing a large area / low cost nanowire multichannel field effect transistor device which can improve current carrying capacity and charge mobility by aligning one per unit channel in a line array.

The above object is a method for manufacturing a nanowire multichannel field effect transistor device,

Preparing a nanowire array through a laser interference lithography process; Self-assembling nanomaterials through a solution process on the nanowire array; And manufacturing a multi-channel field effect transistor device using the nanowire array in which the nanomaterial is self-assembled.

The laser interference lithography process comprises the steps of expanding and spatially filtering a laser beam through a pinhole such that the laser beam is coherent; The coherent laser beam being parallel light by a collimator; The coherent laser beam is aligned toward a rod mirror and a sample holder perpendicular to each other; And the aligned coherent laser beam forms a periodic line pattern of interference light intensity on the photoresist coated substrate.

로 만들기 위해 포토레지스트의 양보다 상대적으로 많은 양의 시너(Thinner)를 혼합하여 기판 위에 스핀 코팅하는 것을 특징으로 한다.In addition, the thickness of the photoresist thin film in the step of manufacturing a nanowire array through the laser interference lithography process 500 ~ 1000

It is characterized in that the spin coating on the substrate by mixing a relatively larger amount of thinner (Thinner) than the amount of photoresist to make.

Preferably, the laser light output exposed in the step of manufacturing the nanowire array through the laser interference lithography process is characterized in that less than 0.2mW.

In particular, when the nanowire array is manufactured with a light output of 0.2 mW or less through the laser interference lithography process, the exposure time is constantly adjusted so that the line width with the photoresist and the line width without the photoresist are at a constant ratio.

에 의해 시료홀더의 회전각(δ)에 따라 나노선 배열의 주기(d)를 조절하고, 상기 λ는 레이저 빔의 파장이다.In addition, in the step of manufacturing a nanowire array by the laser interference lithography process

The period d of the nanowire array is adjusted according to the rotation angle δ of the sample holder, and λ is the wavelength of the laser beam.

Here, the substrate on which the nanowire array of the photoresist pattern is manufactured is made of any one material selected from semiconductor, glass, oxide thin film, dielectric thin film and metal thin film.

The nanowire array of the photoresist pattern is etched on the substrate using the photoresist pattern as an etching mask.

Self-assembling nanomaterials to the nanowire array through the solution process is the step of depositing OTS in the region without the photoresist in the sample having a nanowire array made of laser interference lithography; Removing the photoresist remaining in the sample; And aligning the nanomaterial without functional groups in the region where the photoresist is removed.

In addition, the step of self-assembling the nanomaterial to the nanowire array through the solution process is the step of depositing OTS in the photoresist-free region in the sample having the nanowire array made of the laser interference lithography; Removing the photoresist remaining in the sample; Depositing APTES in the region where the photoresist has been removed; And aligning a nanomaterial having a negative functional group on the APTES pattern.

According to another embodiment of the present invention, the step of assembling the nanomaterial to the nanowire array through the solution process includes assembling the nanomaterial to the etched nanowire array using a photoresist as an etching mask on the substrate.

Preferably, manufacturing a nanowire array by adjusting the width of the nanowire so that only one nanomaterial per unit channel; And aligning the nanomaterial to the prepared nanowire array.

In addition, the step of manufacturing a multi-channel field effect transistor device using the nanowire array is a self-assembled nanomaterial is a source and a photolithography on the nanowire array arranged one nanomaterial per unit channel in the width direction Forming a drain electrode pattern; After depositing Ti / Au on the electrode pattern, manufacturing a drain electrode and a source electrode by a lift-off method.

Accordingly, according to the method of manufacturing a nanowire multichannel field effect transistor device according to the present invention, a nanowire having a line width of submicron size is linearly arranged in a width direction of a channel using a laser interference lithography method, and a solution processing method. By self-assembling nanomaterials into the nanowire array using, it is possible to improve current carrying capacity and charge mobility at a large area / low cost.

In particular, by controlling the number of nano-channels, the current size of the source-drain can be arbitrarily adjusted, eliminating the need for a current amplifier in an external circuit, requiring high speed and high output, and requiring electronic devices, logic devices, chemical sensors, and biosensors based on them. The array device can be implemented.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention provides a step of fabricating a nanowire array (diffraction grating) by a laser interference method in order to produce a linear array of nanowire width in a large area and low cost, and the step of self-assembling nanomaterial to the fabricated diffraction grating The present invention provides a method for manufacturing a multichannel field effect transistor device having a large area nanowire array using the same.

The present invention uses a simple Lloyds mirror device for laser interference lithography process [10]. 1 is a device structural diagram of a laser interference lithography system.

A He-Cd laser beam operating at a wavelength of 325 nm is extended and spatially filtered through the pinhole to become coherent. The incoherent beam is aligned toward the Lloyd's mirror 13 and the sample holder 15 whose plane angle is 90 ° after being collimated by the collimator 18.

The aligned coherent beam engraves a periodic line pattern of interference light intensity on a photoresist (PR) coated substrate 23. At this time, when λ is a wavelength and δ is an angle where the Lloyd mirror 13 forms a horizontal line (rotation angle of the sample holder 15), the period d of the diffraction grating is as follows.

In the above equation, when the sample stage is rotated, δ is changed, so the period of the diffraction grating is changed.

Figure 2 shows the change of the period of the diffraction grating with the change in δ. For example, if the wavelength is 325 nm and δ = 45 °, the period of the diffraction grating is 230 nm. 2, the period of the diffraction grating is in the range of 179 to 385 nm when δ is changed in the range of 25 ° to 65 °.

An SEM image of a nanowire array (diffraction grating) fabricated to have a 230 nm cycle using FIG. 1 is shown in FIG. 3. 3 (a) was produced by exposing the laser output for 2 minutes at 0.15 mW so that the line width with the PR pattern and the line width without the PR pattern were 1: 1.

On the other hand, FIG. 3 (b) shows that the line width with and without the PR pattern is 1: 2 by exposing for 2 minutes and 30 seconds when the laser power is 0.15 mW. The PR used here was mixed with three times more thinner to thin the film thickness.

In this case, when the light output exceeds 0.2 mW, the exposure time is too short due to overexposure, and thus it is preferable that the light output is 0.2 mW or less. At this time, when the exposure time is less than 2 minutes, the line width of the photoresist is wider than the line width without the photoresist, and when the exposure time is greater than 2 minutes, the line width of the photoresist is narrower than the line width without the photoresist.

As the substrate used in FIG. 3, all III-V compound semiconductors such as Si, GaAs, InP, InGaAs, glass, transparent electrode glass, oxide thin film, dielectric thin film, and metal thin film substrate may be used. The substrate materials may be etched using the PR pattern as an etching mask to directly transfer the PR pattern onto the substrate. By using dry etching such as reactive ion etching (RIE), the substrate may be etched in the vertical direction. In particular, when a wet etching solution having a different etching rate according to the crystal direction of the single crystal is used, the pattern transferred to the substrate becomes different from the PR pattern.

4 is a nanowire array (diffraction grating) etched using PR as an etching mask. 4 (a) shows a diffraction grating having an etched section of a triangular shape, and FIG. 4 (b) shows a diffraction grating having a thin line width and a wide space between prehistoric teeth.

When the nanomaterials (nanotubes, nanowires) are self-assembled by the solution process using FIG. 3, a multi-channel FET electronic device of a nanowire array may be manufactured. Nanomaterials can be assembled in areas covered with PR.

5 is a process chart in which SWNTs are self-assembled in a PR pattern that is a nanowire array (diffraction grating). First, the diffraction grating sample having the PR pattern manufactured in FIG. 3 is immersed in a hexane solution to remove moisture from the surface, and then immersed in an electrically neutral octadecyltrichlorosilane (OTS) solution to deposit an OTS thin film 19 on the surface. Be sure to

When the PR pattern is removed with acetone, the substrate 23 in the area where the PR 20 is located is exposed. This sample is then immersed in the APTES solution to deposit the APTES thin film 21 on the exposed substrate 23.

APTES (3-aminopropyl trimethoxysilane) has a positively charged functional group and can be used for self-assembly of negatively charged SWNTs. Next, when the sample having the APTES and OTS patterns is immersed in the SWNT solution, the self-assembly of the SWNT (substrate 23) is completed because the SWNT (substrate 23) adheres only to the APTES pattern. The self-assembly process of FIG. 5 may be performed using the diffraction grating sample of FIG. In this case, after the substrate 23 is etched, the process of FIG. 5 may be repeated without removing the PR used as an etching mask.

FIG. 6 is a conceptual diagram (FIG. 6 (a)) in which nanomaterials are self-assembled in a nanowire array (diffraction grating) and a structure diagram of a nanowire multichannel FET device fabricated using the same. By using the line width of the PR nanowires by using Figure 2 can be arranged in the width direction by one nanotube or nanowire in each channel constituting the nanowire array.

Next, a source and a drain electrode pattern are formed by using photolithography on a nanowire array in which the nanomaterials are aligned one by one in the width direction, and then Ti / Au is deposited on the electrode pattern and then lift-off. The drain electrode 24 and the source electrode 25 are manufactured by the method to complete the multichannel FET device. In FIG. 6, reference numeral 26 denotes a carbon nanotube.

As a result, nanochannel array multichannel FET devices can carry larger currents than single-channel FET devices made from just one nanotube, as well as larger charge transfer than FET devices using SWNT's random network. You can also get Therefore, the shortcomings of the conventional single channel FET device and the network FET device can be solved.

H. I. Smith, "Low cost nanolithography with nanoaccuracy," Physica E, Vol. 11, pp. 104-109 (2001).

The present invention relates to a method for manufacturing a multichannel FET device using a nanowire array. It provides nanowire multi-channel using large area / low cost laser interference lithography process and self-assemble nanostructure material (nanotube or nanowire) in nanowire array using solution process.

Laser interference lithography not only provides a means by which nanowire arrays can be manufactured inexpensively in large areas, but also because the width of the nanowires can be easily adjusted as the sample holder is rotated. Only nanomaterials allow for the creation of nanowire arrays that can be arranged.

Nanowire arrays and laser lithography are compatible with the photolithography process used in the existing silicon semiconductor industry, so they can be mass-produced at low cost.

Therefore, the present invention manufactures a nanowire multichannel FET device or a nanowire multichannel FET array device based on the FET device and a system on chip (SOC) chip in which the devices and the driving circuit are integrated in a mass production method. It is very useful industrially because it provides a means to do so.

While the invention has been shown and described with respect to certain preferred embodiments thereof, the invention is not limited to these embodiments, and has been claimed by those of ordinary skill in the art to which the invention pertains. It includes all the various forms of embodiments that can be carried out without departing from the spirit.

1 is a block diagram of a laser interference lithography apparatus according to an embodiment of the present invention,

2 is a graph showing the change of the period of the diffraction grating according to the change in δ angle when the wavelength is 325nm,

Figure 3 is a photograph showing a nanowire array made of a photoresist pattern according to an embodiment of the present invention,

Figure 4 is a photo showing the nanowire array structure etched using a photoresist according to another embodiment of the present invention as an etching mask,

5 is a flowchart illustrating a process of self-assembling a SWNT having a negative charge functional group in a diffraction grating pattern according to an embodiment of the present invention;

6 is a schematic view showing a conceptual diagram of a nanomaterial self-assembled in a nanowire array according to the present invention and a nanowire multichannel FET device fabricated using the same.

<Description of the symbols for the main parts of the drawings>

10: laser 11: expanding telescope

12: Power Monitor 13: Lloyd Mirror

14 Sample 15 Sample Holder

16: rotating stage 17: manual micrometer

18: collimator 19: OTS thin film

20: PR 21: APTES thin film

22: SWNT 23: substrate

Claims (13)

In the method of manufacturing a nanowire multichannel field effect transistor device, Preparing a periodic photoresist micropattern using a laser interference lithography process, the cycle and the width of the valleys (or floors) being varied according to the rotation angle δ and exposure time of the sample holder; Manufacturing a periodic nanowire pattern by adsorbing nanomaterials to a valley or a floor of the periodic photoresist fine pattern by a self-assembly process; And And fabricating a multichannel field effect transistor device using the periodic nanowire pattern. The method according to claim 1, The laser interference lithography process comprises the steps of expanding and spatially filtering a laser beam through a pinhole such that the laser beam is coherent; The coherent laser beam being parallel light by a collimator; The coherent laser beam is aligned toward an Lloyd mirror and a sample holder perpendicular to each other; And And forming a periodic line pattern of interference light intensity on the photoresist-coated substrate, wherein the aligned coherent laser beam is formed. The method according to claim 2, The thickness of the photoresist thin film in the step of manufacturing the periodic photoresist fine pattern 500 ~ 1000

A method of manufacturing a nanowire multi-channel field effect transistor device comprising spin coating on a substrate by mixing a relatively larger amount of thinner than the amount of photoresist to make it. The method according to claim 2, The method of manufacturing a nanowire multi-channel field effect transistor device, characterized in that the laser light output exposed in the step of manufacturing the periodic photoresist fine pattern is 0.2mW or less. The method according to claim 4, When the nanowire array is manufactured with a light output of 0.2 mW or less through the laser interference lithography process, the exposure time is constantly adjusted so that the line width with the photoresist and the line width without the photoresist are at a constant ratio. Method of manufacturing a multi-channel field effect transistor device. The method according to claim 2, In the step of manufacturing the periodic photoresist micropattern

And a period d of the nanowire array according to the rotation angle δ of the sample holder, wherein λ is a wavelength of a laser beam. The method according to claim 2, A method of manufacturing a nanowire multi-channel field effect transistor device, wherein the substrate on which the nanowire array of the photoresist pattern is manufactured is made of any one material selected from semiconductor, glass, oxide thin film, dielectric thin film and metal thin film. . The method of claim 7, The nanowire array of the photoresist pattern is a nanowire multi-channel field effect transistor device manufacturing method characterized in that the etching using a photoresist pattern as an etching mask on the substrate. The method according to claim 1, In the self-assembly process, the nanomaterial is adsorbed to produce a periodic nanowire pattern. Depositing OTS in a region free of photoresist in a sample having a nanowire array made of laser interference lithography; Removing the photoresist remaining in the sample; And And aligning the nanomaterial having no functional groups in the region where the photoresist has been removed. The method according to claim 1, In the self-assembly process, the nanomaterial is adsorbed to produce a periodic nanowire pattern. Depositing OTS in a region free of photoresist in a sample having a nanowire array made of laser interference lithography; Removing the photoresist remaining in the sample; Depositing APTES in the region where the photoresist has been removed; And And aligning the nanomaterial having a negative functional group on the APTES pattern. The method according to claim 9 or 10, The step of fabricating the periodic nanowire pattern by adsorbing the nanomaterial by the self-assembly process includes the step of assembling the nanomaterial to the etched nanowire array using a photoresist as an etch mask on the substrate. Method of manufacturing a multi-channel field effect transistor device. The method according to claim 9 or 10, Manufacturing a nanowire array by adjusting the width of the nanowire so that only one nanomaterial per unit channel is aligned; And The method of manufacturing a nanowire multi-channel field effect transistor device comprising the step of aligning the nanomaterial to the prepared nanowire array. The method according to claim 1, Fabricating a multichannel field effect transistor device using the periodic nanowire pattern Forming a source and a drain electrode pattern using photolithography on a nanowire array in which one nanomaterial is aligned per unit channel in a width direction; And depositing Ti / Au on the electrode pattern and manufacturing a drain electrode and a source electrode by a lift-off method.

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