KR100992599B1 - Apparatus and method for decoding image having multi-operating capability - Google Patents

Abstract

PURPOSE: An image decoder device having a multi calculation function and a method of the same are provided to realize the multi operation in center of movement compensation which requires a lot of time in processing process, thereby processing the movement compensation process time by minimizing it in real time. CONSTITUTION: An entropy decoder(220) receives compressed coded beat stream and performs entropy decoding, thereby outputting the predict information and difference value information. The inverse quantizer inverse-quantized the difference value information inputted from the entropy decoding unit. An inverse converting unit outputs a difference value image by inverse converting the inverse-quantized difference value which is inputted from the inverse-quantized unit. The movement compensation unit outputs a prediction image by performing the movement compensation using the predict information from the entropy decoding unit.

Description

Apparatus and method for decoding image having multi-operating capability}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image decoding apparatus and method having a multi-computation function, and more particularly, to an image decoding apparatus and method suitable for making intermediate pixels according to the provision of a multi-computation function.

Standardized video compression methods, that is, compressed video codecs, include MPEG-1, MPEG-2, MPEG-4, and H.264. Among these standards, H.264 (or MPEG-4 part-10 / AVC), developed jointly by ITU-T and ISO / IEC, is in the spotlight as the next generation video compression technology with high compression ratio and high quality. It has been adopted as the standard video compression codec in DVB-H, Blue ray and HD-DVD.

A general decoding apparatus applied to the above video clip codec is illustrated in FIG. 1. As shown in FIG. 1, the image decoder 100 includes an entropy decoder 110, an inverse quantizer 120, an inverse transform unit 130, a motion compensator 140, an adder 150, and a decoder. Blocking filter unit 160 is included.

The entropy decoder 110 receives the compression-coded bitstream and performs entropy decoding to output quantized coefficients, motion vectors, and the like. The inverse quantization unit 120 and the inverse transform unit 130 perform inverse quantization and inverse transform on the quantized coefficients to obtain a differential image. The motion compensator 140 generates a predictive image by performing motion compensation on the current block determined as a motion block by using the motion vector decoded by the entropy decoder 110. The adder 150 generates a reproduced image by summing the difference image obtained by the inverse transform unit 130 and the predicted image generated by the motion compensator 140. Finally, the deblocking filter unit 160 deblocks the reproduced image generated by the adder 150 to output the display image.

Among the above-described configurations of the image decoder 100, motion compensation requires the most processing time. Since the motion compensation process requires processing a lot of image data, the amount of memory access and computation is very large. In particular, the configuration of interpolating the image according to the motion vector takes the most time among the motion compensation. Since the processing amount of the motion compensation is proportional to the size of the image, when the size of the image is increased, in the worst case, the entire image may not be processed within a desired time, and thus, natural video reproduction may not be possible.

On the other hand, most image codec engineers try to solve the time taken in the process of the above-described motion compensation by mixing the hardware implementation method and the software implementation method. However, due to the use of interpolation filters and the like for obtaining image clarity, the amount of memory accesses and calculations is increased, and thus there is still a problem that real-time processing is not performed.

In order to solve the above problems, it is an object of the present invention to provide an image decoding apparatus and method having a multi-calculation function.

Another object of the present invention is to provide an image decoding apparatus and method suitable for making intermediate pixels according to the provision of a multi-operation function.

In order to achieve the above object, an image decoding apparatus according to the present invention receives an encoded coded bitstream and performs entropy decoding to output prediction information and difference information, and an prediction output to the entropy decoding unit. And a plurality of arithmetic processors for generating and outputting a reproduced image using information and difference information, respectively, wherein each of the plurality of arithmetic processors includes an inverse quantization unit for inversely quantizing difference information input from the entropy decoding unit. And an inverse transformer for inversely transforming the inversely quantized difference information input from the inverse quantizer and outputting a differential image, and performing a motion compensation using the prediction information input from the entropy decoder to output a prediction image. A motion compensator, the predicted image output from the motion compensator, and the inverse An adder for adding a difference image output from the converter and outputting a reproduced image is provided.

In the image decoding apparatus, when the prediction information and the difference information about predetermined blocks are decoded by the entropy decoding unit and the reproduced images are output by each of the plurality of arithmetic processors, the image decoding apparatus predicts the prediction information and the difference by block from the entropy decoding unit. Preferably, the apparatus further includes a control unit providing value information to the plurality of arithmetic processors, respectively.

The image decoding apparatus further includes a frame memory unit for storing reference images to be used in the plurality of arithmetic processors, each of the plurality of arithmetic processors using reference information to locate a reference pixel of a corresponding region from the frame memory unit. It is preferable to further include a reference pixel selecting unit for selecting a and an interface unit for reading the reference pixel value in an integer unit from the reference pixel position selected from the reference pixel selecting unit.

The image decoding apparatus further includes a deblocking filter unit which receives a reproduction image of the adder and performs deblocking to output a display image.

Preferably, the frame memory unit stores the display image output from the deblocking filter unit as a reference image.

Each of the plurality of arithmetic processors may further include an interpolation filter configured to generate a predictive image in a decimal unit using a reference pixel value of an integer unit input from the interface unit.

The interpolation filter unit may include a four-tap interpolation filter having four coefficients for interpolating 1/2 pixel and a six-tap interpolation filter having six coefficients, and adaptively correspond to an input standard.

The interpolation filter unit includes a four-tap interpolation filter having four coefficients, and the four-tap interpolation filter shifts by multiplying predetermined coefficients by four reference pixels in order to interpolate 1/2 pixels, and adding a constant to the values. It is desirable to.

Preferably, the interpolation filter unit is a six-tap interpolation filter having six coefficients for interpolating 1/2 pixels and 1/4 pixels, respectively.

The present invention provides a method for receiving a compression-encoded bitstream and performing entropy decoding to provide prediction information and difference information to a plurality of arithmetic processors, and using differential information input from each of the plurality of arithmetic processors. Obtaining a prediction image, performing a motion compensation using the input prediction image, obtaining a prediction image, and adding a prediction image and a difference image to output a reproduced image in each of the plurality of arithmetic processors. One purpose can be achieved.

According to an embodiment of the present invention, since the multi-operation is implemented based on the motion compensation which takes a lot of time in the process, it is possible to minimize the motion compensation processing time and the like, thereby enabling real-time processing.

In addition, the present invention generates an intermediate pixel with only a minimum of operations in the interpolation filter, thereby optimizing the video decoding apparatus according to the provision of the multi-calculation function.

1 is a diagram illustrating a general decoding apparatus applied to a compressed video codec.
2 is a schematic block diagram of an image decoding apparatus having a multi-operation function according to an embodiment of the present invention.
3 is a detailed block diagram of an image decoding apparatus having a multi-operation function illustrated in FIG. 2.
4 is a view for explaining a position in which a filtering method is changed according to a motion vector in an MPEG-4 decoding apparatus according to an embodiment of the present invention.
5 is a general coding program implemented in the MPEG-4 codec.
6 is a coding program implemented in an MPEG-4 decoding apparatus according to an embodiment of the present invention.
7A to 7B are diagrams for describing a position at which a filtering method is changed according to a motion vector in an H.264 decoding apparatus according to an embodiment of the present invention.
8 is a flowchart illustrating an image decoding method according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a schematic block diagram of an image decoding apparatus having a multi-operation function according to an embodiment of the present invention.

As shown in FIG. 2, the image decoding apparatus 200 may include an entropy decoder 210, a first operation processor 220, a second operation processor 230, a deblocking filter unit 240, and a frame memory unit. 250 and the control unit 260.

The entropy decoder 210 receives the compression-encoded bitstream and performs entropy decoding to generate and output quantized coefficients, which are differential information, reference frame indexes, and motion vectors, which are prediction information. The bitstream input to the entropy decoding unit 210 is an encoded format of image data and is encoded in an entropy encoding format.

The entropy decoding unit 210 decodes a syntax element encoded by a variable length code (VLC) or a context adaptive binary arithmetic code (CABAC). This syntax element includes picture header information, prediction information, and residual information.

The picture header information includes information such as a picture structure, a picture coding type, a frame size, a reference frame, and the like, and is provided to the controller 260.

The prediction information includes a reference frame index and a motion vector, which are intra frame prediction information used for compensating a block value prediction value within the same frame, or inter frame prediction information used to compensate a block value prediction value from another frame. . The intra frame prediction information is input to the intra predictor (not illustrated), and the reference frame index and the motion vector, which are inter frame prediction information, are input to the first motion compensator 226 and the second motion compensator 236. .

The difference information is expressed in the form of a quantized coefficient obtained by converting a difference value that compensates for an intra or inter prediction value into a frequency domain, and is input to the first inverse quantizer 222 and the second inverse quantizer.

The first arithmetic processor 220 includes a first inverse quantizer 222, a first inverse transform unit 224, a first motion compensator 226, and a first adder 228. 230 also includes a second inverse quantizer 232, a second inverse transform unit 234, a second motion compensator 236, and a second adder 238. Since the operations of the first arithmetic processor 220 and the second processor 230 are substantially the same, a description will be given mainly of the first arithmetic processor 220 in FIG. 2.

The first inverse quantizer 222 receives the difference information decoded by the entropy decoder 210, that is, the quantization coefficients, performs inverse quantization while inversely scanning the transform coefficients that are zigzag-scanned and inputted to the first inverse transformer 224. )

The first inverse transform unit 230 performs inverse transform (IDCT) on the inverse quantized transform coefficients, obtains a difference image, and outputs the difference value image to the first adder 228.

When the macroblock type to be decoded is the inter mode, the first motion compensator 226 receives a reference frame index and a motion vector from the entropy decoder 210 to calculate a corresponding position of the reference frame and performs motion compensation to predict the motion. An image is generated and output to the first adder 228.

The first adder 228 adds the difference image obtained by the first inverse transform unit 224 and the predicted image generated by the first motion compensator 226 to generate a reproduced image, for example, the current block image.

The deblocking filter 240 receives the reproduced image of the first block generated by the first adder 228 and the reproduced image of the second block generated by the second adder 238, and performs deblocking. Output the video. The deblocking filter unit 240 adjusts whether the deblocking filter is employed and the strength of the filter according to the boundary condition of the unit block. In case of H.264 standard image, it passes through deblocking filter unconditionally, but in case of other standard image, for example MPEG-2, it does not go through deblocking filter.

The frame memory unit 250 is a memory for storing the display image passing through the deblocking filter unit 240, and the display image stored in the frame memory unit 250 includes the first motion compensator 226 and the second motion. The compensation unit 236 is used as a reference image. In addition, according to the circuit design, a reproduction image of a block output from the first adder 228 and the second adder 238 may be stored in the frame memory 250.

The control unit 260 receives picture header information from the entropy decoding unit 210, and controls the first operation processor 220, the second operation processor 230, the deblocking filter unit 240, and the frame memory unit 250. To control.

Meanwhile, in FIG. 2, the entropy decoding unit 210 and the control unit 260 have been separately described, but may be implemented by a single processing processor, and preferably, an ARM.

3 is a detailed block diagram of an image decoding apparatus having a multi-operation function illustrated in FIG. 2.

As shown in FIG. 3, the image decoding apparatus 200 may include the entropy decoding unit 210, the first operation processor 220, the second operation processor 230, and the frame memory unit 250 illustrated in FIG. 2. And a controller 260. In FIG. 3, the arithmetic processor is described as a first arithmetic processor 220 and a second arithmetic processor 230, but this is for describing a plurality of arithmetic processors, and the present invention is not limited thereto.

The entropy decoder 210 receives the compressed coded bitstream and performs entropy decoding, and stores information about macroblocks, that is, quantization coefficients, reference frame indexes, and motion vectors for each macroblock, in the entropy memory 312. do. The entropy memory 312 stores information about predetermined macroblocks, which correspond to the number of the operation processors 220 and 230. The entropy decoder 210 may store information about macro blocks in the entropy memory 312 in slice units. When information on predetermined macroblocks is stored in the entropy memory 312, the controller 260 provides the information to the first arithmetic processor 220 and the second arithmetic processor 230.

Since the operations of the first arithmetic processor 220 and the second arithmetic processor 230 are substantially the same, a description will be given mainly of the first arithmetic processor 220 in FIG. 3 as in FIG. 2.

The first operation processor 220 may include a first inverse quantizer 222, a first inverse transform unit 224, a first motion compensator 226, a first adder 228, and a first And an interface unit 322 and a first differential image memory 324.

The first interface unit 322 is an interface for communicating the first operation processor 220 and the entropy decoding unit 210, the controller 260, or the memory controller 360 with each other.

The first inverse quantizer 222 receives the quantized coefficients decoded by the entropy decoder 210, performs inverse quantization while inversely scanning the input transform coefficients which are zigzag-scanned, and outputs the inverse quantized coefficients to the first inverse transformer 224.

The first inverse transform unit 230 obtains a differential image by inverse transforming (IDCT) the inverse quantized transform coefficient and stores the difference image in the first differential image memory 324.

The first differential image stored in the first differential image memory 324 may be stored and then output to the first adder 228 at the time when the predicted image is output from the first motion compensator 226. In addition, it may be stored in the frame memory unit 250, which is the main image memory area, and then read again at the time point when the predicted image is output from the first motion compensator 226 and output to the first adder 228.

The first motion compensation unit 226 receives the reference frame index and the motion vector from the entropy memory 3120 through the first interface unit 322 to perform motion compensation. The first reference pixel memory 328, the first interpolation filter unit 330, and the first prediction image memory 332 are included.

The first reference pixel selector 326 receives a reference frame index and a motion vector from the entropy memory 3120 through the first interface 322 to select a pixel position. The first reference pixel selector 326 reads the integer value of the reference pixel from the frame memory unit 250 through the first interface unit 322 using the position of the pixel.

The first reference pixel memory 328 stores reference pixel values in integer units read from the frame memory unit 250. The first interpolation filter unit 330 interpolates the reference pixel values in integer units and converts the pixel values of the prediction image in decimal units. The first interpolation filter unit 330 may include a 4-tap interpolation filter and a 6-tap interpolation filter to adaptively correspond to MPEG-4 and H.264. The first prediction image memory 332 stores the prediction image of the decimal unit output from the first interpolation filter unit 330.

The first adder 228 generates the reproduced image of the first block by summing the difference image of the first difference image memory 324 and the first prediction image memory 332.

The frame memory unit 250 is a memory for storing the display image passing through the deblocking filter unit 240, and the display image stored in the frame memory unit 250 includes the first motion compensator 226 and the second motion. The compensation unit 236 is used as a reference image. According to a circuit design, a block image output from the first adder 228 and the second adder 238 may be stored in the frame memory 250.

The memory controller 360 controls the flow of image information between the frame memory unit 250, which is a main image memory area, and the first or second arithmetic processor 220.

The control unit 260 receives picture header information from the entropy decoding unit 210, and controls the first operation processor 220, the second operation processor 230, the deblocking filter unit 240, and the frame memory unit 250. To control. In addition, the controller 260 stores information on predetermined macroblocks in the entropy memory 312 and completes motion compensation in the first and second arithmetic processors 220 and 230 for all macroblocks. If necessary, information about each macroblock is provided to the first arithmetic processor 220 and the second arithmetic processor 230.

In FIG. 3, the first difference image memory 324, the first reference pixel memory 328, and the first prediction image memory 332 are separately described, but may be formed of one SDRM.

Hereinafter, the first interpolation filter unit 330 and the second interpolation filter unit 350 shown in FIG. 3 will be described in more detail with reference to FIGS. 4 to 7.

The first interpolation filter unit 330 and the second interpolation filter unit 350 illustrated in FIG. 3 may include a 4-tap interpolation filter and a 6-tap interpolation filter to adaptively correspond to MPEG-4 and H.264. have.

Currently, video compression codecs do not indicate only pixels in a reference image, that is, integer pels, but half pixels or half pixels located between half of integer pixels. The quarter pel located at quarter is also indicated. However, since 1/2 and 1/4 pixels are pixels that do not originally exist in the reference image, the values of these pixels are generated by using pixel interpolation.

4 is a diagram for explaining a position at which a filtering method is changed according to a motion vector in an MPEG-4 decoding apparatus according to an embodiment of the present invention.

In FIG. 4, uppercase letters G, H, M, and N are integer pixel positions, and b, h, j, m, and s are half pixel positions. Equation 1 below is an expression representing motion compensation filtering of MPEG-4.

[Equation 1]

As can be seen from Equation 1 above, in the case of the general 4-tap interpolation filter corresponding to MPEG-4 illustrated in FIG. 4, different equations are applied depending on their positions in interpolating 1/2 pixels. That is, in Equation 1, if the integer unit, that is, the integer pixel, the value of the corresponding position is used as it is, but in the case of the decimal unit, that is, the real pixel, three different operations are performed according to the position. And the coding for implementing this is shown in FIG.

As shown in FIG. 5, a general processor performs one of four if loops. In this case, the execution order of the general processor is when pos == 0, pos == 1, pos == 2 and pos == 3. Assuming 1cycle for performing data loading, storing, and arithmetic operations in a general processor, a maximum of 2688 cycles are required to perform one macroblock (MB). Therefore, assuming that the resolution of the image is QVGA, 300 x 2688 = 806 400 cycles are required to perform motion compensation filtering on one picture.

Meanwhile, when the above Equation 1 is applied to the present invention, the above four situations must always be performed in the multi-computation processor, and all of the results are stored in a memory to selectively use a value. In other words, unlike a general processor, a multi-computation processor is executed in N MB units at the same time, and all four should be performed without performing any one according to the if conditional statement. Therefore, in order to perform motion compensation filtering of 1 MB in a multi-processor, 6 x (128 + 256 + 256 + 448) = 6528 cycles is required. It takes 6528 x 15 = 97920 cycles to perform motion compensation filtering.

In other words, if all the motion compensation filtering is performed according to the position of the motion vector in the multi-processing processor as described above, redundancy occurs and many cycles are required. It is suggested to use one operation that does not change.

[Equation 2]

C1, c2, c3 and c4 in Equation 2 are coefficients of a 4-tap interpolation filter, and C means rounding control. The coefficients c1, c2, c3 and c4, the rounding control C and shift can be applied as shown in Table 1 according to the motion vector.

( mvx & 1) | (( mvy & 1) << 1) C1 C2 C3 C4 C Shift 0 One 0 0 0 0 0 One One One 0 0 1-round One 2 One 0 One 0 1-round One 3 One One One One 2-rounf 2

In order to interpolate the 1/2 pixel, the four-tap interpolation filter multiplies a predetermined coefficient for each of the four reference pixels, adds a predetermined coefficient, and shifts the value by adding a constant.

Coding that implements this is shown in FIG. 6. As shown in FIG. 6, in parallel implementation, it takes 16 + 9 * 64 = 592 cycles and 11840 cycles per frame to perform motion compensation filtering for 20 MB. As a result, filtering of motion compensation can be implemented.

7A to 7B are diagrams for describing a position at which a filtering method is changed according to a motion vector in an H.264 decoding apparatus according to an embodiment of the present invention.

The 6-tap interpolation filter in the H.264 decoding apparatus performs motion compensation in units of 1/4 unlike MPEG-4. In the H.264 encoding apparatus, first, motion prediction is performed in units of 1/2 pixels in the same manner as in MPEG-4, and based on the obtained result, second interpolation is performed again to interpolate 1/4 pixels.

In Figs. 7A to 7B, the uppercase alphabet letters are integer pixel positions, b, h, m, s, cc, dd, ee, ff, gg and hh are 1/2 pixel positions and the remaining portions are 1/4 pixel positions. Positions of the 1/2 pixel are interpolated from integer position samples using 6-tab Finite Impulse Response (FIR) filters and weights, and 1/4 pixels are interpolated from the half pixel position samples using a linear filter, i.e., an average value. .

In FIG. 7A, b, h, m and s are calculated from integer pixels in the horizontal or vertical direction, and the remaining j is interpolated using cc, dd, h, m, ee and ff. 7B shows motion compensation at quarter pixel position. Equation 3 below is a formula representing the motion compensation filtering of the general H.264.

&Quot; (3) &quot;

Equation 3 shows an equation for motion compensation in each pixel.

Table 2 shows a method of performing in the horizontal direction and the vertical direction according to each pixel position in FIG. 7A.

Pixel position Horizontal direction Vertical direction 1/2 pixel interpolation 1/4 pixel interpolation 1/2 pixel interpolation 1/4 pixel interpolation G x x x x a o o x x b o x x x c o o x x d x x o x e o o o x f x x o o g o o o x h x x o x i x x o o j o x o x k o o o x n x x o o p o o o x q x x o o r o o o x

In order to apply Table 2 to the arithmetic processor, 1/2 pixel interpolation and 1/4 pixel interpolation must be performed differently according to pixel positions in the horizontal and vertical directions.

In this case, the expected number is 16. In C or C ++, you only need to execute one of 16 conditional statements, but for multi-computing processors, you must perform 16 1/2 pixel interpolation and 1/4 pixel interpolation. This increases the amount of computation and results in real-time processing. Therefore, as in MPEG-4, the following equations (4) and (5) are applied to a multi-processing processor. When using Equations 4 and 5, both 1/2 pixel operations and 1/4 operation can be processed. Finally, 16 operations can be done in two.

&Quot; (4) &quot;

pred_t0 [x] = round (fh [0] * ref [x] + fh [1] * ref [x + 1] + fh [2] * ref [x + 2] + fh [3] * ref [x + 3] + fh [4] * ref [x + 4] + fh [5] * ref [x + 5])

pred_t1 [x] = round (fv [0] * pred_t0 [x] + fv [1] * pred_t0 [x + 1] + fv [2] * pred_t0 [x + 2] + fv [3] * pred_t0 [x + 3] + fv [4] * pred_t0 [x + 4] + fv [5] * pred_t0 [x + 5])

Here, pred_t0 [x] means integer pixels and 1/2 pixels in the horizontal direction, and pred_t1 [x] means integer pixels and 1/2 pixels in the vertical direction.

[Equation 5]

pred_t2 [x] = round (fh [0] * ref [x] + fh [1] * ref [x + 1] + fh [2] * ref [x + 2] + fh [3] * ref [x + 3] + fh [4] * ref [x + 4] + fh [5] * ref [x + 5])

recon [x] = round ((C1 * (fv [0] * pred_t2 [x] + fv [1] * pred_t2 [x + 1] + fv [2] * pred_t2 [x + 2] + fv [3] * pred_t2 [x + 3] + fv [4] * pred_t2 [x + 4] + fv [5] * pred_t2 [x + 5] +512) >> 10 + pred_t1 [x] + C2) >> shift)

Here, pred_t2 [x] means integer pixels and 1/2 pixels in the horizontal direction, and recon [x] means 1/4 pixels.

As can be seen from the above Equations 4 and 5, Equations 4 and 5 can obtain 1/2 pixel and 1/4 pixel only with a 6-tap interpolation filter.

Equation 4 multiplies a predetermined coefficient for each of six reference pixels to interpolate integer pixels and 1/2 pixels in the horizontal direction, and adds the above six interpolations to interpolate integer pixels and 1/2 pixels in the vertical direction. Predetermined coefficients are multiplied by the given integer pixels and 1/2 pixels, respectively.

In addition, Equation 5 multiplies a predetermined coefficient for every six reference pixels to interpolate integer pixels and 1/2 pixels in the horizontal and vertical directions, and adds the above six interpolated to interpolate 1/4 pixels. It can be seen that each of the 1/2 pixels is multiplied by a predetermined coefficient and added to each of them, and the value is shifted by adding the integer pixels in the vertical direction and 1/2 pixels obtained by the equation (4).

Fh and fv in Equations 4 and 5 have different values according to motion vectors.

Table 3 shows fh and fv values determined according to the motion vector in Equation 4.

(mvx & 3) │ ((mvy & 3) << 2) fh [6] fv [6] 0 0,0,32,0,0,0 0,0,32,0,0,0 4.8,9,12 0,0,32,0,0,0 1, -5,20,20, -5,1 11 0,0,0,32,0,0 1, -5,20,20, -5,1 10 1, -5,20,20, -5,1 1, -5,20,20, -5,1 13 1, -5,20,20, -5,1 0,0,0,32,0,0 1,2,3,5,6,7 1, -5,20,20, -5,1 0,0,32,0,0,0

Table 4 below shows fh and fv values determined according to the motion vector in Equation 5.

(mvx & 3) │
((mvy & 3) << 2) fh [6] fv [6] C1 C2 shift 0,2,8,10 0,0,0,32,0,0 0,0,32,0,0,0 0 0 0 3 0,0,32,0,0,0 1, -5,20,20, -5,1 One One One 12 0,0,32,0,0,0 0,0,0,32,0,0 One One One 1,4 0,0,0,32,0,0 0,0,0,32,0,0 One One One 6,9,11,14 1, -5,20,20, -5,1 1, -5,20,20, -5,1 One One One 5,13 0,0,32,0,0,0 1, -5,20,20, -5,1 One One One 7,13,15 0,0,0,32,0,0 1, -5,20,20, -5,1 One One One

8 is a flowchart illustrating an image decoding method according to an embodiment of the present invention.

The entropy decoding unit 210 receives the compressed coded bitstream, performs entropy decoding, and outputs prediction information and difference information (S802).

When the prediction information and the difference information about the predetermined blocks are decoded in the entropy decoder 210 and the reproduced images are output from the first and second arithmetic processors 220 and 230, the entropy decoder 210 From the block to the prediction information and the difference information is provided to the first operation processor 220 and the second operation processor 230 (S804).

The first arithmetic processor 220 and the second arithmetic processor 230 inversely quantize and inversely transform difference information input from the entropy decoding unit 210 to output a difference image, and are input from the entropy decoding unit 210. The prediction image is output by performing motion compensation using the prediction information (S806).

The first operation processor 220 and the second operation processor 230 add the predicted image and the difference image, and output a reproduced image (S810).

The deblocking filter unit 240 receives the reproduced image from the first arithmetic processor 220 and the second arithmetic processor 230, performs deblocking, and outputs a display image (S810).

The display image output from the deblocking filter unit 240 is stored in the frame memory unit 250 as a reference image (S812).

The protection scope of the present invention should be interpreted by the following claims. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention as defined by the appended claims. It should be interpreted that it is included in the scope of right.

210: entropy decoder
220: first computing processor
222: first inverse quantization unit
224: first inverse transform unit
226: first motion compensation unit
228: first adder
230: second computing processor
240: deblocking filter unit
250: frame memory section
260 control unit

Claims (10)

An entropy decoder configured to receive the compression-encoded bitstream and perform entropy decoding to output prediction information and difference information;
An inverse quantizer for inversely quantizing the difference information input from the entropy decoder, an inverse transformer for inversely converting the inverse quantized difference information input from the inverse quantizer, and outputting a difference value image, and the entropy decoder A motion compensation unit for outputting a prediction image by performing motion compensation using the prediction information input from the prediction information, and outputting a reproduction image by summing the prediction image output from the motion compensation unit and the difference image output from the inverse transform unit. A plurality of arithmetic processors including adders each to process the prediction information and the difference information input from the entropy decoding unit in parallel and output a reproduced image; And
When the prediction information and the difference value information for the predetermined blocks are decoded by the entropy decoder and a reproduced image is output by each of the plurality of arithmetic processors, the plurality of pieces of prediction information and the difference information for each block are obtained from the entropy decoder. And a control unit for controlling each of them to be provided to an arithmetic processor. delete The method of claim 1,
And a frame memory unit for storing reference images to be used in the plurality of arithmetic processors.
Each of the plurality of arithmetic processors includes a reference pixel selecting unit that selects a reference pixel position of a corresponding region from the frame memory unit using prediction information, and a reference pixel in an integer unit from the reference pixel position selected by the reference pixel selecting unit. And an interface unit for reading a value. The method of claim 3,
And a deblocking filter unit configured to receive a reproduction image of the adder and perform deblocking to output a display image.
And a display image output from the deblocking filter unit as a reference image in the frame memory unit. The method of claim 3,
And the motion compensator further comprises an interpolation filter module generating a predicted image in a decimal unit by using a reference pixel value of an integer unit input from the interface unit. The method of claim 5,
The interpolation filter module includes a four-tap interpolation filter with four coefficients for interpolating 1/2 pixel and a six-tap interpolation filter with six coefficients for interpolating 1/4 pixel and is adaptive according to an input standard. And an image decoding apparatus according to claim 1, wherein: The method of claim 5,
The interpolation filter module includes a four tap interpolation filter having four coefficients,
And the four-tap interpolation filter multiplies a predetermined coefficient for each of the four reference pixels in order to interpolate 1/2 pixels, and adds a constant to the four reference pixels. The method of claim 5,
The interpolation filter module includes a six-tap interpolation filter having six coefficients,
The interpolation filter module multiplies a predetermined coefficient for each of the six reference pixels respectively input to the six-tap interpolation filter, and then adds an integer pixel and a half pixel in the horizontal direction. And multiplying a predetermined coefficient for each integer pixel and 1/2 pixels obtained in the horizontal direction, and then adding 1/2 pixels or the remaining 1/4 pixels in the vertical direction. Receiving the compression-encoded bitstream and performing entropy decoding to provide prediction information and difference information to a plurality of arithmetic processors;
Obtaining a differential image by using difference information input from each of the plurality of arithmetic processors, and performing a motion compensation using the input prediction image to obtain a predicted image;
Summing the predicted image and the differential image and outputting a reproduced image in each of the plurality of arithmetic processors;
Providing the prediction information and the difference information to a plurality of arithmetic processors may include prediction information for each block when prediction information and difference information for predetermined blocks are decoded and a reproduced image is output from each of the plurality of processors. And providing the difference value information to the plurality of arithmetic processors, respectively.
The obtaining of the difference image and the prediction image may include processing the input prediction information and the difference information in parallel to output a reproduced image. 10. The method of claim 9,
Each of the plurality of arithmetic processors includes a six-tap interpolation filter having six coefficients,
The obtaining of the predicted image may include multiplying a predetermined coefficient for each of six reference pixels respectively input to the six-tap interpolation filter, and adding the multiplying coefficients to obtain integer pixels and half pixels in a horizontal direction, and the six-tap interpolation filter. And multiplying a predetermined coefficient for each of the integer pixels and the 1/2 pixels obtained in the horizontal direction, respectively, and then adding the integer pixels and the 1/2 pixels or the remaining 1/4 pixels in the vertical direction. Decryption method.

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