KR100990090B1 - High-Power Semiconductor Device Having Improved Transconductance - Google Patents

Abstract

A high power semiconductor device is disclosed. The disclosed high power semiconductor device includes a first conductive semiconductor substrate, a gate electrode formed on the semiconductor substrate, a second conductive source region formed on one side of the gate electrode, and a second conductive type formed on the other side of the gate electrode. A drain region between the semiconductor substrate and the gate electrode, the first gate insulating layer adjacent to the source region, the second gate insulating layer adjacent to the drain region, and the first and second gate insulating layers positioned between the first and second gate insulating layers. And a second conductive type drift region formed under the second gate insulating layer, the third gate insulating layer, and the drain region, wherein the third gate insulating layer includes the first and second gate insulating layers. It is relatively thinner than the gate insulating film.

High Power, Transconductance, Gate, CMOS

Description

High-Power Semiconductor Device Having Improved Transconductance

The present invention relates to high power semiconductor devices, and more particularly to high power semiconductor devices having improved transconductance.

It is common for high voltage integrated circuits in which one or more high voltage transistors are placed on the same chip together with low voltage circuits to be widely used in various electrical applications. In such integrated circuits, so-called lateral double-diffused MOS (LDMOS) transistors are high power devices in critical positions. In practical design of this LDMOS transistor, it is fundamentally necessary to minimize the high breakdown down voltage and the on resistance (Ron). However, it is also well known that these two electrical parameters conflict with each other in current process technology.

On the other hand, the on resistance Ron is known as a function of transconductance (gm), which is defined as the derivative of the drain current I _D value with respect to the gate voltage Vgs in the operating region of the transistor. That is, when the transconductance gm of the transistor is increased, the current driving capability is increased, which means that the on resistance Ron is reduced.

Therefore, in order to fabricate a high performance horizontal diffusion transistor, it is required to increase the transconductance under a constant breakdown voltage.

The transconductance is affected by the depth of the junction region of the transistor and the resistance of the wiring providing the voltage to the transistors. In other words, to ensure high transconductance, it must be accompanied by optimization of junction area depth and low wiring resistance.

However, in the current highly integrated semiconductor device, the depth of the junction region is near the limit, and changing the wiring material also causes the manufacturing cost to increase. Therefore, there is a need for a method of securing a stable breakdown voltage and a low on-resistance (high transconductance) by a simple method without increasing the manufacturing cost.

Accordingly, an object of the present invention is to provide a semiconductor device capable of securing a high transconductance while ensuring a high breakdown voltage.

A semiconductor device according to an embodiment of the present invention for achieving the above object of the present invention is a semiconductor substrate of the first conductivity type, the gate electrode formed on the semiconductor substrate, the second conductivity type formed on one side of the gate electrode A source region, a drain region of a second conductivity type formed on the other side of the gate electrode, a first gate insulating layer interposed between the semiconductor substrate and the gate electrode, and adjacent to the source region, and a second gate insulating layer adjacent to the drain region And a gate insulating film including a third gate insulating film positioned between the first and second gate insulating films, and a drift region of a second conductivity type formed under the second gate insulating film, the third gate insulating film, and the drain region. And the third gate insulating layer has a thickness relatively thinner than that of the first and second gate insulating layers. Have

According to the present invention, the thickness of the gate insulating film of the high power semiconductor device is differently formed for each section. That is, the drain region side gate insulating film is formed thickest, the source region side gate insulating film is thinner than that of the drain side, and the gate insulating film of the channel center is formed relatively thinner than the source side and drain side gate insulating film.

By varying the thickness of the gate insulating film in the same manner as the channel direction in this manner, the threshold voltage of the high power semiconductor device can be arbitrarily changed. That is, the change of the threshold voltage may change the carrier density of the inversion layer constituting the channel, thereby adjusting the channel resistivity of the channel in the horizontal direction. This change in channel resistance causes a change in potential in the channel region. In other words, the potential applied between the drain and the source is distributed along the channel. By varying the thickness of the gate insulating layer of the semiconductor device for each section, a potential potential (V) distribution can be made at the boundary between each section and the section. Will be. This rapid potential distribution in the channel serves to increase the magnitude of the electric field (E = dV / dx). As a result, the channel drift rate can be increased, and the transconductance can be increased. Accordingly, the on-resistance can be lowered while maintaining a constant breakdown voltage.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

The high power device of the present exemplary embodiment includes gate insulating layers 120a, 120b, and 120c, a drift region 105, a gate electrode 130, a source region 140a, and a drain region 140b formed on the semiconductor substrate 100. .

The semiconductor substrate 100 may be, for example, a p-type silicon substrate or a silicon on insulator (SOI) having a p-type semiconductor layer. The semiconductor substrate 100 includes a device isolation layer 110 formed to partition the device region ACT in which the LDMOS is to be formed. The device isolation layer 110 may have a local oxidation of silicon (LOCOS) structure or a trench structure.

The gate insulating layer 120 may include a first gate insulating layer 120a, a second gate insulating layer 120b, and a third gate insulating layer 120c having different thicknesses t1, t2, and t3, respectively. The third to third gate insulating layers 120a, 120b, and 120c extend continuously without disconnection. Here, the first gate insulating layer 120a is positioned on the source region 140a side, the second gate insulating layer 120b is positioned on the drain region 140b side, and the third gate insulating layer 120b is formed on the first region. And between the second gate insulating layers 120a and 120b, that is, at the center of the substantial channel. Here, the second gate insulating layer 120b is provided to reduce the reduced surface field (RESURF) of the drift region 105 while reducing the short channel effect as one of the characteristics of the high power semiconductor device. It has a thickness close to the thickness. The second gate insulating layer 120b has the thickest thickness among the first to third gate insulating layers 120a-120c. On the other hand, the third gate insulating film 120c has a relatively thin thickness than the first and second gate insulating films 120a and 120b. When the thickness of the third gate insulating layer 120c is thinner than that of the first gate insulating layer 120a on the source region 140a, the threshold voltage toward the source region 140a is relatively increased, thereby increasing the high channel electric field. electric field may be applied. This increases the channel drift velocity and ultimately the transconductance of the LDMOS transistor.

Here, the line width ratios of the first gate insulating layer 120a, the second gate insulating layer 120b, and the third gate insulating layer 120c may be approximately 1: 1: 1, and the thickness of the third gate insulating layer 120c may be The thickness of the first gate insulating layer 120a may be 1/3 to 1/4.

In this case, the third gate insulating layer 120c may be formed by first forming a thickness of the first gate insulating layer 120a and then etching a portion thereof, or the first gate insulating layer 120a may be formed of a plurality of insulating layers. In addition, the second gate insulating layer 120b may be formed by a local oxidation technique, and may include a plurality of insulating layers more than the first gate insulating layer 120a so as to reduce damage due to local oxidation.

The drift region 105 is formed to be opposite to the substrate and is formed under the second gate insulating layer 120b. Theoretically, the drift region 105 is formed under the second gate insulating layer 120b. However, when the drive-in process for ion activation is performed, the drift region 105 is formed in addition to the lower portion of the second gate insulating layer 120b. It is formed over the gate insulating film 120c and the drain region 140b. Accordingly, the drift region 150 may be a drain region that is substantially double-diffused in the horizontal direction.

The gate electrode 130 is formed on the gate insulating layer 120 having various thicknesses. In this case, the gate electrode 130 may have a stepped shape due to the thickness of the second gate insulating layer 120c of the thick film. Insulating spacers 135 may be formed on both sidewalls of the gate electrode 130.

The source region 140a is formed by impurities of a type opposite to that of the semiconductor substrate 100, and is formed on the semiconductor substrate 100 on one side of the gate electrode 130, that is, on the side of the first gate insulating layer 120a. The drain region 140b is also formed of impurities opposite to the semiconductor substrate 100 and is formed on the semiconductor substrate 100 on the other side of the gate electrode 130, that is, on the other side of the third gate insulating layer 120c. The semiconductor substrate 100 on which the drain region 140b is formed may be a drift region 105.

2 is a cross-sectional view for describing a high power CMOS transistor according to another exemplary embodiment of the present invention.

Referring to FIG. 2, the high power CMOS transistor includes a high power NMOS transistor NT, a high power PMOS transistor PT, and a device isolation layer 225 separating them. Here, the device isolation layer 225 may be formed of a LOCOS or a trench oxide layer.

The high power NMOS transistor NT includes the semiconductor substrate 200, the gate insulating layers 240a, 240b, and 240c formed on the semiconductor substrate 200, the n-type drift region 230, the gate electrode 250, and the n-type. It may include a source region 260a, an n-type drain region 260b, and a p-type substrate contact region 270.

The semiconductor substrate 200 on the side of the high power NMOS transistor NT has a high concentration p-type buried layer 210 and a p-type epitaxial layer epitaxially grown from the high concentration p-type buried layer 210. It may include.

The gate insulating layer 240 is formed on the semiconductor substrate 200, and includes a first gate insulating layer 240a, a second gate insulating layer 240b, and a third gate insulating layer having different thicknesses t11, t12, and t13. 240c, and the first to third gate insulating films 240a, 240b, and 240c extend continuously without disconnection. Here, the first gate insulating layer 240a is positioned on the source region 260a side, the second gate insulating layer 240b is positioned on the drain region 260b side, and the third gate insulating layer 240c is formed on the first gate insulating layer 240c. And between the second gate insulating layers 240a and 240b. Here, the second gate insulating layer 240b may have the thickest thickness among the first to third gate insulating layers 240a-240c, for example, the thickness of the device isolation layer 225. Meanwhile, the third gate insulating layer 240c may have a relatively thin thickness than the first and second gate insulating layers 240a and 240b, and the thickness of the third gate insulating layer 120c may be the first gate insulating layer 120a. It may be 1/3 to 1/4 the thickness.

The n-type drift region 230 is formed over the second gate insulating layer 240b, the third gate insulating layer 240c, and the drain region 260b.

The gate electrode 250 is formed on the gate insulating layer 240. In this case, the gate electrode 250 may have a stepped shape due to the thickness of the second gate insulating layer 240b of the thick film. Insulating spacers 255 may be formed on both sidewalls of the gate electrode 250.

The source region 260a is formed on the p-type epi layer 220 on one side of the gate electrode 250, that is, on the first gate insulating layer 240a, and the drain region 260b is on the other side of the gate electrode 250. The n-type drift region 230 on the other side of the second gate insulating layer 240b is formed.

The p-type substrate contact region 270 is formed at one side of the source region 270 and electrically connected to the source terminal to provide a voltage to the p-type epitaxial layer 220.

Similar to the high power NMOS transistor NT, the high power PMOS transistor PT also includes a semiconductor substrate 200, gate insulating layers 240a, 240b and 240c formed on the semiconductor substrate 200, and a p-type drift region 235. The gate electrode 250 may include a p-type source region 280a, a p-type drain region 280b, and an n-type substrate contact region 290.

The semiconductor substrate 200 on the side of the high power PMOS transistor PT may include a high concentration n-type buried layer 215 and an n-type epitaxial layer 223 epitaxially grown from the high concentration n-type buried layer 215. have.

The gate insulating layer 240 is formed on the semiconductor substrate 200, and includes a first gate insulating layer 240a, a second gate insulating layer 240b, and a third gate insulating layer having different thicknesses t11, t12, and t13. 240c, and the first to third gate insulating layers 240a, 240b, and 240c continuously extend without disconnecting each other. In this case, the gate insulating layer 240 of the high power PMOS transistor may be obtained by the same steps and methods as the gate insulating layer of the high power NMOS transistor. Here, the first gate insulating layer 240a is positioned on the source region 260a side, the second gate insulating layer 240b is positioned on the drain region 260b side, and the third gate insulating layer 240c is formed on the first gate insulating layer 240c. And between the second gate insulating layers 240a and 240b. The second gate insulating layer 240c may have the thickest thickness among the first to third gate insulating layers 240a-240c, for example, the thickness of the device isolation layer 225. On the other hand, the third gate insulating film 240c has a relatively thin thickness compared to the first and second gate insulating films 240a and 240b.

The p-type drift region 235 is formed under the second gate insulating layer 240b, the third gate insulating layer 240c, and the drain region 280b.

The gate electrode 250 is formed on the gate insulating layer 240. In this case, the gate electrode 250 may have a stepped shape due to the thickness of the second gate insulating layer 240b of the thick film. Insulating spacers 255 may be formed on both sidewalls of the gate electrode 250.

The p-type source region 280a is formed in the n-type epitaxial layer 223 on one side of the gate electrode 250, that is, the first gate insulating layer 240a, and the p-type drain region 280b is formed by the gate electrode ( The p-type drift region 235 is formed on the other side of the 250, that is, on the other side of the second gate insulating layer 240b.

The n-type substrate contact region 290 is formed at one side of the source region 280a and electrically connected to the source terminal s to provide a predetermined voltage to the n-type epitaxial layer 223.

According to the present invention as described above, the thickness of the gate insulating film of the high power semiconductor device is formed differently for each section. That is, the drain region side gate insulating film is formed thickest, the source region side gate insulating film is thinner than that of the drain side, and the gate insulating film of the channel center is formed relatively thinner than the source side and drain side gate insulating film.

In this manner, by varying the thickness of the gate insulating film in the channel direction, the threshold voltage of the high power semiconductor device may be arbitrarily changed. That is, the carrier density of the inversion layer constituting the channel can be changed according to the change of the threshold voltage, and thus the resistance in the horizontal direction of the channel can be adjusted. This change in channel resistance causes a change in potential in the channel region. In other words, the potential applied between the drain and the source is distributed along the channel. By varying the thickness of the gate insulating layer of the high-power semiconductor device for each section, a sharp potential (V) distribution can be made at the boundary between the sections. Will be. This rapid potential distribution in the channel serves to increase the magnitude of the electric field (E = dV / dx). As a result, the channel drift rate can be increased, and the transconductance can be increased. Accordingly, the on-resistance can be lowered while maintaining a constant breakdown voltage.

3 is a graph showing a two-dimensional device simulation showing the speed of electrons moving in a channel region of a high power semiconductor device according to an embodiment of the present invention. According to FIG. 3, it can be seen that the electron velocity (cm / s) is sharply increased at the interface between the first gate insulating film and the second gate insulating film. Since the velocity of the electron is a function of the transconductance, the experiment shows that the transconductance is improved in the vicinity of the step difference between the first and second gate insulating layers.

Although the present invention has been described in detail with reference to the above-described preferred embodiment, the present invention is not limited to the above embodiment, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. It is possible.

1 is a cross-sectional view of a high power semiconductor device according to an embodiment of the present invention;

2 is a cross-sectional view of a high power semiconductor device according to another embodiment of the present invention, and

3 is a two-dimensional device simulation result graph of the electron speed of the n-channel high-power semiconductor device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100,200: semiconductor substrate 120a, 240a: first gate insulating film

120b and 240b: second gate insulating film 120c and 240c: third gate insulating film

Claims (5)

A semiconductor substrate of a first conductivity type; A gate electrode formed on the semiconductor substrate; A source region of a second conductivity type formed on one side of the gate electrode; A drain region of a second conductivity type formed on the other side of the gate electrode; A first gate insulating layer interposed between the semiconductor substrate and the gate electrode, the first gate insulating layer adjacent to the source region, the second gate insulating layer adjacent to the drain region, and a third gate insulating layer positioned between the first and second gate insulating layers; A gate insulating film comprising; And A drift region of a second conductivity type formed under the second gate insulating layer, the third gate insulating layer, and the drain region; The third gate insulating film has a relatively thin thickness than the first and second gate insulating film. The method of claim 1, The second gate insulating film is a thicker film than the first gate insulating film. The method of claim 1, The semiconductor substrate, A buried layer of a first conductivity type embedded in the semiconductor substrate; And A high power semiconductor device comprising an epitaxial layer of the first conductivity type formed on the buried layer of the first conductivity type. The method of claim 1, The high power semiconductor device further includes a device isolation layer for separating the devices, And a thickness of the second gate insulating layer is equal to the thickness of the device isolation layer. The method of claim 1, And the third gate insulating layer is about 1/3 to 1/4 of the thickness of the first gate insulating layer.

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