KR100982960B1 - Method for manufacturing image sensor - Google Patents

Abstract

A method of manufacturing an image sensor is disclosed. The method comprises the steps of: forming a planarization layer on a semiconductor substrate in a pixel array region having at least one photodiode, and a layer of material for the microlens over the top surface of the planarization layer, filling a via hole formed on top of the pad electrode. Applying a light, selectively exposing a region in which the microlens pattern is not formed in the material layer for the microlens using the first exposure mask, and using the second exposure mask for the microlens above the pad electrode. Selectively exposing only the material layer, developing the exposed microlens material layer to form a microlens pattern, and reflowing the microlens pattern to form a microlens corresponding to each photodiode. Characterized in that. Therefore, the exposure energy can be adjusted as desired by the user to the final reflow process to remove the residue of the layer of the microlens material on the pad electrode and cleanly remove it while minimizing the gap (CD) between the microlenses. It has the effect of improving the CD margin (margin) of the formed micro lens.

Image Sensor, Double Exposure, Micro Lens

Description

Method for manufacturing image sensor {Method for manufacturing image sensor}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to a method of manufacturing an image sensor.

In general, an image sensor is a semiconductor device that converts an optical signal into an electrical signal. Among them, CMOS (Complementary Metal Oxide Semiconductor) image sensors use CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits to make photodiodes as many as the number of pixels and use them. Is a device that employs a switching method that sequentially detects output.

For example, a CMOS image sensor consists of a pixel array area with a photodiode that senses light and a CMOS logic circuit area that processes the detected light into an electrical signal and turns it into data. Efforts have been made to increase the ratio of the area of the photodiode or to reduce the path of light input and to form a microlens on the top to collect more light into the photodiode region.

In addition, CMOS image sensors are classified into 3T type, 4T type, 5T type, and the like according to the number of transistors. The 3T type consists of one photodiode and three transistors, and the 4T type consists of one photodiode and four transistors. The equivalent circuit and layout of the unit pixels of the 3T-type CMOS image sensor are as follows.

FIG. 1 is an equivalent circuit diagram of a general 3T CMOS image sensor, and FIG. 2 is a layout diagram illustrating unit pixels of a general 3T CMOS image sensor.

As shown in FIG. 1, a unit pixel of a general 3T CMOS image sensor includes one photodiode (PD) and three nMOS transistors T1, T2, and T3. The cathode of the photodiode PD is connected to the drain of the first nMOS transistor T1 and the gate of the second nMOS transistor T2. The sources of the first and second nMOS transistors T1 and T2 are all connected to a power supply to which the reference voltage VR is supplied, and the gate of the first nMOS transistor T1 is supplied with a reset signal RST. It is connected to the reset.

In addition, the source of the third nMOS transistor T3 is connected to the drain of the second nMOS transistor, the drain of the third nMOS transistor T3 is connected to a read circuit (not shown) via a signal line, and the third nMOS transistor ( The gate of T3 is connected to the column select line to which the selection signal SLCT is supplied. Accordingly, the first nMOS transistor T1 is referred to as a reset transistor Rx, the second nMOS transistor T2 is referred to as a drive transistor Dx, and the third nMOS transistor T3 is referred to as a selection transistor Sx.

As shown in FIG. 2, the unit pixel of a typical 3T CMOS image sensor has an active region 10 defined therein, and one photodiode 20 is formed in a wide portion of the active region 10. Gate electrodes 120, 130, 140 of three transistors are formed in the active region 10 of the portion, respectively. That is, the reset transistor Rx is formed by the gate electrode 120, the drive transistor Dx is formed by the gate electrode 130, and the selection transistor Sx is formed by the gate electrode 140. Here, impurity ions are implanted into the active region 10 of each transistor except for lower portions of the gate electrodes 120, 130, and 140 to form source / drain regions of each transistor. Therefore, the power supply voltage Vdd is applied to the source / drain region between the reset transistor Rx and the drive transistor Dx, and the source / drain region on one side of the select transistor Sx is connected to the read circuit. Although not shown, each of the gate electrodes 120, 130, and 140 described above is connected to each signal line, and each signal line is connected to an external driving circuit having a pad at one end thereof.

A micro lens (ML) of a general image sensor is formed by forming an ML pattern (lens island) through a lithography process using a photoresist and applying heat to reflow. In this case, the reflow process using the thermal process is not easy to control the CD compared to the lithography process where the critical dimension (CD) is relatively easy to adjust, so that the gap space between MLs is narrowed to about 100 nm or less. it's difficult. In order to solve this problem, there is a method of forming the gap between the ML patterns formed in the photo process as small as possible and minimizing the CD change through reflow, but this causes another problem. For example, in the photo process for forming the ML pattern, a small CD must be formed while the pad electrode (metal pad) of the scribe lane is completely opened. At this time, the pad electrode is dug about 0.6 μm deeper than the pixel array region where the ML is formed, and the surface of the pad electrode is formed about 2 μm below the ML formation region when the color filters formed in the pixel array region are combined. Thus essentially defocused exposure intensity is formed. When defocused as described above, a much higher threshold energy (Eth: threshold energy) is required than at on-focus, so it is difficult to form a narrow ML pattern that requires low exposure energy.

FIG. 3 is a graph for explaining a case in which an exposure energy region required for CD formation is hardly used since the pad electrode is not opened, and the solid line 160 corresponds to such a condition. In Fig. 3, the vertical axis represents exposure energy and the horizontal axis represents focus.

The above-mentioned Eth means a minimum exposure energy capable of removing all of the positive resist during front exposure. For example, if the exposure energy for forming an appropriate ML pattern is approximately 220 mJ / cm 2, as shown by the margin window of solid line 160 in FIG. 3, resist residues remain on the defocused pad electrode. The exposure energy to be removed cleanly is approximately 240 mJ / cm 2 or more. In this case, in order to remove all the resist of the pad electrode, an exposure energy of at least approximately 240 mJ / cm 2 should be applied. In such an exposure energy, the ML pattern interval is increased by 1.5 times or more, and thus it is necessary to reduce it in the reflow process. . As a result, the width of the CD, which must be changed using a thermal process, increases, leading to a further reduction in process margins. In the case of recently developed image sensors, the target of the reflowed CD is usually 100 nm or less, and thus, the above-described problem is further increased.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of manufacturing an image sensor capable of cleanly removing resist residues remaining on an upper surface of a pad electrode while forming a sufficiently small gap CD between micro lens patterns in a pixel array region. .

According to an aspect of the present invention, there is provided a method of manufacturing an image sensor, the method including: forming a planarization layer on a semiconductor substrate in a pixel array region having at least one photodiode, and filling a via hole formed on the pad electrode Coating a microlens material layer on the entire upper surface of the planarization layer, selectively exposing a region in which the microlens pattern is not formed in the microlens material layer using a first exposure mask, Selectively exposing only the microlens material layer on the pad electrode using a second exposure mask, developing the exposed microlens material layer to form the microlens pattern, and By reflowing the lens pattern, the microlenses corresponding to the respective photodiodes It is preferable made of a step of sex.

The manufacturing method of the image sensor according to the present invention can adjust the exposure energy as desired by the user so that the gap (CD) between the microlenses can be reduced as much as possible without removing the residue of the material layer for the microlens on the pad electrode. As a result, the CD margin of the microlens formed by the final reflow process can be improved.

Hereinafter, with reference to the accompanying drawings, an embodiment of a manufacturing method of an image sensor according to the present invention will be described as follows.

4A to 4K show cross-sectional views of a method of manufacturing an image sensor according to an exemplary embodiment of the present invention.

Referring to FIG. 4A, an interlayer insulating layer 200 is formed on a semiconductor substrate (not shown) defined by a pixel array region P having at least one photo diode (not shown) and a logic circuit region L. Referring to FIG. For example, after the oxide film is deposited on the semiconductor substrate, the surface of the interlayer insulating layer 200 may be formed by performing a chemical mechanical polishing (CMP) process to planarize the surface. At this time, various structures (not shown) formed on the semiconductor substrate and electrically connected to each other through contact plugs, transistors (not shown) for controlling the on / off of a signal, and red (R: red), green (G) It is a matter of course that a photodiode (not shown) for sensing a green and blue signal is formed.

Referring to FIG. 4B, in the logic circuit region L, a pad electrode 210 is formed on the interlayer insulating layer 200. For example, a metal material such as aluminum is deposited on the interlayer insulating film 200 by sputtering, and silicon nitride materials (SiN, SiON) are deposited thereon, either physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic ALD (Atomic). After depositing by a layer deposition method, the pad electrode 210 may be formed in the logic circuit region L by patterning the same by a photo and etching process. Here, a TiN / Ti laminated film, Ta, TaN, WN, TaC, WC, TiSiN, TaSiN may be used as a barrier layer (not shown) below the pad electrode 210.

Referring to FIG. 4C, an oxide film or the like is deposited on the entire surface of the interlayer insulating layer 200 including the pad electrode 210 and the surface is polished by a CMP process to form a protective film 220. Here, from the pad electrode 210 to prevent the pad electrode 210 from being polished, the oxide film is thickly deposited to remove the step between the pixel array region P and the logic circuit region L by the pad electrode 210. For example, the CMP process can be stopped at a position of 3000 to 5000 kPa.

Referring to FIG. 4D, the protection layer 220 on the upper portion of the pad electrode 210 is selectively removed by a photolithography and etching process to form a via hole 224 for bonding the pad electrode 210 to an external driving circuit.

Referring to FIG. 4E, in the pixel array region P, a color filter layer 230 corresponding to each photodiode (not shown) is formed on the passivation layer 220A. For example, a color having an arbitrary pattern in the pixel array region P by applying a photoresist to the entire surface including the protective film 220A and selectively removing a portion of the photoresist by applying a photo-etching process using a mask. The filter layer 230 may be formed. The color filter layer 230 is formed by containing a pigment showing color in the photoresist, and generally contains pigments of R, G, and B colors. Thus, the color filter layer 230 is composed of an R-color filter layer, a G-color filter layer, and a B-color filter layer.

Referring to FIG. 4F, the planarization layer 240 is formed on the passivation layer 220A of the pixel array region P including the color filter layer 230. For example, a photoresist is applied to the entire surface of the protective film 220A including the color filter layer 230, the surface is polished by a CMP process, and then a photo and etching process using a mask is applied to the photoresist. By selectively removing the photoresist, the planarization layer 240 may be formed in the pixel array region P to cover the color filter layer 230.

Referring to FIG. 4G, the via hole 224 formed on the pad electrode 210 is filled with a microlens material layer 250 applied to the entire upper surface of the planarization layer 240. For example, the material layer 250 for the microlens may be a photoresist.

Referring to FIG. 4H, light 262 such as a laser may be selectively irradiated on a region where the microlens pattern 250A is not formed in the microlens material layer 250 using the first exposure mask 260. It exposes. To this end, the first exposure mask 260 has a light transmitting portion 266 for transmitting light and a blocking portion 264 for blocking light. According to the present invention, in order to reduce the distance w1 of the micro lenses 250B, the first exposure energy of the light irradiated when the first exposure mask 260 is used is set as small as possible. For example, the first exposure energy may be less than 200 mJ / cm 2 to less than 240 mJ / cm 2.

Referring to FIG. 4I, only the microlens material layer 250 on the pad electrode 210 is selectively exposed by irradiating light 276 using the second exposure mask 270. The second exposure mask 270 transmits light and has a width wl (2) having a width w2 (or a pad electrode opening part or terminal via) and a blocking part 270 that does not transmit light. It consists of. The blocking unit 270 may be made of chromium. According to the present invention, the second exposure energy of the light irradiated when the second exposure mask 270 is used to open the pad electrode 210 without residue can be set sufficiently large. For example, the second exposure energy may be 200 mJ / cm 2 to 3000 mJ / cm 2. In this case, when the microlens material layer 250 is exposed using the second exposure mask 270, the pixel array region P is not exposed. Therefore, the distance CD (w1) between the micro lenses 250B formed by the first exposure energy is unchanged, but the pad electrode 210 is secondarily subjected to the second exposure energy. As a result, the microlens material layer 250 formed on the top of the pad electrode 210 is exposed twice, so that the microlens material layer 250 is exposed to a much larger exposure energy compared to the conventional case of exposing once by a single mask. Therefore, in the case of the present invention, when developing the microlens material layer 250, the pad electrode 210 can be opened cleanly without debris that can be left on the pad electrode 210 due to lack of exposure energy.

Referring to FIG. 4J, the exposed microlens material layer 250 is developed to form the microlens pattern 250A. Here, it can be seen that the microlens material layer 250 on the pad electrode 210 is cleanly removed during development by double exposure using the first and second exposure masks 260 and 270.

Referring to FIG. 4K, the microlens pattern 250A is reflowed by baking at a temperature of 150 to 200 ° C., for example, to form a hemispherical microlens 250B. However, the microlens 250B may be implemented in various shapes according to the kind of the microlens material layer 250. The present invention may be implemented in the form of the microlens 250B as long as the microlenses 250B are spaced apart from each other. It can be applied regardless.

Meanwhile, the present invention forms the microlens material layer 250 on the planarization layer 240 while filling the via hole 224 opening the pad electrode 210, and spaces between the microlens patterns 250A. It can be applied to any field that wants to narrow down. Therefore, the present invention is not limited to the process illustrated in FIGS. 4A to 4F to form the pad electrode 210 and to form the planarization layer 240, the color filter layer 230, and the like as described above.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1 is an equivalent circuit diagram of a general 3T CMOS image sensor.

2 is a layout diagram illustrating unit pixels of a general 3T CMOS image sensor.

3 is a graph for explaining a case in which an exposure energy region necessary for CD formation is hardly used since the pad electrode is not opened.

4A to 4K show cross-sectional views of a method of manufacturing an image sensor according to an exemplary embodiment of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

200: interlayer insulating film 210: pad electrode

220: protective film 224: via hole

230: color filter layer 240: planarization layer

250: material layer for the microlens 260: first exposure mask

270: second exposure mask

Claims (5)

In a pixel array region having at least one photo diode, forming a planarization layer on a semiconductor substrate; Applying a layer of microlens material to the entire upper surface of the planarization layer while filling the via hole formed on the pad electrode; Selectively exposing a region in which the microlens pattern is not formed in the microlens material layer using a first exposure mask: Selectively exposing only the material layer for the microlens on the pad electrode using a second exposure mask; Developing the exposed microlens material layer to form the microlens pattern; And reflowing the micro lens pattern to form a micro lens corresponding to each photodiode. The method of claim 1, wherein the manufacturing method of the image sensor is Forming an interlayer insulating film on said semiconductor substrate defined by said pixel array region and a logic circuit region; Forming the pad electrode on the interlayer insulating film in the logic circuit area; Forming a protective film on an entire surface of the interlayer insulating film including the pad electrode; Selectively removing the passivation layer on the pad electrode to form the via hole; And Forming a color filter layer corresponding to each photodiode on the passivation layer in the pixel array region, And the planarization layer is formed on the passivation layer of the pixel array region including the color filter layer. The method of claim 1, wherein the portion of the second exposure mask that does not transmit light is made of chromium. The method of manufacturing an image sensor according to claim 1, wherein the exposure energy at the time of exposure using said first exposure mask is 200 mJ / cm 2 to less than 240 mJ / cm 2. The method of manufacturing an image sensor according to claim 1, wherein the exposure energy at the time of exposure using said second exposure mask is 200 mJ / cm 2 to 3000 mJ / cm 2.

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