KR100978814B1 - Graphic acceleration system for displaying multi 3d graphic using single application processor and method thereof - Google Patents

Abstract

PURPOSE: A graphics acceleration system and a method thereof for indicating a multi 3D graphic by a single application processor by using a multi 3D graphic speed-up apparatus are provided to display a plurality of 3D graphics to an application processor by adding a multi-3D graphic accelerator. CONSTITUTION: An application processor comprises a thirteenth dimensional graphics acceleration module(110). When the first application is processed, the first 3D graphics acceleration module processes data about 3D graphic of the first application as first 3D graphic data. A memory comprises a first frame buffer and the first and the second application storing first 3D graphic data. When the second application is processed, a second 3D graphics acceleration module(210) processes data about 3D graphic of the second application as second 3D graphic data.

Description

GRAPHIC ACCELERATION SYSTEM FOR DISPLAYING MULTI 3D GRAPHIC USING SINGLE APPLICATION PROCESSOR AND METHOD THEREOF}

The present invention relates to a graphics acceleration system and method for displaying multiple 3D graphics with a single application processor, and in particular, by adding multiple 3D graphics accelerators to a single application processor, a plurality of 3D graphics with a single application processor without sacrificing speed. A graphics acceleration system and method for displaying multiple 3D graphics with a single application processor capable of displaying the same.

In the case of a mobile terminal using general 3D graphics, there is one 3D graphics acceleration module 11 inside a system on chip (SoC) as shown in FIG. 1. That is, conventionally, in order to display 3D graphics, the CPU 17 reads data stored in the memory 30 using the system bus. The loaded data is processed by the 3D graphics acceleration module 11 and stored in the frame buffer on the memory 30 again. The 3D graphic data is processed in a form that is called through the display controller 15 and sprinkled on the display 40.

In this conventional configuration, if two 3D graphics are to be displayed simultaneously, simply adding a graphics acceleration module may not achieve the desired result. In other words, if you add two more graphics acceleration modules to execute two contents (applications) with two 3D graphics acceleration modules, the pipeline (AXI bus) in an embedded system can be occupied by only one application. Although there are two graphics acceleration blocks, two applications cannot run at the same time. At the same time, the bandwidth of the limited system bus may cause speed degradation and bottlenecks, resulting in deterioration of overall system stability and performance. In order to display a plurality of 3D graphics on a mobile terminal, which is lower than that of a computer, the next application may be driven only after a single 3D application is driven and stopped. Therefore, to prevent this, double the system bus. However, when the system bus is doubled, there is a problem that the size of the product increases and the production cost of the product increases. In the graphics acceleration module used in the mobile terminal for miniaturization, it is very fatal to increase the size of the product.

On the other hand, in the case of overlaying graphics, clocks must be matched between graphic data to be overlaid. In the related art, a method of storing a graphic image once and then re-reading it according to the clock of another graphic image has been used. However, such a prior art has to write and read a single graphic image continuously, which takes up a large portion of the memory bandwidth, which is connected to the performance degradation of the graphics acceleration system.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and by adding a multi 3D graphics accelerator to a single application processor, a multi application 3D graphics with a single application processor that can display a plurality of 3D graphics with a single application processor without sacrificing speed It is an object of the present invention to provide a graphic acceleration system and a method for displaying the same.

According to another embodiment of the present invention, by simultaneously displaying a plurality of 3D graphics on one display, a graphics acceleration system that can display multiple 3D graphics with a single application processor capable of intuitive and various screen configuration on the mobile device and its It is an object to provide a method.

According to another embodiment of the present invention, the first display controller transmits the first 3D graphic data directly to the second display controller, whereby the second frame buffer is configured to overlay the first 3D graphic data and the second 3D graphic data. 1 It is an object of the present invention to provide a graphics acceleration system and method for displaying multiple 3D graphics using a single application processor that does not require WRITE or READ of 3D graphics data.

In order to achieve the above object, a graphic acceleration system displaying multiple 3D graphics with a single application processor according to an embodiment of the present invention, when the first application is executed, the first 3D data about the 3D graphics of the first application; An application processor incorporating a first 3D graphics acceleration module for processing graphics data; A memory including a first frame buffer for storing the first 3D graphics data, the first application and a second application; And a second 3D graphics acceleration module configured to process data relating to 3D graphics of the second application as second 3D graphics data when the second application is executed. The graphic accelerator includes: a CPU configured to display the multi 3D graphic data by overlaying the first 3D graphic data and the second 3D graphic data, and wherein the application processor controls the application processor; A data bus that is a data transmission path from the application processor; A memory interface that interfaces with the memory; A multi-graphics accelerator interface for performing an interface with the multi-graphics accelerator; And a first display controller configured to transmit the first 3D graphic data stored in the first frame buffer to the multi-graphics accelerator.

delete

According to another aspect of the present invention, there is provided a graphics acceleration system for displaying multiple 3D graphics with a single application processor, wherein the multiple graphics accelerator stores the second 3D graphics data and provides the second 3D graphics data. Frame buffer; And a second display controller configured to overlay the first 3D graphic data and the second 3D graphic data to generate the multi 3D graphic data.

According to another aspect of the present invention, there is provided a graphic acceleration system for displaying multiple 3D graphics using a single application processor, wherein the second display controller includes a vertical signal VSYNC, a horizontal signal HSYNC, a data enable signal DE, and a clock. The signal CLK may be received from the application processor as a control signal, and overlay may be performed according to the vertical signal, the horizontal signal, and the data enable signal.

According to another embodiment of the present invention, a graphics acceleration system for displaying multiple 3D graphics with a single application processor includes: when the multi 3D graphics data overlays the first 3D graphics data and the second 3D graphics data, N; Overlaying three layers is characterized by a 3 + N-1 clock (CLK) delay.

According to another aspect of the present invention, there is provided a graphics acceleration system for displaying multiple 3D graphics using a single application processor, wherein the second display controller is configured to perform the first 3D by any one of alpha blending, color masking, clipping, and transparency. And overlaying the graphic data and the second 3D graphic data into multiple 3D graphic data.

A graphics acceleration system for displaying multiple 3D graphics with a single application processor according to another embodiment of the invention is characterized in that the data bus is an ahb Bus or an AXI Bus.

According to another embodiment of the present invention, a graphics acceleration system for displaying multiple 3D graphics with a single application processor is characterized in that the CPU is an ARM core.

A graphics acceleration system for displaying multiple 3D graphics with a single application processor according to another embodiment of the invention is characterized in that it operates in RGB interface mode.

A graphics acceleration method for displaying multiple 3D graphics with a single application processor, according to an embodiment of the present invention, includes: a first application driving step in which the application processor drives a first application stored in a memory; A first 3D graphic data processing step of the application processor processing first 3D graphic data associated with the first application; A second application driving step of the application processor driving the second application stored in the memory; A second 3D graphic data processing step of the multi graphics accelerator processing second 3D graphic data associated with the second application; And processing, by the multi-graphics accelerator, receiving the first 3D graphic data, and overlaying the first 3D graphic data and the second 3D graphic data with the multi 3D graphic data. Processing, by the application processor, data about 3D graphics of the first application into the first 3D graphics data according to the driving of the first application in a first 3D graphics data processing step; Storing the first 3D graphic data; And transmitting the first 3D graphic data to the multi-graphics accelerator according to a control signal.

delete

According to another aspect of the present invention, there is provided a graphics acceleration method for displaying multiple 3D graphics using a single application processor, wherein the multi-graphics acceleration device includes a vertical signal (VSYNC), a horizontal signal (HSYNC), Receiving a data enable signal DE and a clock signal CLK from the application processor as a control signal; And performing an overlay according to the vertical signal, the horizontal signal, and the data enable signal.

According to another aspect of the present invention, there is provided a graphic acceleration method for displaying multiple 3D graphics using a single application processor, after the processing of the multiple 3D graphics data, a display step of displaying the multiple 3D graphics data through a display; Characterized by performing.

A graphics acceleration system and method for displaying multiple 3D graphics with a single application processor in accordance with the present invention, by adding multiple 3D graphics accelerators to a single application processor, display multiple 3D graphics with a single application processor without compromising speed. It provides an effect that can be done.

Graphic acceleration system and method for displaying multiple 3D graphics with a single application processor according to another embodiment of the present invention, by displaying a plurality of 3D graphics on one display at the same time, it is possible to intuitively and various screen configuration on a mobile device It provides the effect of displaying multiple 3D graphics with a single application processor.

According to another aspect of the present invention, there is provided a graphics acceleration system and method for displaying multiple 3D graphics with a single application processor, wherein the first display controller sends the first 3D graphics data directly to the second display controller, thereby providing the first 3D graphics. When overlaying the data and the second 3D graphic data, the second frame buffer does not have to write or read the first 3D graphic data, thereby providing an effect that may not degrade performance.

1 is a system diagram illustrating a graphics acceleration system for displaying a single 3D graphic with a single application processor in accordance with the prior art.
2 is a system diagram illustrating a graphics acceleration system for displaying multiple 3D graphics with a single application processor in accordance with an embodiment of the present invention.
3 is an overlay timing diagram of a graphics acceleration system displaying multiple 3D graphics with a single application processor in accordance with an embodiment of the invention.
4 is an overlay timing diagram of a graphics acceleration system displaying multiple 3D graphics with a single application processor in accordance with an embodiment of the invention.
5 is a diagram illustrating a delay of a graphics acceleration system for displaying multiple 3D graphics with a single application processor in accordance with an embodiment of the present invention.
6 is a flow diagram illustrating a graphics acceleration method for displaying multiple 3D graphics with a single application processor in accordance with an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating a graphics acceleration system for displaying multiple 3D graphics with a single application processor in accordance with an embodiment of the present invention.

Referring to FIG. 2, a graphic acceleration system displaying multiple 3D graphics with a single application processor according to the present invention may include an application processor 100, a multi graphics accelerator 200, and a memory 300. .

The memory 300 may include a first frame buffer 310 and store the first application 330 and the second application 350.

First application 330 and second application 350 are applications that include 3D graphics. 3D graphic data associated with the first application 330 is referred to as first 3D graphic data, and 3D graphic data associated with the second application 350 is referred to as second 3D graphic data.

When the first application 330 is executed, the first frame buffer 310 stores the first 3D graphics data processed by the first 3D graphics acceleration module 110 in relation to the 3D graphics. The frame buffer 310 is a part for outputting an image signal to a raster display and may be called a refresh memory. The frame buffer has at least one screen of screen data converted into pixel representations, and outputs the memory contents as a bit string in accordance with the signal.

The application processor 100 executes an application stored in the memory 300 and processes 3D graphics. To this end, the application processor 100 may include a CPU 190, a memory interface 130, a first 3D graphics acceleration module 110, a first display controller 150, and a multi-graphics accelerator interface 170. Can be. The data of the application processor 100 may move through the system bus 180.

The CPU 190 performs a function of controlling the application processor 100. The CPU 190 may in particular be an ARM core used in a portable terminal. That is, when a command enters the CPU through an input, the CPU 190 drives the first application 330 stored in the memory 300.

The memory interface 130 performs an interface between the application processor 100 and the memory 300.

The data bus 180 is a data transmission path in the application processor 100. This data bus 180 may be, for example, an ahb Bus or an AXI Bus.

When the first application 330 is executed, the first 3D graphics acceleration module 110 performs a function of processing data related to 3D graphics of the first application as first 3D graphics data. The first 3D graphics data processed by the first 3D graphics acceleration module 110 is stored in the first frame buffer 310. The first 3D graphics acceleration module 110 performs a function of processing graphics in embedded and mobile devices such as mobile phones, PMPs, and navigation. The first 3D graphics acceleration module 110 may support OpenGL / ES, Microsoft's DirectX, Direct3D, and the like, which are serviced by an application processor embedded in a mobile communication terminal.

The graphics acceleration module is a graphic display board with a built-in stereoscopic image processing function. 3D graphics acceleration module is not essential in two-dimensional graphics currently displayed in portable terminals. However, in games, graphics using 3D tend to increase, and when creating image data, the Z axis is added and processed based on the XY axis. When the 3D graphics data generated through such processing is processed by the acceleration module or the central processing unit (CPU), the motion of the image is very slow. Therefore, a 3D graphics acceleration module having a 3D image dedicated processing function has emerged.

The first display controller 150 transmits the first 3D graphic data VIN stored in the first frame buffer 310 to the multi-graphics accelerator 200.

The multi graphics accelerator interface 170 interfaces with the multi graphics accelerator 200.

The multi-graphics accelerator 200 processes the second 3D graphics data associated with the 3D graphics of the second application 350, overlays the first 3D graphics data and the second 3D graphics data with the multi 3D graphics data, and multi- 3D graphics. It performs a function to allow data to be displayed via the display 400.

More specifically, the multi-graphics accelerator 200 may include a second 3D graphics acceleration module 210, a second frame buffer 230 and a second display controller 250.

When the second application 350 is executed, the second 3D graphic acceleration module 210 performs a function of processing the second 3D graphic data. The second 3D graphics acceleration module 210 interfaces with the multi-graphics accelerator interface 170 to process data related to 3D graphics of the second application as second 3D graphics data according to the execution of the second application 350. It performs the function.

The second frame buffer 230 stores the second 3D graphic data processed by the second 3D graphic acceleration module 210 and provides the second 3D graphic data to the second display controller 250.

The second display controller 250 performs a function of overlaying the first 3D graphic data and the second 3D graphic data to generate the multi 3D graphic data. That is, when the first application 330 is executed, the first 3D graphics data processed by the first 3D graphics acceleration module 110 is stored in the first frame buffer 310 and then the first display controller 150. ) To the second display controller 250. When the second application 350 is executed, the second 3D graphic data processed by the second 3D graphic acceleration module 210 is stored in the second frame buffer 230 and then the second display controller 250. Is sent to. Then, the second display controller 250 overlays the first 3D graphic data and the second 3D graphic data to process the multi 3D graphic data to be displayed on the display 400.

In order to overlay the two data according to the prior art, the clocks do not coincide exactly with each other between the overlaying data, and therefore, the clocks must first be matched. Therefore, in the related art, data to be overlaid (corresponding to "first 3D graphic data" of the present invention) must first be read into memory (corresponding to "second frame buffer" of the present invention) and then read again according to output timing. However, in this case, since the data to be overlayed must be continuously written and read into the memory, it takes up a large part of the memory bandwidth, which is connected to the performance degradation of the graphics acceleration module, which becomes a problem. To solve this problem, the present invention outputs the second 3D graphic data stored in the second frame buffer to be synchronized with the clock of the first 3D graphic data, which is the data to be overlaid, and writes and reads the data to be overlaid in memory. There is no need to do this so that the performance of the graphics acceleration module is not degraded.

The second display controller 250 may overlay the first 3D graphic data and the second 3D graphic data by using any one of alpha blending, color masking, clipping, and transparency to process the multi 3D graphic data.

In order to overlay the first 3D graphic data and the second 3D graphic data, the second display controller 250 receives a control signal from the application processor 100, as shown in FIG. 3, a vertical signal VSYNC, horizontally. The signal HSYNC, the data enable signal DE, and the clock signal CLK may be provided. The second display controller 250 may perform overlay according to the vertical signal, the horizontal signal, and the data enable signal. The vertical signal VSYNC and the horizontal signal HSYNC may be activated at a low level. In FIG. 3, the vertical signal VSYNC and the horizontal signal HSYNC are activated at a low level. However, the vertical signal VSYNC and the horizontal signal HSYNC may be activated at a high level.

When overlaying the first 3D graphic data and the second 3D graphic data, when overlaying with N layers, the 3 + N-1 clock CLK may be delayed. A layer is used to perform an image in Photoshop, etc., and is used to implement various images by overlapping, adjusting transparency, or applying a style in the form of a transparent film, as shown in FIG. For example, when overlaid with four layers, there may be a 6 clock delay (CLK). That is, overlay is performed when the data enable signal DE is activated. First, the timing instability is solved by retiming (A). Retiming is performed to eliminate timing instability caused by PAD delays because data is input through the PAD. This retiming can be done by latching to the inverting clock of the clock CLK and then latching the result back to the clock. The falling edge of the clock is the most stable and therefore the inverting clock. It can be latched. After retiming, a read request is generated to access the second frame buffer (B), and the valid data for the read request is latched (C). The overlay is processed step by step between each layer. The first overlay is performed between two layers having lower priority (D), and the second overlay is performed between the first overlay result and the next higher layer (E). Next, a third overlay is performed between the previous overlay, the second overlay result, and the top layer (F). While performing the overlay as described above, it is delayed by a clock corresponding to (A) to (F).

Such a graphic acceleration system according to an embodiment of the present invention may operate in an RGB interface mode.

6 illustrates a graphics acceleration method for displaying multiple 3D graphics with a single application processor in accordance with an embodiment of the invention.

First, the application processor 100 performs a first application driving step S100 of driving the first application 330 stored in the memory 300.

Next, the application processor 100 performs a first 3D graphic data processing step S200 of processing graphic data related to the first application as first 3D graphic data.

The first 3D graphic data processing step (S200) may include processing, by the application processor 100, data about 3D graphics of the first application into first 3D graphic data according to driving of the first application 330. Storing the 3D graphic data and transmitting the first 3D graphic data to the multi-graphics accelerator 200 according to a control signal.

The application processor 100 may perform a second application driving step S300 for driving the second application 350 stored in the memory 300.

Next, the multi-graphics accelerator 200 may perform a second 3D graphic data processing step S400 of processing second 3D graphic data related to the second application 350.

Meanwhile, the first application driving step S100 and the second application driving step S300 are not necessarily limited to the above order and may be simultaneously performed.

Next, the multi-graphics accelerator 200 receives the first 3D graphic data processed in the first 3D graphic processing step S200, and the second 3D graphic data and the second 3D graphic processing step S400. 2 performs a multi- 3D graphics processing step (S500) of overlaying the 3D graphics data. In the multi 3D graphic data processing step (S500), the multi graphic accelerator 200 may control a vertical signal VSYNC, a horizontal signal HSYNC, a data enable signal DE, and a clock signal CLK as control signals. 100). The first 3D graphic data and the second 3D graphic data are overlaid according to the vertical signal, the horizontal signal, and the data enable signal.

On the other hand, the graphic acceleration method according to an embodiment of the present invention, after the multi-3D graphics data processing step (S500), the display step of displaying the multi- 3D graphics data overlaid by the multi-graphics accelerator 200 through the display ( S600) may be further performed.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications, changes, etc. fall within the scope of the claims Should be seen.

100: application processor
110: first 3D graphics acceleration module
130: memory interface
150: first display controller
170: multi graphics accelerator interface
190 CPU
200: multi graphics accelerator
210: second 3D graphics acceleration module
230: second frame buffer
250: second display controller
300: memory
310: first frame buffer
330: First application
350: second application
400: Displayer

Claims (13)

An application processor incorporating a first 3D graphics acceleration module configured to process data relating to 3D graphics of the first application as first 3D graphics data when the first application is executed;
A memory including a first frame buffer for storing the first 3D graphics data, the first application and a second application; And
And a multi-graphics acceleration device including a second 3D graphics acceleration module configured to process data regarding 3D graphics of the second application as second 3D graphics data when the second application is executed.
The multi-graphics accelerator, displays the multi- 3D graphics data by overlaying the first 3D graphics data and the second 3D graphics data,
The application processor may include a CPU controlling the application processor; A data bus that is a data transmission path from the application processor; A memory interface that interfaces with the memory; A multi-graphics accelerator interface for performing an interface with the multi-graphics accelerator; And a first display controller configured to transmit the first 3D graphics data stored in the first frame buffer to the multi-graphics accelerator. 2. .
delete The method of claim 1, wherein the multi-graphics accelerator,
A second frame buffer for storing the second 3D graphic data and providing the second 3D graphic data; And
And a second display controller configured to overlay the first 3D graphic data and the second 3D graphic data to generate the multi 3D graphic data, and to display the multi 3D graphic with a single application processor. system.
The method of claim 1, wherein the second display controller,
Receive a vertical signal (VSYNC), a horizontal signal (HSYNC), a data enable signal (DE) and a clock signal (CLK) as a control signal from the application processor,
And overlaying according to the vertical signal, the horizontal signal, and the data enable signal. A graphics acceleration system displaying multiple 3D graphics with a single application processor.
The method of claim 4, wherein the multi 3D graphic data,
When overlaying the first 3D graphic data and the second 3D graphic data, overlaying with N layers results in a 3 + N-1 clock (CLK) delay. Graphics acceleration system.
The method of claim 1, wherein the second display controller,
Multi 3D with a single application processor, characterized by overlaying the first 3D graphics data and the second 3D graphics data by any one of alpha blending, color masking, clipping, and transparency to process the multi 3D graphics data. Graphics acceleration system for displaying graphics.
The method of claim 1, wherein the data bus,
Graphics acceleration system for displaying multiple 3D graphics with a single application processor, characterized as ahb Bus or AXI Bus.
The method of claim 1, wherein the CPU,
A graphics acceleration system for displaying multiple 3D graphics with a single application processor, characterized by an ARM core.
The method of claim 1, wherein the graphic acceleration system,
A graphics acceleration system for displaying multiple 3D graphics with a single application processor, operating in RGB interface mode.
A first application driving step of the application processor driving the first application stored in the memory;
A first 3D graphic data processing step of the application processor processing first 3D graphic data associated with the first application;
A second application driving step of the application processor driving the second application stored in the memory;
A second 3D graphic data processing step of the multi graphics accelerator processing second 3D graphic data associated with the second application; And
The multi-graphics accelerator receiving the first 3D graphic data, and multi-dimensional 3D graphic data processing step of overlaying the first 3D graphic data and the second 3D graphic data with multi 3D graphic data;
The processing of the first 3D graphics data may include: processing, by the application processor, data about 3D graphics of the first application into the first 3D graphics data according to driving of the first application; Storing the first 3D graphic data; And transmitting the first 3D graphics data to the multi-graphics accelerator in accordance with a control signal.
delete The method of claim 10, wherein the processing of the multi 3D graphic data comprises:
Receiving, by the multi-graphics accelerator, a vertical signal (VSYNC), a horizontal signal (HSYNC), a data enable signal (DE) and a clock signal (CLK) from the application processor as a control signal; And
And performing an overlay according to the vertical signal, the horizontal signal, and the data enable signal. 2.
The method of claim 10, wherein after the multi-3D graphic data processing step,
And displaying the multi 3D graphic data through a display. The method of claim 2, further comprising displaying the multi 3D graphic data with a single application processor.

Images