KR100972903B1 - Bitline equalization signal driving circuit of semiconductor memory device - Google Patents

Abstract

The present invention relates to a bit line equalization signal driving circuit of a semiconductor memory device, and more particularly, to generate a bit line equalization voltage VBLEQ by pumping an external power supply voltage VEXT to stably stabilize a bit line equalization signal BLEQ for equalizing bit line pairs. Driven by technology. To this end, the present invention is characterized in that it comprises a bit line equalization driving unit for driving the bit line equalization voltage VBLEQ by pumping the external power supply voltage VEXT to stabilize and output the bit line equalization signal.

Description

Bitline equalization signal driving circuit of semiconductor memory device

1 is a diagram illustrating an equalization signal driving circuit of a semiconductor memory device according to the related art.

2 is an embodiment of an equalization signal driving circuit of a semiconductor memory device according to the present invention;

3 is a detailed circuit diagram of a bit line equalization signal driver according to the present invention;

4 is an operation timing diagram of a bit line equalization signal driver according to the present invention;

The present invention relates to a bit line equalization signal driving circuit of a semiconductor memory device. More particularly, the bit line equalization voltage VBLEQ is set to an independent level by pumping an external power supply voltage VEXT to stably drive the bit line equalization signal BLEQ. This technology makes it possible to equalize the bit line pairs quickly and stably.

The bit line pair of the semiconductor memory device is for sensing data of a memory cell or transferring data to be written to the memory cell.

1 is a conceptual diagram illustrating a main part of a semiconductor memory device according to the prior art. Here, only the bit line equalization unit 11 and the bit line equalization signal driver 20 in the memory block 10 are shown.

The bit line equalizer 11 precharges the bit line pair BL, / BL to the bit line precharge voltage VBLP level after the write operation or the read operation, and the bit line pair BL, /, Equalization transistor EQTR1 for equalizing BL is provided. At this time, the bit line precharge voltage VBLP is applied to the common nodes of the precharge transistors PTR1 and PTR2. Here, all the transistors PTR1, PTR2, and EQTR1 are composed of NMOS transistors.

When the bit line equalization signal BLEQ of the bit line equalization unit 11 reaches the external power supply voltage VEXT level, the transistors PTR1, PTR2, and EQTR1 are turned on so that the potentials of the bit line pairs BL and / BL are equalized to the bit line precharge voltage VBLP level. . In this case, the external power supply voltage VEXT is shared and used in a peripheral circuit of the semiconductor memory device.

The bit line equalization signal driver 20 outputs the bit line equalization signal BLEQ using the external power supply voltage VEXT. However, when the external power supply voltage VEXT is less than or equal to a certain voltage, it takes a long time to equalize the bit line pairs.

As described above, it takes a long time to equalize the bit line pairs due to the instability of the external power supply voltage VEXT, and there is a problem of inhibiting the speed of the semiconductor memory device.

An object of the present invention for solving the above problems is to equalize the bit line pair quickly and stably by generating the bit line equalization signal by using the constant voltage pumped independently of the external power supply voltage VEXT.

The present invention for achieving the above object is a bit line equalization signal driving circuit of a semiconductor memory device for driving a bit line equalization signal for controlling the bit line equalization circuit for equalizing the bit line, by pumping an external power supply voltage constant voltage And a bit line equalization signal generating means for generating the above bit line equalization voltage and supplying a bit line equalization signal having a level of bit line equalization voltage to the bit line equalization circuit.
The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

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Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a conceptual diagram illustrating a main part of a semiconductor memory device according to the present invention. Here, only the bit line equalization unit 31 and the bit line equalization signal driver 40 in the memory block 30 are shown.

The bit line equalization unit 31 precharges the bit line pairs BL and / BL to the bit line precharge voltage VBLP level after the write or read operation, and the bit line equalization transistors PTR3 and PTR4 and the bit line pairs BL, / An equalization transistor EQTR2 equalizes the BL. At this time, the bit line precharge voltage VBLP is applied to the common node of the precharge transistors PTR1 and PTR2. Here, all the transistor bit lines PTR3, PTR4 and EQTR2 are composed of NMOS transistors.                     

When the bit line equalization signal BLEQ becomes high level, the bit line equalizer 31 turns on all transistors PTR3, PTR4, and EQTR2 so that the potentials of the bit line pairs BL and / BL are bit line precharge voltages. Equalizes to VBLP level.

The bit line equalization signal driver 40 outputs the bit line equalization signal BLEQ using the bit line equalization voltage VBLEQ having the potential at which the external power supply voltage VEXT is pumped. At this time, the bit line equalization voltage VBLEQ is preferably set to 1.9V to 3.6V.

3 is a detailed circuit diagram of the bit line equalization signal driving circuit of FIG. 2.

The bit line equalization signal driver 40 is composed of NMOS transistors NM1, NM2, NM3, pumping capacitor CP, and load capacitor CL.

The NMOS transistors NM1 and NM2 have an external power supply voltage VEXT applied to the drain, the drain and the gate are commonly connected, and the source is connected to the pumping node N1 and the output node N2, respectively. The NMOS transistor NM3 is connected between the pumping node N1 and the output node N2, and a gate is connected to the pumping node N1.

The pumping capacitor CP has one end connected to the pumping node N1, the other end connected to the pulse input terminal, and when the pulse P is input through the pulse input terminal, the pumping capacitor CP increases the potential of the pumping node N1. One end of the load capacitor CL is connected to the output node N2, the other end is connected to the ground voltage VSS, and is charged by receiving the potential of the pumping node N1 through the NMOS transistor NM3. Here, the capacity of the load capacitor CL is preferably designed to be much larger than that of the pumping capacitor CP.

4 is an operation timing diagram of the bit line equalization signal driver shown in FIG. 3.                     

First, pulse P is generated with a periodic clock having an external power supply voltage VEXT level.

When the potential of the pumping node N1 is initially maintained at a constant potential (VEXT-VTN), and the pulse P is input to the pumping capacitor CP, the pumping node N1 is boosted by aVEXT (a is the boost ratio) and the specific potential (1 + a) It rises to VEXT-VTN and drops to the initial potential (VEXT-VTN) when pulse P input is interrupted. That is, the potential of the pumping node N1 repeats rising and falling in accordance with the input of the pulse P.

The potential of the output node N2 is initially maintained at a constant potential (VEXT-VTN), and when the pulse P is input, the potential of the pumped node N1 is received and the load capacitor CL is charged, so that the potential of the output node N2 is equal to the charging amount. Increases. The potential of the output node N2 rises to the highest highest potential (1 + a) VEXT-2VTN level.

Hereinafter, operations of the bit line equalization signal driver 40 will be described with reference to FIGS. 3 and 4.

When the pulse P is not input to the other end of the pumping capacitor CP, the potential of the nodes N1 and N2 is equal to the potential of the NMOS transistors NM1 and NM2 minus the threshold voltage of each NMOS transistor NM1 and NM2 by the external power supply voltage VEXT. The potential VEXT-VTN is maintained.

When the pulse P is input to the other end of the pumping capacitor CP, the pumping node N1 is boosted by aVEXT (a is the boost ratio) to become a specific potential (VEXT-VTN + aVEXT). As such, the potential of the pumping node N1 is pumped through the pumping capacitor CP to turn on the NMOS transistor NM3. Accordingly, when the potential of the pumping node N1 is transferred to the output node N2, the charge is charged to the load capacitor CL. At this time, since the capacity of the load capacitor CL is larger than the pumping capacitor CP, the charging amount of the output node N2 is small.

When the potential of the output node N2 rises through the pumping of the pumping capacitor CP and the potential difference between the pumping node N1 and the output node N2 becomes equal to or greater than the threshold voltage VTN of the NMOS transistor NM3, the NMOS transistor NM3 is turned off. As a result, charge charging of the load capacitor CL is stopped.

Thereafter, when the pulse P input is stopped, the potential of the pumping node N1 falls below the initial potential VEXT-VTN. However, the NMOS transistor NM1 immediately maintains the initial potential (VEXT-VTN).

Thereafter, each time the pulse P is applied, the potential of the output node N2 rises to reach the highest potential (1 + a) VEXT-2VTN level. Here, the highest potential (1 + a) VEXT-2VTN level is maintained in the form of charge stored in the load capacitor CL, and this level drops when charge loss occurs. When such a charge loss occurs, the NMOS transistor NM3 is turned on to recover the charge loss of the output node N2. The potential of this output node N2 is used as the bit line equalization voltage VBLEQ.

Therefore, when the precharge command is input to the memory block 30, the bit line equalization voltage VBLEQ is provided to the bit line equalization unit 31 to equalize the bit line pairs BL and / BL.

In this way, the bit line equalization signal BLEQ for pumping the external power voltage VEXT and driving at the pumped voltage is provided to the bit line equalizer 31 without using the external power voltage VEXT commonly used in the memory block 30 as it is. This makes it possible to equalize the bit line pairs BL and / BL quickly and stably.

As described above, the present invention has the effect of equalizing the bit line pairs quickly and stably by driving the bit line equalization signal by generating a bit line equalization voltage of a predetermined level or more by pumping an external power supply voltage.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

Claims (5)

In a bit line equalization signal driving circuit of a semiconductor memory device for driving a bit line equalization signal for controlling a bit line equalization circuit for equalizing a bit line, And a bit line equalization signal generating means for pumping an external power supply voltage to generate a bit line equalization voltage of a predetermined potential or more and supplying the bit line equalization signal having a level of the bit line equalization voltage to the bit line equalization circuit. A bit line equalization signal driving circuit of a semiconductor memory device. The method of claim 1, wherein the bit line equalization signal generating means, First and second switching means which are driven by the external power supply voltage to precharge a potential of a pumping node and an output node to a constant potential; Pumping means for boosting the potential of the pumping node by a predetermined pulse signal; Third switching means for transferring a pumping potential of the pumping node to the output node; And Charging means for charging a potential of the output node; And a bit line equalization signal driving circuit of the semiconductor memory device. The method of claim 2, wherein the pumping means and the charging means A bit line equalization signal driving circuit of a semiconductor memory device, characterized in that it is a capacitor. 4. The bit line equalization signal driving circuit of claim 3, wherein the capacitance of the charging means is larger than that of the pumping means. 2. The bit line equalization signal driving circuit of claim 1, wherein the bit line equalization voltage is set in a range of 1.9V to 3.6V.

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