KR100953648B1 - Transmitting/receiving system and method of processing data - Google Patents

Abstract

An improved digital transmit / receive system is provided. The receiving system is provided with a sequence generation unit therein that informs that it is an additional data symbol and generates a sequence predefined by the transmitting side and included in the additional data. The receiving system further includes an MPEG data processing unit which processes the reverse sequence with the transmitting side by using the internally generated sequence and a demultiplexer which demultiplexes the output data of the MPEG data processing unit into MPEG data and additional data. . The receiving system includes an additional data processor for processing the additional data output from the demultiplexer in reverse order with the transmitting side to restore the original additional data. By using the predefined sequence, the slicer prediction, the decoding process, and the symbol determination of the additional data are more accurately performed, thereby improving the performance of the receiving system.

Send system, receive system, sequence

Description

Transmitting / receiving system and method of processing data}

The present invention relates to a receiving system that is more resistant to ghosting and noise of a channel than conventional receiving systems.

In the United States, ATSC 8T-VSB (8Trellis-Vestigial Sideband) transmission system was adopted as a standard in 1995, and broadcasted since the second half of 1998. In Korea, ATSC 8T-VSB transmission system, which is identical to the American method, is used as the standard. The test broadcast was started in May 1995, and the test broadcast system was switched to August 31, 2000.

1 shows a conventional ATSC 8T-VSB transmission system.

In Fig. 1, the data randomizer 1 randomizes data, and the Reed Solomon encoder 2 adds 20 bytes of parity code into the data by Reed-Solomon coding the data. The data interleaver 3 interleaves the data, and the trellis encoder 4 converts the data from bytes into symbols and then trellis-codes the data. The multiplexer 5 multiplexes the symbol string and the synchronization signals, the pilot inserter 6 adds the pilot signal to the symbol string, and the VSB modulator 7 modulates the symbol string into an 8T-VSB signal. The RF converter 8 converts the baseband signal into an RF band signal which is transmitted via the antenna 9 towards the receiving system.

Looking closely at the trellis encoder 4, the bytes output from the data interleaver 3 are converted to symbols and then a plurality of identical trellis encoders and precoders 32-1, 32-2, ... .32-12) one symbol at a time.

Figure 2 shows a conventional ATSC 8T-VSB receiving system.

In FIG. 2, demodulator 11 converts a signal of the RF band received through antenna 10 into a baseband signal, and a synchronization and timing recoverer (not shown) is a segment sync signal, a field sync signal, and a symbol. Restore the timing. Meanwhile, the comb filter 12 removes the NTSC interference signal, and the channel equalizer 13 uses the slicer predictor 14 to correct the distorted channel. Phase reconstructor 15 reconstructs the phase of the received signal, and trellis decoder 16 performs Viterbi decoding on the reconstructed signal. The data deinterleaver 17 performs the reverse operation of the data interleaver 3 of the transmission system, and the Reed Solomon decoder 18 decodes the Reed Solomon encoded signal. On the other hand, the data de-randomizer 19 performs the reverse operation of the data-randomizer 1 in the transmission system.

As described above, the conventional ATSC 8T-VSB receiver only receives MPEG data and cannot receive additional data. Therefore, it is necessary to develop a reception system capable of receiving both MPEG video and audio data as well as additional data.

In addition, in the conventional receiving system, the prediction reliability of the slicer predictor that predicts a set of signal levels under a noisy or ghosting channel is greatly degraded. Therefore, there is a disadvantage in that the performance of the receiving system is greatly reduced.

An object of the present invention is to provide a digital receiving system capable of receiving both MPEG data and additional data.

Another object of the present invention is to provide a digital receiving system having better performance against noise and ghosting of a channel than a conventional ATSC 8T-VSB receiver.

In order to achieve the above object, the receiving system uses a predefined sequence included in the additional data transmitted by the digital broadcasting transmission system.

According to one aspect of the present invention, a reception system for receiving and decoding an input signal including an MPEG data segment and an additional data segment transmitted from a transmission system is configured to decode a symbol corresponding to the additional data segment, thereby performing the decoding. A sequence generator for generating a predefined sequence encoded in the; A data processor which processes the data received from the transmission system in a reverse order to the data processing order of the transmission system using the generated sequence; A demultiplexer for demultiplexing the data output from the data processing unit into an MPEG data segment and an additional data segment; And an additional data processor for processing the additional data segment output from the demultiplexer in the reverse order of the additional data processing order of the transmission system and restoring the original additional data.

The slicer predictor of the data processor increases prediction reliability by performing prediction using the predefined sequence included in the additional data.

The trellis decoder of the data processor increases decoding performance by performing decoding using the predefined sequence included in the additional data.

The channel equalizer and the phase decompressor of the data processor determine slicers having further distances between signals using the predefined sequence, and determine the symbols of the additional data using the slicers. Therefore, errors in signal determination can be reduced.

According to the receiving system of the present invention, the following effects can be obtained.

First, since the receiving system includes components that can process MPEG data and additional data together, both the MPEG data and the additional data can be received.

Secondly, a sequence generator for generating a predefined sequence as an input signal of a trellis encoder of a transmission system is provided in the reception system, so that the reception system can be compared with respect to a ghost signal and a noise signal of a channel when compared with a conventional ATSC 8T-VSB receiver. The reception performance can be greatly improved. In particular, the performance of the slicer predictor and trellis decoder in the receiving system is greatly improved.

Third, the receiving system may use slicers having a farther distance between signals as compared to conventional slicers in an internal channel equalizer and a phase recoverer by using a predefined sequence in signing in the transmitting system. Therefore, errors in signal determination can be minimized.

Hereinafter, embodiments of the present invention will be described in detail.

3 is a diagram showing the configuration of a transmission system according to the present invention. The system of FIG. 3 is compatible with the conventional ATSC 8T-VSB system and can transmit MPEG data as well as additional data.

The system of FIG. 3 includes a conventional ATSC 8T-VSB transmission system 25, a mux 24 for multiplexing the MPEG data and additional data, and an MPEG in a segment of the additional data to maintain compatibility with the conventional ATSC 8T-VSB receiver. MPEG header inserter 23 for inserting a header, null sequence inserter 22 for inserting a predefined sequence, and interleaver 21 for interleaving the additional data in order to improve performance against burst noise of the additional data. And a Reed Solomon encoder 20 for reed Solomon encoding the additional data.

FIG. 4 is a diagram for explaining a process of inserting a predetermined sequence into additional data by the null sequence insertion unit 22 of FIG.

In order to receive the additional data well at the receiver side, a predetermined sequence is inserted into at least part of the additional data and transmitted. The predetermined sequence has a form in which 1 and 0 are arranged in a predetermined order. At this time, the number of 1 and 0 should be the same on average. An example of the predetermined sequence is an output of a pseudo random value generator in which an initial value is predetermined.

The performance of receiving the additional data at the receiver is determined by how much the predetermined sequence is inserted into the additional data. In other words, the more the predetermined sequence is inserted into the additional data, the stronger reception performance of the receiving system is obtained.

When one bit of additional data is input, the null sequence insertion unit 22 inserts one bit of null bits and outputs two bits as shown in FIG. 4. The null bits are randomized in the 8T-VSB transmission system of FIG. 3 and then Reedsolomon encoded. This encoded side data is interleaved and then applied to one input d0 of a trellis encoder (not shown). Here, the input signal d0 corresponds to a lower bit of two bits input to the trellis encoder.

In FIG. 3, since the configuration and operation of the 8T-VSB transmission system have already been described with reference to FIG. 1, a detailed description thereof will be omitted. On the other hand, the receiving system includes a component for generating the predetermined sequence corresponding to the input signal d0 of the trellis encoder, and the predetermined sequence generated through the component is used to generate the predetermined sequence of the receiving system. Used to improve performance. The null sequence shown in Fig. 4 shows a simple example, and any other sequence may be used instead of this null sequence.

On the other hand, as described above, since the occurrence probability of the eight levels should be the same for compatibility with the 8T-VSB transmission system, the existence probability of 0 and 1 in the sequence corresponding to the input bit (d0) of the trellis encoder. The probability of existence of must be the same.

FIG. 5 is a diagram showing the configuration of a trellis encoder and a precoder used in the ATSC 8T-VSB transmission system 25 of FIG.

FIG. 6 shows a state transition diagram of the trellis encoder shown in FIG.

In FIG. 5, the trellis encoder 28 and the precoder 27 output three output bits C0, C1, C2 for two input bits d0, d1. The non-explained number 29 is an 8T-VSB modulator, and a modulation value Z corresponding to the three output bits C0, C1, and C2 output from the trellis encoder 28 and the precoder 27. ) In Fig. 5, 27a and 28b indicate adders, and 27b, 28a, and 28c indicate registers.

As shown in Fig. 5, the input bit d1 is precoded by the precoder 27 to become an output bit C2, and the input bit d0 is replaced with an output bit C1 as it is. On the other hand, the output bit C0 is determined by the value stored in the register 28c of the trellis encoder 28. The signal level is determined according to the output bit strings C0, C1, C2 of the trellis encoder 28 and the precoder 27, and the entire set of signal levels having the number of levels 8 (-7, -5). , -3, -1, +1, +3, +5, +7 are two signal level sets (-7, -3, +1) each having a number of 4 levels according to the output bit C0. , +5) (-5, -1, + 3, + 7).

In other words, two sets of signal levels (-7, -3, + 1, + 5) having a number of four by the value stored in the register 28c (-5, -1, + 3, + 7) One is selected. Thus, if the receiving system can predict the value currently stored in the register 28c in the trellis encoder, then the output signal level of the trellis encoder 28 is which of the two signal level sets. We can predict whether Using this prediction information, a four-level slicer having twice the distance between levels can be used instead of the ordinary eight-level slicer.

The Viterbi algorithm is used in the trellis decoder of the receiving system to predict the value stored in the register 28c in the trellis encoder 28. On the other hand, if the prediction of the set of signal levels is incorrect, the error of the determination value may be greater. Therefore, the conventional 8T-VSB receiving system uses a four-level slicer if the reliability of the prediction value is high, and uses the original eight-level slicer if the reliability of the prediction value is low to minimize the determination error as described above. As described above, the present invention greatly improves the reliability of the prediction value by using the predefined sequence transmitted by the transmission system such as a data broadcasting system.

The slicer predictor and trellis decoder used in the ATSC 8T-VSB receiving system both use a Viterbi algorithm. The Viterbi algorithm is an algorithm for predicting the most probable state transition (or path) among the state transitions (or paths) of the trellis encoder over time.

The probability that the state value of the trellis encoder at time k is Si is proportional to the cumulative matrix Mi of the state value Si as shown in Equation (1) below.

...........(1)P (Si) ∝

...........(One)

The cumulative matrix up to the time k can be expressed as Equation 2 below. In Equation (2) below, yi is a received 8T-VSB signal value, and xj is a level value of the 8T-VSB signal assigned to a branch connecting states in the state transition diagram of FIG. .

...........(2)M _i =

...........(2)

As shown in the state transition diagram of Fig. 6, since the input bits of the trellis encoder are two bits, the number of branches connected to each state is four. The Viterbi algorithm selects and stores a path having the smallest cumulative matrix value among four paths connected to each state S1, S2, S3, and S4. This part of the process is called an ACS (accumulate / compare / select) part. In this way, the state having the highest probability at the time k is determined by selecting the smallest matrix value among the matrices selected and stored in each state S1, S2, S3, S4.

As described above, the VSB transmission system for digital television broadcasting shown in Fig. 3 inserts the null sequence into the additional data and stores the predefined sequence through the bit d0 input to the trellis encoder. Send to receiving system. On the other hand, if the predefined sequence is used on the receiving system side, the performance of the Viterbi algorithm can be greatly improved.

As an example, consider the case where bit d0 of the predefined sequence transmitted from the transmission system at time k is one. In this case, it is impossible for the branches whose d1d0 is 00 and 10 to be determined as the most probable state among the four branches connected to the states S1, S2, S3, and S4. Equally, consider the case where bit d1 of the predefined sequence is zero. In this case, it is impossible for the branches having d1d0 of 01 and 11 to be determined as the most probable state among the four branches connected to the states S1, S2, S3, and S4. As a result, the ACS unit can reduce the number of branches from four to two with the Viterbi algorithm by using the predefined sequence. That is, in the receiving system, the performance of the trellis decoder and the reliability of the slicer predictor can be greatly improved.

The channel equalizer and phase recoverer of the ATSC 8T-VSB receiving system shown in FIG. 2 use a slicer and a slicer predictor, respectively. The slicer predictor used in the phase recoverer is usually included in the trellis decoder.

FIG. 7 is a diagram showing the configuration of a trellis encoder included in the ATSC 8T-VSB transmission system shown in FIG. The trellis encoder of Fig. 7 has twelve trellis encoders and precoders 32-1, 32-2, ... 32-12, an input terminal and the trellis encoder and precoders 32-. Multiplexer 30 connected between the input terminals of 1, 32-2, ... 32-12, and the output terminal and the trellis encoder and precoders 32-1, 32-2, ... And a multiplexer 31 connected between the output terminals of .32-12).

8 is a diagram showing the configuration of a digital VSB receiving system according to the present invention. The reception system shown in Fig. 8 utilizes the predefined sequence as described above to improve its reception performance.

In FIG. 8, the VSB receiving system according to the present invention uses a sequence generator 46 for indicating an additional data symbol and generating a predefined sequence included in the additional data, and the data received from the transmission system. MPEG data processing unit 100 for processing in reverse order with the transmission system, demultiplexer 56 for demultiplexing the output data of the MPEG data processing unit 100 into MPEG data and additional data, and the demultiplexer 56. And an additional data processor 200 which processes the additional data outputted from the reverse order with the transmission system to obtain original additional data.

As shown in Fig. 8, the MPEG data processing unit 100 includes a demodulator 47, a comb filter 48, a channel equalizer 49, a slicer predictor 50, a phase decompressor 51, and a trellis decoder. 52, a first data deinterleaver 53, a first Reed Solomon decoder 54, and a data derandomizer 55. The additional data processor 200 includes an MPEG header remover 57, a null sequence remover 58, a second data deinterleaver 59, and a second Reed Solomon decoder 60.

The demodulator 47 converts the RF band signal into a baseband signal, and then the sync and timing recoverer (not shown) recovers the segment sync signal, the field sync signal, and the symbol timing. The comb filter 48 removes the NTSC interference signal, and the channel equalizer 49 corrects the distorted channel using the slicer predictor 50. The phase recoverer 51 recovers the phase of MPEG data, and the trellis decoder 52 performs Viterbi decoding by using the generated sequence and the Viterbi algorithm. Here, the channel equalizer 49, the slicer predictor 50, the phase decompressor 51, and the trellis decoder 52 use the sequence generated from the sequence generator 46 to generate the MPEG. Decrypt the data. The first data deinterleaver 53 performs a reverse operation on the data interleaver of the ATSC 8T-VSB transmission system, and the first Reed Solomon decoder 54 is a Reed Solomon-coded signal in the ATSC 8T-VSB transmission system. Decrypt again. On the other hand, the data derandomizer 55 performs a reverse operation on the data randomizer of the transmission system.

On the other hand, the sequence generator 46 indicates whether or not a symbol received from the transmission system is a symbol corresponding to the additional data, and generates the same predefined sequence inserted into the additional data and transmitted. As described above, the channel equalizer 49, the slicer predictor 50, the phase decompressor 51, and the trellis decoder 52 each use their own predefined sequence information. Improve performance In this case, the components using the predefined sequence are used by delaying the sequence information in consideration of the data processing delay of the previous components.

The demultiplexer 56 demultiplexes the data input from the MPEG data processing unit 100 into an additional data segment and an MPEG data segment using the multiplexing information recovered from the field synchronization signal. The first Reed Solomon decoder 54 described above removes only 20 bytes of parity bits added by the Reed Solomon encoder of the transmission system without performing Reed Solomon decoding on the additional data segment. If the noise of the channel is severe, more error occurs in the parity byte of the ATSC Reed Solomon code than the additional data. The reason is that there is no predefined sequence in the parity byte of the ATSC Reed Solomon code, so there is no gain in the trellis decoder 52. The reason that the first Reed Solomon decoder 54 does not perform Reed Solomon decoding on the additional data segment is because the first Reed Solomon decoder 54 when an error exceeding 10 bytes occurs on the additional data segment. Is likely to perform incorrect error correction.

Meanwhile, the additional data segment outputted through the demultiplexer 56 is first input to the MPEG header remover 57, and the MPEG header remover 57 removes a 3-byte MPEG header from the additional data segment. do. The MPEG header was inserted when the additional data was transmitted in the ATSC segment format by the transmission system.

Subsequently, the null sequence remover 58 removes the null sequence that was inserted in the null sequence inserter of the transmission system from the additional data segment. Then, the second deinterleaver 59 performs a reverse operation on the interleaving process in the transmission system on the additional data segment. If the interleaver is omitted in the transmission system, the reception system also does not include the second deinterleaver 59. The second Reed Solomon decoder 60 decodes a Reed Solomon code for the additional data.

On the other hand, the phase recoverer of the conventional ATSC 8T-VSB receiving system selectively uses an internal slicer with the help of the slicer predictor built in the trellis decoder. However, the phase recoverer of the reception system according to the present invention is different from the conventional reception system in that the slicer is predicted and selected using the predefined sequence.

Since the predefined sequence depends only on the symbols of the additional data, the receiving system must be able to recognize which symbol is the symbol of the additional data, and if the predefined sequence sent from the transmission system is zero or not, Must be able to recognize 1 There are two main methods for recognizing the additional data symbol and the information about the predefined sequence in the receiving system. According to the first method, symbols corresponding to one field of an ATSC data frame are previously stored in a read only memory (ROM). For reference, since the data randomizer included in the ATSC 8T-VSB transmission system is initialized in synchronization with the field synchronization signal, the period of the predefined sequence also becomes a field unit. However, this first method has a disadvantage in that a large amount of memory is required because the predefined sequence must be stored in field units according to the multiplexing scheme in the transmission system. According to a second method, the receiving system has its own transmitter which generates the predefined sequence.

9 is a block diagram showing the detailed configuration of the sequence generator 46 in the receiving system of FIG. 8 according to the second method.

The sequence generator 46 of Fig. 9 includes a multiplexer 61, a modified randomizer 62, a dummy parity inserter 63, a data interleaver 64, and a trellis encoder 65. 9, an additional data dummy packet and an MPEG data dummy packet are input to the multiplexer 61. First, in the case of the MPEG data packet, 187 dummy bytes 0x00 are generated. In the case of the additional data packet, three dummy bytes 0x00 corresponding to the MPEG header bytes are generated, and 184 dummy bytes 0xAA corresponding to the additional data are generated.

These dummy bytes are multiplexed in the multiplexer 61 and then rendered through the modified randomizer 62. In this case, the modified randomizer 62 bitwisewise ANDs the pseudorandom byte and 0x55 generated intentionally, and then the result of the AND logic operation is multiplexed again to the multiplexer 61. Render by bitwise-wise with an input byte from the Exclusive OR operation.

Subsequently, the dummy parity insertion unit 63 inserts dummy bytes 0x00 corresponding to 20 parities added by the Reed Solomon encoder of the ATSC 8T-VSB into the randomized data. The output of the dummy parity insertion unit 63 is interleaved in the data interleaver 64. The interleaved dummy bytes are converted into symbols, and the converted symbols are input to the trellis coder 65. The detailed structure of the trellis coder 65 is shown in FIG. That is, the symbols are input to the twelve trellis encoder and precoders 32-1, 32-2, .... 32-12 of Figure 7, wherein the symbols are substantially the twelve trellis. The encoder and the precoders 32-1, 32-2, ..., 32-12 are output as they are, without being precoded and trellis coded. In this way, the finally output symbol consists of two bits d1d0. Herein, when the bit d1 is 1, the symbol is a symbol of the additional data, and when the bit d1 is 0, it is a symbol of the MPEG data. On the other hand, when the bit d1 is 1, the bit d0 corresponds to the predefined sequence that will be input to the trellis encoder of the transmission system. The sequence generator 46 operates in synchronization with the field synchronization signal restored by the receiving system.

  Fig. 10A is a diagram showing three kinds of slicers for MPEG data symbols used in the channel equalizer. Each slicer represents a level of a signal to be determined, and each slicer also performs a function of determining a signal that is closest in distance to the signal received from the transmission system. If the reliability of slicer prediction is low, slicer 1 having 8 levels is used. If the reliability of the slicer prediction is high, one of the slicer 2 and the slicer 3 is selected according to the predicted value of the register 28c of the trellis encoder 28 shown in FIG. If the predicted value of the register 28c is 0, the slicer 2 is selected. If the predicted value is 1, the slicer 3 is selected.

Fig. 10B is a diagram showing six kinds of slicers for additional data symbols. That is, when the symbols are symbols of the additional data, six slicers as shown in FIG. 10 (b) may be used using the bit d0 of the predefined sequence. First, the set of signal levels that can be transmitted from the transmission system when the sequence bit d0 is zero is (-7, -5, + 1, + 3). On the other hand, when the sequence bit (d0) is 1, the set of signal levels that can be transmitted from the transmission system is (-3, -1, +5, +7). Therefore, when the slicer predictor has low reliability, one of the slicer 4 and the slicer 5 is selected according to the value of the sequence bit d0.

Hereinafter, consider a case where the reliability of the slicer predictor is high. When the sequence bit d0 is 0, the slicer 4 may be divided into the two slicers 6 and 7 according to the value stored in the register 28c in the trellis encoder 28. That is, if the stored value of the register 28c is 0, the slicer 6 is selected. If the stored value of the register 28c is 1, the slicer 7 is selected. Meanwhile, when the sequence bit d0 is 1, the slicer 5 may be divided into the two slicers 8 and 9 according to the value stored in the register 28c in the trellis encoder 28. . That is, the slicer 8 is selected if the stored value of the register 28c is 0, and the slicer 9 is selected if the stored value of the register 28c is 1.

As described above, the slicers 6, 7, 8, and 9 of FIG. 10 (b) are twice as far between signals as compared with the conventional slicers 2 and 3 shown in FIG. Therefore, in the case of the additional data symbol, by using the predefined sequence, it is possible to use slicers having a farther distance between signals, and further minimize errors in signal determination.

11 is a block diagram showing the configuration of a channel equalizer of a receiving system using the predefined sequence. In FIG. 11, the channel equalizer adds a feed-forward filter 66, a feedback filter 67, an adder 68 that adds the outputs of the filters 66, 67, Nine slicers 69-1, 69-2, ... 69-9, multiplexer 70, and control unit 71 are included.

In Fig. 11, the input signal of the channel equalizer 49 is input to the feed forward filter 66, and the output signal of the feed forward filter 66 and the output signal of the feedback filter 67 are added to the adder. At 68 is added. The output signal of the adder 68 becomes the output signal of the channel equalizer 49. On the other hand, the output signal of the channel equalizer 68 is input to the nine slicers 69-1, 69-2, ... 69-9 in common, and each of the slicers 69-1, 69 -2, .... 69-9) determine the output signal.

The controller 71 controls the multiplexer 70 to select any one of the outputs of the slicers 69-1, 69-2,... 69-9, and the selected output is the feedback. It is input to the filter 67 and the control part 71. The controller 71 updates the filter coefficients of the feed forward filter 66 and the feedback filter 67 using the selected slicer output and the output of the channel equalizer 49.

On the other hand, the slicer predictor 50 of FIG. 8 inputs the output signal of the channel equalizer 49 and the output signal of the sequence generator 46 and uses the input signals to trellis in the transmission system. After predicting the values stored in the register 28c of the encoder encoder 28 and calculating the reliability of the predicted values, these values are transferred to the control unit 71 of the channel equalizer 49. On the other hand, the control unit 71 of the channel equalizer 49 is inserted into the additional data symbol and information on whether the symbol currently received from the sequence generator 46 corresponds to additional data or MPEG data. The predefined sequence d0 is provided. In addition, the control unit 71 receives the prediction value and the prediction reliability value from the slicer predictor 50, which have predicted the value stored in the register 28c of the trellis encoder 28 in the transmission system. As one of the outputs of the nine slicers (69-1, 69-2, ... 69-9) is selected.

1 is an ATSC 8T-VSB transmission system

Figure 2 is an ATSC 8T-VSB receiving system

3 is a VSB transmission system for digital television broadcasting according to the present invention.

4 is a diagram illustrating null sequence insertion

5 is a diagram showing the configuration of a trellis encoder and a precoder

6 is a state transition diagram of an ATSC 8T-VSB trellis encoder.

7 is a diagram showing the configuration of an ATSC 8T-VSB trellis encoder

8 is a digital VSB receiving system of the present invention.

9 is a diagram showing the configuration of the sequence generator of the present invention.

10A is a diagram showing slicers for an MPEG data symbol

10B is a diagram showing slicers for additional data symbols.

11 is a diagram showing the configuration of a channel equalizer of the present invention.

Explanation of symbols for the main parts of the drawings

46: sequence generator, 56: demultiplexer, 100: MPEG data processor, 200: additional data processor

Claims (10)

Receiving demodulation by receiving a broadcast signal multiplexed with first data having a first property and second data having a second property; Compensating for channel distortion generated in the demodulated broadcast signal; Trellis decoding the broadcast signal with the channel distortion compensated; Separating second data from the trellis decoded broadcast signal; And Performing error correction decoding on the separated second data to correct an error generated in the second data; The data processing method of the receiving system comprising a. The method of claim 1, And performing a deinterleaving on the separated second data and outputting the second corrected data for error correction decoding. delete delete The method of claim 1, And the second data is received by performing at least one more interleaving than the first data. A demodulator configured to receive and demodulate a broadcast signal multiplexed with first data having a first property and second data having a second property; An equalizer for compensating for channel distortion generated in the demodulated broadcast signal; A trellis decoder for trellis decoding the broadcast signal compensated for by the channel distortion; A separator for separating second data from the trellis decoded broadcast signal; And And an error correction decoder for correcting an error generated in the second data by performing error correction decoding on the separated second data. The method of claim 6, And a deinterleaver for performing deinterleaving on the second data, further included in front of the error correction decoder. delete delete The method of claim 6, And the second data is received by performing at least one more interleaving than the first data.

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