KR100953066B1 - Flash memory cell - Google Patents

Abstract

The present invention relates to a NAND type flash memory cell having a stacked gate structure, and adjusts the doping concentrations of the floating gate and the control gate to reduce the potential of the floating gate to a negative voltage during a program operation. The width of the depletion layer formed at the upper end of the gate is increased. The injection of the electron is reduced by the reduction of capacitance between the floating gate and the control gate due to the increase in the depletion layer. As a result, an over program occurs because the threshold voltage does not rise above a certain voltage. It doesn't work.

Transient Program, Floating Gate, Coupling Ratio, F-N Tunneling, Depletion Layer

Description

Flash memory cell             

1 is a structural diagram of a flash memory cell of a typical stacked gate structure.

2 is a graph for explaining a program operation of a flash memory cell.

3 is a graph illustrating a change in a threshold voltage during an erase operation of a flash memory cell.

4 is a graph illustrating a change in threshold voltage during a program operation of a flash memory cell.

5 is a circuit diagram of a memory cell array for explaining a read operation.

6 is a structural diagram illustrating a flash memory cell according to the present invention;

7 is a circuit diagram illustrating a program operation of a flash memory cell according to the present invention.

8 is a graph showing a change in capacitance between a floating gate and a control gate according to the potential of the floating gate.

9 is a graph showing a change in threshold voltage according to a change in program time.

<Description of the symbols for the main parts of the drawings>

1: semiconductor substrate 2: tunnel oxide film

3: floating gate 4: dielectric film                 

5: control gate 5a: depletion layer

The present invention relates to flash memory cells, and more particularly, to a NAND type flash memory cell having a stacked gate structure in which a transient program is prevented.

In general, a NAND type flash memory cell having a stacked gate structure includes a tunnel oxide film 2, a floating gate 3, a dielectric film 4, and an upper portion of a channel region of a semiconductor substrate 1, as shown in FIG. 1. The gate in which the control gate 5 is stacked is formed, and the junction region 6 formed in the semiconductor substrate 1 on both sides of the gate.

In the flash memory cell configured as described above, hot electrons of the channel are formed by FN tunneling by an electric field formed by a potential difference between the floating gate 3 and the substrate 1. It is programmed as it is injected into the floating gate 3. That is, as shown in FIG. 2, the suspending voltage Vt changes according to the degree of injection of electrons into the bottom gate used as the floating gate 3, and thus, the logic "1" and "0". Are distinguished.

In general, as shown in FIG. 3, the threshold voltage Vt of the memory cell is reduced, so that a current flows to the drain connected to the bit line by an arbitrary bias voltage applied to the control gate 5 when read. The logic " 1 " state is defined as erase, and the logic " 0 " state which is an OFF state in which no current flows is increased by increasing the threshold voltage Vt of the memory cell as shown in FIG. It is prescribed.

For erasing a memory cell, the threshold voltage Vt may be made below a specific voltage level at which current may flow when read, but for a program, the threshold voltage Vt may be above a certain voltage level at which current may not flow when read. It must be maintained. However, if the threshold voltage Vt becomes too high, that is, over programmed, the memory cell MC3 may be over programmed even if a predetermined voltage (for example, 4.5 V) is applied to the word line as shown in FIG. 5. As a result, the current driving capacity is reduced or no current flow occurs.

For example, in the flash memory device in which the threshold voltage distribution of the erased memory cell is -1 to -3V and the threshold voltage distribution of the programmed memory cell is 1 to 3V, as shown in FIGS. 3 and 4, FIG. 5. If the memory cells MC1 and MC3 are programmed to maintain threshold voltages of 3V and 5V, respectively, and the memory cells MC2 are erased to maintain the threshold voltage of -2V, the memory cells MC2 and MC3 are stored in the memory cells MC2. To read the information, 0V is applied to the word lines of the memory cells MC2 and 4.5V is applied to the word lines of the other memory cells MC1 and MC3. However, if the threshold voltage of the unselected memory cell MC3 is maintained at about 5V due to an excessive program, it is not turned on even when 4.5V is applied to the word line. Therefore, since the current flowing through the bit line BL does not reach a senseable current level, information stored in the selected memory cell MC2 cannot be read. That is, since the flow of current through the bit line BL is not sensed, a malfunction that is recognized as a programmed memory cell occurs.

Accordingly, the present invention provides a flash memory cell that can solve the above disadvantages by adjusting the doping concentration of the floating gate and the control gate to increase the width of the depletion layer formed on the control gate or the floating gate during the program operation. There is a purpose.

delete

delete

The flash memory cell according to the embodiment of the present invention for achieving the above object is a floating gate formed on a substrate and electrically separated by a tunnel oxide film, and formed on the floating gate and the floating gate formed by a dielectric film; And a junction region formed on the substrate on both sides of the floating gate, wherein different ions are injected into the control gate and the floating gate, and the concentration of ions injected into the control gate is increased. As the potential of the floating gate decreases to a negative voltage during a program operation, the width of the depletion layer formed at the upper end of the floating gate increases so that the threshold voltage is higher than a predetermined voltage. It is characterized in that it is configured not to be raised. P-type ions are implanted in the floating gate, N-type ions are implanted in the control gate, and P-type ions implanted in the floating gate are boron (B) of 1.2E20 / cm 3 to 1.0E19 / cm 3, and the control The N-type ions implanted into the gate are 2.0E20 / cm 3 or more of phosphorus (P) or 2.0E20 / cm 3 to 4.0E20 / cm 3 of arsenic (As).

Flash memory cell according to another embodiment of the present invention for achieving the above object is characterized in that the N-type ions are implanted in the floating gate, P-type ions are implanted in the control gate.

The N-type ions implanted into the floating gate are phosphorus (P) of 1.2E20 / cm 3 to 1.0E19 / cm 3 or arsenic (As) of 1.0E20 / cm 3 to 1.0E19 / cm 3, and the P-type ions implanted into the control gate Is 1.2E20 / cm 3 to 1.0E19 / cm 3 of boron (B).

Hereinafter, a flash memory cell according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, the potential of the floating gate 3 to which the direct bias voltage cannot be applied is the coupling capacitance ratio of the bias of each terminal surrounding the floating gate 3, that is, the control gate 5. ), And the amount of electric potential and self charge induced by the coupling capacitance ratio between the substrate 1 and the junction region 6 and the floating gate 3. This relationship is illustrated by Equation 1 below.

Vfg = Kfc * Vg + Kd * Vd + Ks * Vs + Kb * Vb + Kfc (Vt_uv □ Vt_cell)

Where Ct = Cfc + Cd + Cs + Cb

Vt_uv: Cell threshold voltage (Vt) at equilibrium

Vt_cell: Current cell threshold voltage (Vt)

Kfc (ONO coupling ratio) = Cfc / Ct

Kd (drain coupling ratio) = Cd / Ct

Ks (source coupling ratio) = Cs / Ct

Kb (substrate coupling ratio) = Cb / Ct

Kfc + Kd + Ks + Kb = 1

Therefore, the thickness and area of the dielectric material existing between the floating gate 3 and each terminal greatly influence the potential formation of the floating gate 3.

The program operation is performed by applying a positive voltage bias to the control gate 5 and a ground voltage (0V) to the substrate 1. Typically, the thickness of the second dielectric material (dielectric film) between the control gate 5 and the floating gate 3 is relatively thicker than the thickness of the first dielectric material (tunnel oxide film) between the floating gate 3 and the substrate 1. To prevent the passage of electrons, but to increase the area to compensate for the reduction of the coupling capacitance, the coupling capacitance ratio between the control gate 5 and the floating gate 3 is 0.6, the junction region 6 and the substrate 1 ) And the coupling ratio between the floating gate 3 is maintained at about 0.4. Therefore, when the threshold voltage Vt of the memory cell is -1V, and 18V is applied to the control gate 5 and 0V is applied to the substrate 1 in the memory cell having the original threshold voltage Vt of 1V, the floating gate 3 The potential is about 12V. Thus, if the potential difference applied to the first dielectric material is 12V and the thickness is 8 nm, an electric field of about 15 MV / cm is formed and electrons are injected into the floating gate 3 by F-N tunneling.

When the program proceeds and the threshold voltage Vt of the memory cell reaches 2V, the potential of the floating gate 3 becomes 10.2V and the electric field becomes 12.75MV / cm. Since the FN tunneling current is exponentially proportional to the electric field as shown in Equation 2 below, as the program time increases as shown in the line A of FIG. 9, the threshold voltage Vt of the memory cell continuously increases to rise to 4.5 V or more. Can be.

J = A * E ² exp (-B / E)

Where J is the tunneling current density

A, B: constant

E: electric field

However, if the coupling ratio applied to the second dielectric material is decreased when the threshold voltage Vt of the memory cell is increased by the program, the potential of the floating gate 3 moves in the negative voltage direction accordingly. The electric field applied to the material is reduced to suppress the movement of electrons due to FN tunneling, thereby maintaining a specific threshold voltage Vt.

When the threshold voltage Vt of the memory cell is increased by the program, the potential of the floating gate 3 moves in the negative voltage direction. Then, as shown in FIG. 6, a depletion layer 5a is formed in the control gate 5 made of N-type polysilicon as in a substrate of a general transistor, and a capacitance is formed as shown in FIG. 7. The coupling capacitance between 5) and the floating gate 3 is reduced as shown in FIG. That is, as Cfc decreases in Equation 1, the coupling ratio Kfc also decreases. Therefore, as shown in the program characteristic curve of FIG. 9, when the threshold voltage Vt is reached, the FN tunneling current is exponentially reduced due to the decrease of the electric field, and the threshold voltage Vt of the memory cell converges to a certain level. )do. However, if the doping concentration is set too low, an inversion layer may be formed in the control gate 5, and thus, doping should be performed so that only a depletion layer can be formed. In the graph of FIG. 9, the line A represents a continual increase in the threshold voltage Vt with the program time in the conventional memory cell, while the lines B, C, and D decrease the doping concentrations of the floating gate and the control gate. The threshold voltage Vt does not increase continuously but shows convergence to a constant voltage.

Next, an embodiment of the present invention for preventing a transient program by preventing the continuous increase of the threshold voltage Vt as described above will be described.

Example 1

High concentration N-type ions are implanted into the floating gate 3, and low concentration N-type ions are implanted into the control gate 5. The floating gate 3 is implanted with a high concentration of N-type ions such as phosphorus (P) or arsenic (As) of 2.0E20 / cm 3 or more, and the phosphorus of 1.2E20 / cm 3 to 1.0E19 / cm 3 in the control gate 5. Low concentration N-type ions such as (P) or arsenic (As) of 1.0E20 / cm 3 to 1.0E19 / cm 3 are implanted.

When a positive voltage is applied to the control gate 5 and a ground voltage (0V) is applied to the substrate 1 to program a memory cell, hot electrons of a channel region are transferred to the floating gate 3 by FN tunneling. The threshold voltage Vt is increased to increase the width of the depletion layer 5a formed at the lower end of the control gate 5 as the potential of the floating gate 3 decreases to a negative voltage by the injection of the electron. Is increased so that the threshold voltage Vt does not rise above a certain voltage.

[Example 2]

Low concentration P-type ions are implanted into the floating gate 3, and high concentration N-type ions are implanted into the control gate 5. Low concentration P-type ions such as boron (B) of 1.2E20 / cm 3 to 1.0E19 / cm 3 are implanted into the floating gate 3, and phosphorus (P) or 2.0E20 of 2.0E20 / cm 3 or more to the control gate 5. High concentration N-type ions such as arsenic (As) of / cm 3 to 4.0E 20 / cm 3 are implanted.

When a positive voltage is applied to the control gate 5 and a ground voltage (0V) is applied to the substrate 1 to program a memory cell, hot electrons of a channel region are transferred to the floating gate 3 by FN tunneling. The threshold voltage Vt is increased to increase the width of the depletion layer 5a formed at the upper end of the floating gate 3 as the potential of the floating gate 3 decreases to a negative voltage by the injection of the electron. Is increased so that the threshold voltage Vt does not rise above a certain voltage.

Example 3

Low concentration N-type ions are implanted into the floating gate 3, and low concentration P-type ions are implanted into the control gate 5. The floating gate 3 is implanted with a low concentration of N-type ions such as phosphorus (P) of 1.2E20 / cm 3 to 1.0E19 / cm 3 or arsenic (As) of 1.0E20 / cm 3 to 1.0E19 / cm 3, and the control gate (5) is implanted with a low concentration of P-type ions such as boron (B) of 1.2E20 / cm 3 to 1.0E19 / cm 3.

When a positive voltage is applied to the control gate 5 and a ground voltage (0V) is applied to the substrate 1 to program a memory cell, hot electrons of a channel region are transferred to the floating gate 3 by FN tunneling. The threshold voltage Vt is increased to increase the width of the depletion layer 5a formed at the upper end of the floating gate 3 as the potential of the floating gate 3 decreases to a negative voltage by the injection of the electron. Is increased so that the threshold voltage Vt does not rise above a certain voltage.

As described above, the present invention increases the width of the depletion layer formed on the lower end of the control gate or the upper end of the floating gate as the potential of the floating gate decreases to a negative voltage during the program operation by adjusting the doping concentrations of the floating gate and the control gate. Be sure to The injection of electrons is reduced by the reduction of the capacitance between the floating gate and the control gate due to the increase in the depletion layer. As a result, the threshold voltage does not rise above a certain voltage. Therefore, the transient program does not occur, thereby screening the transient program. No special steps are required, the failure rate is reduced, and the influence of peripheral circuits due to transient programming is avoided.

Claims (8)

delete delete delete A floating gate formed on the substrate and electrically separated by the tunnel oxide film; A control gate formed on the floating gate and electrically separated from the floating gate by a dielectric film; A junction region formed in the substrate on both sides of the floating gate, Different ions are injected into the control gate and the floating gate, and the concentration of the ions injected into the control gate is equal to or higher than the concentration of the ions injected into the floating gate, so that the potential of the floating gate is increased during a program operation. And a depletion layer formed at an upper end of the floating gate increases as the voltage decreases to a negative voltage, thereby preventing the threshold voltage from rising above a predetermined voltage. 5. The flash memory cell of claim 4, wherein P-type ions are implanted in the floating gate and N-type ions are implanted in the control gate. The method of claim 5, wherein the P-type ions implanted into the floating gate is boron (B) of 1.2E20 / cm3 to 1.0E19 / cm3, and the N-type ions implanted into the control gate is 2.0E20 / cm3 or more phosphorus (P) Or arsenic (As) of 2.0E20 / cm 3 to 4.0E20 / cm 3. 5. The flash memory cell of claim 4, wherein the floating gate is implanted with N-type ions and the control gate is implanted with P-type ions. The N-type ion implanted in the floating gate is phosphorous (P) of 1.2E20 / cm 3 to 1.0E19 / cm 3 or arsenic (As) of 1.0E20 / cm 3 to 1.0E19 / cm 3. P-type implanted into the flash memory cell, characterized in that the boron (B) of 1.2E20 / cm 3 to 1.0E19 / cm 3.

Images