KR100949270B1 - Semiconductor memory device - Google Patents

Abstract

The present invention provides a method for driving a first transmission line corresponding to the first bank group in response to the bank information and address information, and first and second bank groups each having a plurality of banks activated in response to bank information. It provides a semiconductor memory device having a first address driving means, and a second address driving means for driving a second transmission line corresponding to the second bank group in response to the bank information and the address information.

Bank Groups, Global Address Lines, Bank Information, Additive Latency

Description

Semiconductor memory device {SEMICONDUCTOR MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly, to an address driver for transferring an externally input address to a global address line disposed inside a semiconductor memory device.

In general, semiconductor memory devices, including DDR Double Data Rate Synchronous DRAM (SDRAM), store data or output data according to commands required by a central processing unit (CPU), for example. If the CPU requests a write operation, it stores data corresponding to a memory cell corresponding to an address input from the CPU, and if a read operation is requested, the data is stored at an address input from the CPU. Output data stored in the corresponding memory cell. Therefore, the semiconductor memory device includes a global address line through which an address is transmitted, and an address driver for receiving an external address and applying the address to the global address line.

1 is a circuit diagram illustrating an address driver of a 512 mega semiconductor memory device. For reference, the 512 mega semiconductor memory device has four banks.

Referring to FIG. 1, an address driver includes a read address input unit 110, a write address input unit 130, and an address output unit 150. For reference, an address applied by the CPU includes a plurality of address signals, and the address driver disclosed in FIG. 1 corresponds to one address signal input during a read operation and a write operation.

The read address input unit 110 outputs the read address signal RDLA input during the read operation in response to the read pulse signal IRDP. The read pulse signal IRDP is a pulse signal that is activated during a read operation of the semiconductor memory device.

The write address input unit 130 receives a write address signal WTLA input during a write operation and outputs the write address signal WWLA in response to the write pulse signal IWTP. The write pulse signal IWTP is a pulse signal that is activated during a write operation of the semiconductor memory device.

The address output unit 150 is used to drive the global address line G_ADD with the output signals of the read address input unit 110 and the write address input unit 130, and includes a latching unit 152 and a driving unit 154.

The latching unit 152 latches the output signals of the read address input unit 110 and the write address input unit 130, and the driving unit 154 uses the global address line G_ADD as the address signal latched by the latching unit 152. ). Here, the global address line G_ADD is connected to each column decoder (not shown) corresponding to four banks (not shown) to transmit a signal output from the driver 154 to each column decoder during a read operation or a write operation. To deliver, it has a relatively large loading. Therefore, the driver 154 should have a relatively large driving force corresponding to the loading of the global address line G_ADD.

Meanwhile, semiconductor memory devices are being developed in response to the demand for miniaturization, large capacity, and low power consumption, and the number of banks is increasing as part of achieving large capacity.

2 is a circuit diagram illustrating an address driver of a 1 Giga semiconductor memory device. For reference, one Gigabit semiconductor memory device has eight banks. The address driver of FIG. 2 is designed differently from the first and second drivers 210 and 230 as compared to the address driver of FIG. 1. For convenience of description, descriptions other than the first and second drivers 210 and 230 will be described. It will be omitted.

Referring to FIG. 2, the first driver 210 drives the first global address line G_1234ADD with the address signal latched at the front end, and the second driver 230 also has the second signal with the address signal latched at the previous stage. The global address line G_5678ADD is driven. Here, the first global address line G_1234ADD corresponds to four banks (hereinafter, referred to as 'first bank groups') among four banks among eight banks, and four columns corresponding to the first bank group. In connection with a decoder (not shown), a signal output from the first driver 210 is transferred to a corresponding column decoder in a read operation or a write operation. The second global address line G_5678ADD corresponds to the remaining four banks (hereinafter, referred to as a 'second bank group') and is connected to four column decoders (not shown) corresponding to the second bank group. The signal output from the second driver 230 is transferred to a corresponding column decoder in a read operation or a write operation.

The first and second global address lines G_1234ADD and G_5678ADD have relatively large loadings. Therefore, the first and second drivers 210 and 230 should have a relatively large driving force corresponding to the loading of the first and second global address lines G_1234ADD and G_5678ADD. Here, the large driving force of the first and second driving units 210 and 230 means higher power consumption. That is, the first and second drivers 210 and 230 drive the first and second global address lines G_1234ADD and G_5678ADD with address signals latched in a read operation or a write operation. do.

In other words, the conventional address driver of FIG. 2 generates unnecessary power consumption in separately accessing the bank corresponding to the first bank group and the bank corresponding to the second bank group. That is, when an address for accessing a bank corresponding to the first bank group is applied, the second global address line G_5678ADD corresponding to the second bank group is unnecessarily driven, and similarly to the bank corresponding to the second bank group. When an address for access is applied, the first global address line G_1234ADD corresponding to the first bank group is unnecessarily driven. This unnecessary driving operation has a problem that eventually generates unwanted power consumption.

The present invention has been proposed to solve the above problems, and an object thereof is to provide a semiconductor memory device capable of driving a global address line corresponding to a bank group to which access is made, and a driving method thereof.

According to an aspect of the present invention, there is provided a semiconductor memory device, including: first and second bank groups each having a plurality of banks activated in response to bank information; First address driving means for driving a first transmission line corresponding to the first bank group in response to the bank information and the address information; And second address driving means for driving a second transmission line corresponding to the second bank group in response to the bank information and the address information.

According to another aspect of the present invention, there is provided a semiconductor memory device, including: first and second bank groups each having a plurality of banks activated in response to bank information; The first and second read control signals corresponding to the first and second bank groups are generated by reflecting the first latency reflected in the address information in the read operation in the bank information, and reflected in the address information in the write operation. Control signal generation means for generating first and second write control signals corresponding to the first and second bank groups by reflecting the second latency to be in the bank information; First address driving means for driving a first transmission line corresponding to the first bank group in response to the first read control signal, the first write control signal, and the address information in the read operation and the write operation; And second address driving means for driving a second transmission line corresponding to the second bank group in response to the second read control signal, the second write control signal, and the address information in the read operation and the write operation. Equipped.

In the case of a conventional semiconductor memory device, when all bank groups are accessed, all global address lines corresponding to all bank groups are driven, thereby causing unnecessary power consumption. In contrast, the semiconductor memory device according to the present invention may selectively drive a global address line corresponding to a bank group to which access is made using bank information corresponding to the bank group.

According to the present invention, by selectively driving a global address line corresponding to a bank group to which access is made, an effect of minimizing power consumed in performing a read operation and a write operation can be obtained.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

FIG. 3 is a block diagram illustrating a part of a configuration of a semiconductor memory device according to the present invention, which is a 1 Giga semiconductor memory device having 8 banks as in FIG. 2.

Referring to FIG. 3, the semiconductor memory device may include a first bank group 310, a second bank group 330, a first address driver 350, and a second address driver 370.

The first through fourth banks 312A, 312B, 312C, and 312D of the first bank group 310 and the first through fourth column decoders 314A, 314B, 314C, and 314D corresponding to the respective banks may be provided. have. The first to fourth banks 312A, 312B, 312C, and 312D include a plurality of memory cells capable of storing data, and the first to fourth column decoders 314A, 314B, 314C, and 314D may include a plurality of memory cells. A column selection signal for decoding one of a plurality of address signals transmitted through a first global address line G_1234ADD <0:11> and selecting one of a plurality of memory cells of a bank activated by bank information Not shown). Thus, the first to fourth column decoding units 314A, 314B, 314C, and 314D share a plurality of first global address lines G_1234ADD <0:11>.

Fifth to eighth banks 332A, 332B, 332C, and 332D of the second bank group 330 and fifth to eighth column decoders 334A, 334B, 334C, and 334D corresponding to each bank. have. The fifth to eighth banks 332A, 332B, 332C, and 332D also include a plurality of memory cells capable of storing data, and the fifth to eighth column decoders 334A, 334B, 334C, and 334D may include a plurality of memory cells. Column selection signal for selecting any one of a plurality of memory cells of the bank activated by the bank information by decoding the plurality of address signals transmitted through the second global address line G_5678ADD <0:11> ) Can be created. Thus, the fifth to eighth column decoding units 334A, 334B, 334C, and 334D are shared with each other.

For reference, the bank information is a signal for activating a desired bank among the eight banks, and includes three bank information signals (eg, BA <0>, BA <1>, and BA <2>). The BA <2> bank information signal is a signal that can distinguish the first bank group 310 from the second bank group 330.

Meanwhile, the first address driver 350 may include a plurality of read address signals RDLA <0:11> applied during a read operation, a plurality of write address signals WTLA <0:11> applied during a write operation, and The plurality of first global address lines G_1234ADD <0:11> corresponding to the first bank group 310 may be driven in response to the bank information signal BA <2>. The first address driver 350 may be provided in a number corresponding to the read address signals RDLA <0:11> and the write address signals WTLA <0:11> which are address information. That is, since a plurality of read address signals RDLA <0:11> and a plurality of write address signals WTLA <0:11> are inputted by 12, respectively, 12 first address drivers 350 should be provided. 12 corresponding global address lines should be provided. Thus, the twelve read address signals RDLA <0:11> and the twelve write address signals WTLA <0:11> are respectively input to the corresponding first address driver and the plurality of first global address lines corresponding thereto. It is preferable to output to (G_1234ADD <0:11>).

The second address driver 370 responds to the read address signal RDLA <0:11>, the write address signal WTLA <0:11>, and the bank information signal BA <2> in response to the second bank group. The plurality of second global address lines G_5678ADD <0:11> corresponding to 330 may be driven. Here, like the first address driver 350, 12 second address drivers 370 are provided corresponding to the read address signals RDLA <0:11> and the write address signals WTLA <0:11>. 12 corresponding global address lines should be provided.

Therefore, the semiconductor memory device according to the present invention receives the read address signals RDLA <0:11> during the read operation and receives the first and second global address lines G_1234ADD <in response to the bank information signals BA <2>. 0:11> and G_5678ADD <0:11>). In the case of a conventional semiconductor memory device, a plurality of first global address lines G_1234ADD corresponding to a first bank group and a plurality of second global address lines G_5678ADD corresponding to a second bank group cannot be driven separately, thereby unnecessary power. Compared to the depletion, the semiconductor memory device according to the present invention has a first global address line G_1234ADD <0:11> and a second global address line G_5678ADD <0 corresponding to a desired bank group during read and write operations. (11>) is driven separately by the bank information signal BA <2>, so that unnecessary power consumption can be prevented.

In the meantime, various functions are imposed on semiconductor memory devices to satisfy demands of consumption, and specifications (SPEC.) Are determined to regulate them to some extent. Among them are additive latency (AL) and cas latency (CAS latency). Hereinafter, this will be described in more detail with reference to the description.

The external command signal input from the CPU may define an active operation, a precharging operation, a read operation, a write operation, and the like of the semiconductor memory device. Here, the column command signal is activated during the read operation and the write operation, and the column command signal is a column selection signal that determines when to store the data in the memory cell during the write operation and when the data stored in the memory cell is output during the read operation. Is closely related to. The external command signals include a chip select signal, a row address strobe (RAS) signal, a column address strobe (CAS) signal, a write enable signal, and the like. .

Meanwhile, the semiconductor memory device typically performs an active operation and performs a read operation or a write operation after tRCD (RAS to CAS Delay) defined by the specification. In other words, the read pulse signal IRDP activated during the read operation and the write pulse signal IWTP activated during the write operation should be activated after tRCD is guaranteed. This is because a minimum tRCD is required to perform an internal operation corresponding to the active operation.

However, as the user's preferences are diversified, the semiconductor memory device is designed to receive an external command signal corresponding to a read operation or a write operation before tRCD. The external command signal corresponding to the read operation (hereinafter referred to as read command signal) or the external command signal corresponding to the write operation (hereinafter referred to as write command signal) is applied and held before tRCD. can be outputted as a read pulse signal IRDP or a write pulse signal IWTP at a time point when tRCD is satisfied.

Here, the time point at which the read command signal is applied before tRCD is defined as an additive latency AL. For example, when the additive latency AL is 2, the read command signal is applied 2 clocks before the desired tRCD based on the external clock signal. If the additive latency AL is 0, the read command signal is applied considering only tRCD.

Subsequently, when the read command signal is applied, the semiconductor memory device outputs data after a predetermined time, which is defined as the cascade latency CL. For example, when the additive latency AL is 0 and the cascade latency CL is 3, a read command signal is applied and data is output after 3 clocks based on the external clock signal.

As described above, in the read operation, the additive latency (AL) and the cascade latency (CL) must be guaranteed to meet specifications. This situation must be guaranteed for write operations as well. Therefore, the additive latency AL and the cascade latency CL are reflected in the read pulse signal IRDP corresponding to the read operation and the write pulse signal IWTP corresponding to the write operation. That is, the read pulse signal IRDP is applied with a read command signal and is synchronized with the clock signal after the additive latency AL, and the write pulse signal IWTP is applied with a write command signal and has a write latency. After WL), it is output in synchronization with the clock signal. Here, the light latency WL is a latency including an additive latency AL and a cascade latency CL, which may be generally defined by Equation 1, and may vary according to design.

Hereinafter, if the read pulse signal IRDP and the write pulse signal IWTP are redefined, the read pulse signal IRDP is a pulse signal to which a read command signal is applied and is activated after the additive latency AL. IWTP is a pulse signal to which a write command signal is applied and is activated after the write latency WL.

On the other hand, the read latency signal RDLA applied at the same time as the read command signal reflects the additive latency AL so that it can be latched by the read pulse signal IRDP, and applied at the same time as the write command signal. The write latency signal WL is reflected to the extent that the write address signal WTLA can be latched by the write pulse signal IWTP. In particular, the write pulse signal IWTP may be designed to further reflect the latency considering the burst length of data in addition to the write latency WL. If the burst length is 4, the write pulse signal IWTP should additionally reflect, for example, 2tCK corresponding to the burst length in addition to the write latency WL.

FIG. 4 is a diagram for describing the first and second address drivers 350 and 370 of FIG. 3, wherein the first and second addresses according to the present invention are considered in consideration of the additive latency AL and the cascade latency CL. The control signal generator 410 for controlling the drivers 350 and 370 is shown. In FIG. 4, for convenience of description, only one of the plurality of read address signals RDLA <0:11> and the plurality of write address signals WTLA <0:11> is shown. For reference, reference numerals of the first address driver 350 may be newly referred to as '430' and reference numerals of the second address driver 370 will be newly referred to as '450'.

3 and 4, the control signal generator 410 reads the first and second reads in response to the column command signal RDWT, the bank information signal BA <2>, and the clock signal CLK. The control signals CTR_1234RD and CTR_5678RD and the first and second write control signals CTR_1234WT and CTR_5678WT may be generated.

The first read control signal CTR_1234RD corresponds to the first to fourth banks 312A, 312B, 312C, and 312D of the first bank group 310, and corresponds to the address signal RDLA applied during the read operation. The reflected latency, that is, the signal reflecting the additive latency AL by the bank information signal BA <2>, and the second read control signal CTR_5678RD is the fifth to eighth banks of the second bank group 330. Corresponding to (332A, 332B, 332C, and 332D), the signal reflects only the additive latency AL in the bank information signal BA <2>. Subsequently, the first write control signal CTR_1234WT corresponds to the first to fourth banks 312A, 312B, 312C, and 312D of the first bank group 310, and corresponds to the address signal WTLA applied during the write operation. The reflected latency, that is, the signal reflecting the write latency WL in the bank information signal BA <2>, and the second write control signal CTR_5678WT is the fifth to eighth banks of the second bank group 330. Corresponding to (332A, 332B, 332C, and 332D), the signal reflects the write latency WL in the bank information signal BA <2>. In other words, the light latency WL may be defined by Equation 1.

FIG. 5 is a block diagram illustrating the control signal generator 410 of FIG. 4.

Referring to FIG. 5, the control signal generator 410 may include a latency reflecting unit 510 and a control signal output unit 530.

The latency reflecting unit 510 reflects and outputs the additive latency AL and the write latency WL to the bank information signal BA <2>, and includes the bank information signal latching unit 512 and the additive latency. The reflector 514 and the cas latency reflector 516 may be provided.

The bank information signal latching unit 512 may latch the bank information signal BA <2> in response to the column command signal RDWT. The column command signal RDWT is a signal that is activated during a read operation and a write operation. Thus, the bank information signal BA <2> may be latched in synchronization with the column command signal RDWT.

FIG. 6 is a circuit diagram illustrating the bank information signal latching unit 512 of FIG. 5.

5 and 6, the bank information signal latching unit 512 may include a transfer unit 610 and a latching unit 630.

The transfer unit 610 transmits the bank information signal BA <2> to the latching unit 630 in response to the column command signal RDWT. The transfer unit 610 receives the column command signal RDWT and inverts the first inverter. INV1 and a transfer gate TG for transferring the bank information signal BA <2> to the latching unit 630 in response to the column command signal RDWT and the output signal of the first inverter INV1. can do.

The latching unit 630 latches the output signal of the transmission unit 610, and receives the output signal of the transmission unit 610 and inverts the second inverter INV2 and the output signal of the second inverter INV2. It may be provided with a third inverter (INV3) for receiving the inverted to output to the input terminal of the second inverter (INV2). Operation waveforms of the signals will be described in detail with reference to FIG. 9.

Referring to FIG. 5 again, the additive latency reflecting unit 514 shifts the output signal NET_A of the bank information signal latching unit 512 in response to the clock signal CLK, and adds the shifted signal to the addi- tion of the shifted signal. The signal corresponding to the creative latency AL <0: 6> may be selectively output.

FIG. 7 is a circuit diagram for describing the additive latency reflecting unit 514 of FIG. 5.

5 and 7, the additive latency reflecting unit 514 may include a plurality of shifting units 710, an additive latency multiplexer 730, and an output unit 750.

The shifting units 710 shift the output signal NET_A of the bank information signal latching unit 512 in response to the clock signal CLK, and include the first to sixth synchronization units 711, 712, 713, 714, 715, 716. That is, the output signal NET_AL <1> of the first synchronization unit 711 is a signal obtained by shifting the output signal NET_A of the bank information signal latching unit 512 once in response to the clock signal CLK. The output signal NET_AL <2> of the second synchronization unit 712 is a signal obtained by shifting the output signal NET_A of the bank information signal latching unit 512 twice in response to the clock signal CLK.

The additive latency multiplexer 730 selectively selects a signal corresponding to the additive latency AL <0: 6> among the output signals of the first to sixth synchronization units 711, 712, 713, 714, 715, and 716. The first to seventh transfer parts 731, 732, 733, 734, 735, 736, and 737 corresponding to the additive latency AL <0: 6> may be provided. That is, the first transfer unit 731 outputs the output signal NET_AL <1> of the first synchronization unit 711 in response to the 'AL <1>' additive latency, and the second transfer unit 732 The output signal NET_AL <2> of the second synchronization unit 712 is output in response to the 'AL <2>' additive latency.

Subsequently, the output unit 750 outputs the output signal selected by the additive latency multiplexer 730 as an output signal NET_B of the additive latency reflecting unit 514. Operation waveforms of the signals will be described in detail with reference to FIG. 9.

 Referring to FIG. 5 again, the cas latency reflecting unit 516 shifts the output signal NET_B of the additive latency reflecting unit 514 in response to the clock signal CLK, and among the shifted signals, the cas latency (CL <). 2: 7>) can be selectively output.

FIG. 8 is a circuit diagram illustrating the cas latency reflecting unit 516 of FIG. 5.

5 and 8, the CAS latency reflecting unit 516 may include a plurality of shifting units 810, a CAS latency multiplexing unit 830, and an additional shifting unit 850.

The shifting units 810 shift the output signal NET_B of the additive latency reflecting unit 514 in response to the clock signal CLK, and include the first to sixth synchronization units 811, 812, 813,. 814, 815, 816. That is, the output signal NET_CL <2> of the first synchronization unit 811 is a signal obtained by shifting the output signal NET_B of the additive latency reflecting unit 514 once in response to the clock signal CLK. The output signal NET_CL <3> of the second synchronization unit 812 is a signal obtained by shifting the output signal NET_B of the additive latency reflecting unit 514 twice in response to the clock signal CLK.

The CAS latency multiplexer 830 selectively outputs a signal corresponding to CAS latency CL <2: 7> among the output signals of the first to sixth synchronization units 811, 812, 813, 814, 815, and 816. In order to do so, the first to sixth transfer units 831, 832, 833, 834, 835, and 836 corresponding to the cascade latency CL <2: 7> may be provided. That is, the first transfer unit 731 outputs the output signal NET_CL <2> of the first synchronization unit 811 in response to the 'CL <2>' cas latency, and the second transfer unit 732 is' The output signal NET_CL <3> of the second synchronization unit 812 is output in response to the CL <3> 'cas latency.

Subsequently, the additional shifting unit 850 shifts the output signal of the CAS latency multiplexer 730 in response to the clock signal CLK, and may perform an additional shifting operation in consideration of the burst length in addition to the write latency WL. have. The additional shifting unit 850 is preferably designed according to the situation. For reference, the output signal NET_C of the CAS latency reflecting unit 516 reflects the additive latency AL and the CAS latency CL in the bank information signal BA <2>, that is, the light latency WL. It becomes the reflected signal. Operation waveforms of the signals will be described in detail with reference to FIG. 9.

Referring back to FIG. 5, the control signal output unit 530 may respond to the output signal NET_B of the additive latency reflecting unit 514 and the output signal NET_C of the cascade latency reflecting unit 516. 2 For generating the read control signals CTR_1234RD and CTR_5678RD and the first and second write control signals CTR_1234WT and CTR_5678WT, the read control signal output unit 532 and the write control signal output unit 534 may be provided. have.

The read control signal output unit 532 outputs the first and second read control signals CTR_1234RD and CTR_5678RD in response to the output signal NET_B of the additive latency reflecting unit 514. The first inverter INV1 that receives the output signal NET_B of 514 and inverts the output signal NET_B and outputs the first read control signal CTR_1234RD, and the second read control that inverts the first read control signal CTR_1234RD. The second inverter INV2 for outputting the signal CTR_5678RD may be provided. Here, the first read control signal CTR_1234RD and the second read control signal CTR_5678RD may have opposite phases, and one of the first address driver 430 and the second address driver 450 may be a read address signal. (RDLA) can be controlled to receive. That is, one of the first and second read control signals CTR_1234RD and CTR_1234RD may be activated in response to the bank information signal BA <2>.

The write control signal output unit 534 outputs the first and second write control signals CTR_1234WT and CTR_5678WT in response to the output signal NET_C of the cascade latency reflecting unit 516. A third inverter (INV3) that receives the output signal NET_C of the output signal NET_C and inverts the first write control signal CTR_1234WT, and receives the first write control signal CTR_1234RD. A fourth inverter INV4 for outputting CTR_5678WT may be provided. Here, the first write control signal CTR_1234WT and the second write control signal CTR_5678WT may have opposite phases, and any one of the first address driver 430 and the second address driver 450 may be a write address signal. (WTLA) can be controlled to receive input. That is, one of the first and second write control signals CTR_1234WT and CTR_5678WT may be activated in response to the bank information signal BA <2>. Operation waveforms of the signals will be described in detail with reference to FIG. 9.

Meanwhile, referring back to FIG. 4, the first address driver 430 may respond to the first read control signal CTR_1234RD and the first write control signal CTR_1234WT in a read operation and a write operation, and thus, the first global address line G_1234ADD. ) Is used to drive the read address signal RDLA or the write address signal WTLA, and may include a read address input unit 432, a write address input unit 434, and an address output unit 436.

The read address input unit 432 receives the read address signal RDLA in response to the first read control signal CTR_1234RD and the read pulse signal IRDP. The read address input unit 432 receives the transfer unit 432_1 and the activator 432_2. It can be provided.

The transfer unit 432_1 is to transfer the read address signal RDLA to the address output unit 436 in response to the output signal of the activator 432_2, and receives and outputs the output signal of the activator 432_2. The inverter INV, and a transfer gate TG for transmitting the read address signal RDALA in response to the output signal of the activator 432_2 and the output signal of the inverter INV may be provided.

The activation unit 432_2 is for activating the transfer unit 432_1 in response to the first read control signal CTR_1234RD and the read pulse signal IRDP, and the external power voltage terminal VDD and the first NMOS transistor NM1. A source-drain path is formed between the first PMOS transistor PM1 and the first NMOS transistor NM1 and the second NMOS transistor NM2 that receive a first read control signal CTR_1234RD as a gate. A drain path is formed and a source-drain path is formed between the first NMOS transistor NM1, which receives the first read control signal CTR_1234RD, and the first NMOS transistor NM1 and the ground voltage terminal VSS. And a second NMOS transistor NM2 that receives the read pulse signal IRDP as a gate.

The write address input unit 434 may receive the write address signal WTLA in response to the first write control signal CTR_1234WT and the write pulse signal IWTP. Since the write address input unit 434 is similar in configuration to the read address input unit 432, detailed configuration description thereof will be omitted. However, the write address input unit 434 is different from the input signal compared to the read address input unit 432. That is, the write address signal WTLA is input instead of the read address signal RDLA, the first write control signal CTR_1234WT is input instead of the first read control signal CTR_1234RD, and the large read pulse signal IRDP is input. The write pulse signal IWTP may be input to the.

The address output unit 436 drives the first global address line G_1234ADD as an output signal of the read address input unit 432 during a read operation, and a first global address line as an output signal of the write address input unit 434 during a write operation. It is for driving (G_1234ADD) and may include a latching portion 436_1 and a driving portion 436_2.

The latching unit 436_1 may latch the output signal of the read address input unit 432 and the output signal of the write address input unit 434, and the driving unit 436_2 may use the first global address as an address latched by the latching unit 436_1. The line G_1234ADD may be driven.

Meanwhile, the second address driver 450 reads the second global address line G_5678ADD in response to the second read control signal CTR_5678RD and the second write control signal CTR_5678WT in read and write operations, and reads the read address signal RDLA. Or the write address signal WTLA. Since the configuration of the second address driver 450 is similar to that of the first address driver 430, detailed descriptions thereof will be omitted. If the second address driver 450 is different from the input signal, the second address driver 450 may be driven differently from the global address line. That is, the second read control signal CTR_5678RD is input instead of the first read control signal CTR_1234RD, the second write control signal CTR_5678WT is input instead of the first write control signal CTR_1234WT, and the first global address. The second global address line G_5678ADD may be driven instead of the line G_1234ADD.

Hereinafter, a brief description of the operation will be given. For convenience of description, the shifting operation corresponding to the burst length of data will be omitted.

First, the read operation will be described. The additive latency AL is reflected in the read pulse signal IRDP, and the read address signal RDLA corresponding to the read operation is latched by the read pulse signal IRDP. As much as possible the additive latency (AL) is reflected. Similarly, the bank information signal BA <2> also reflects the additive latency AL. Subsequently, the first and second read control signals CTR_1234RD and CTR_5678RD are generated in response to the output signal CET_B of the additive latency reflecting unit 514 in which the additive latency AL is reflected in the bank information signal BA <2>. When any one of them is activated, the read address signal RDLA may be output to the first global address line G_1234ADD or the second global address line G_5678ADD according to the bank information signal BA <2>.

Next, the write operation will be described. The write latency signal WL is reflected in the write pulse signal IWTP, and the write address signal WTLA corresponding to the write operation may be latched by the write pulse signal IWTP. The degree of light latency WL is reflected. Similarly, the write information WL is also reflected in the bank information signal BA <2>. Subsequently, any one of the first and second write control signals CTR_1234WT and CTR_5678WT is activated according to the bank information signal BA <2>. Accordingly, the write address signal WTLA is activated by the bank information signal BA <2>. ) May be output to the first global address line G_1234ADD or the second global address line G_5678ADD.

9 is a waveform diagram illustrating an operation waveform of each of the signals illustrated in FIGS. 4 to 8. For convenience of explanation, the operation to be described below is an example in which the additive latency is 2 and the cascade latency is 3, and only the signal waveforms required for the description are shown. We also included an additional 2tCK shifting operation in consideration of the burst length of the data. For reference, the light latency is 5 (additive latency + cas latency).

9 shows a clock signal CLK, a bank information signal BA <2>, a column command signal RDWT, an output signal NET_A of the bank information signal latching unit 512, and an additive latency reflecting unit. Output signals NET_AL <1> and NET_AL <2> of the first and second synchronization units 711, 712 (see FIG. 7) of 514 and the output signal NET_B of the additive latency reflecting unit 514. Of the first and second read control signals CTR_1234RD and CTR_5678RD, the read pulse signal IRDP, and the first and second synchronizers 811 and 812 of the cas latency reflecting unit 516. The output signals NET_CL <2> and NET_CL <3>, the output signal NET_C of the cascade latency reflecting unit 516, the first and second write control signals CTR_1234WT and CTR_5678WT, and the write pulse signal IWTP. ) Is shown.

A read operation (a read operation corresponding to the 'RD7' read command signal) for accessing the seventh bank 332C included in the second bank group 330 will be described with reference to FIGS. 4 through 9. In the 'RD7' read operation, the bank information signal BA <2> is input to, for example, a logic 'high' corresponding to the second bank group 330.

When the 'RD7' read command signal is applied, the bank information signal BA <2> is latched in response to the column command signal RDWT, and the output signal NET_A of the bank information signal latching unit 512 is logic 'low'. Becomes Subsequently, the output signal NET_A of the bank information signal latching unit 512 is shifted and output by the additive latency reflecting unit 514 in response to the clock signal CLK. That is, the output signal NET_AL <1> of the first synchronization unit 711 of the additive latency reflecting unit 514 and the output signal NET_AL of the second synchronization unit 712 of the additive latency reflecting unit 514. <2>) is generated. Since the additive latency is 2, the output signal NET_B of the additive latency reflecting unit 514 is output at a logic 'high' in response to the output signal NET_AL <2> of the second synchronization unit 712. do. Accordingly, the first read control signal CTR_1234RD has a logic 'low', and the second read control signal CTR_5678RD has a logic 'high'.

The second address driver 450 may read the read address signal RDLA in response to the read pulse signal IRDP reflecting the additive latency AL reflected in the RD7 read command signal and the second read control signal CTR_5678RD. 2 The global address line G_5678ADD may be driven. In this case, even if the read pulse signal IRDP is activated, the first address driver 430 does not drive the first global address line G_1234ADD because the first read control signal CTR_1234RD has a logic 'low'.

Next, a write operation (a read operation corresponding to the 'WT1' write command signal) for accessing the first bank 312A included in the first bank group 310 will be described. In the 'WT1' write operation, the bank information signal BA <2> is input to, for example, a logic 'low'.

When the 'WT1' write command signal is applied, the bank information signal BA <2> is latched in response to the column command signal RDWT, and the output signal NET_A of the bank information signal latching unit 512 is logic 'high'. Becomes Subsequently, the output signal NET_A of the bank information signal latching unit 512 is shifted and output by the additive latency reflecting unit 514 in response to the clock signal CLK. That is, the output signal NET_AL <1> of the first synchronization unit 711 of the additive latency reflecting unit 514 and the output signal NET_AL of the second synchronization unit 712 of the additive latency reflecting unit 514. <2>) is generated. Since the additive latency is 2, the output signal NET_B of the additive latency reflecting unit 514 is output as logic 'low' in response to the output signal NET_AL <2> of the second synchronization unit 712. do.

Subsequently, the output signal NET_B of the additive latency reflecting unit 514 is shifted and output in response to the clock signal CLK in the cas latency reflecting unit 516. That is, the output signal NET_CL <2> of the first synchronization unit 811 of the cas latency reflector 516 and the output signal NET_CL <3 of the second synchronization unit 812 of the cas latency reflector 516. >) Is generated. Since the cas latency is 3, the output signal NET_C of the cas latency reflecting unit 516 after the shifting operation of the additional shifting unit 850 is added to the output signal NET_CL <3> of the second synchronization unit 812. Is output as logic low. Accordingly, the first write control signal CTR_1234WT has a logic 'high', and the second write control signal CTR_5678WT has a logic 'low'.

Meanwhile, the first address driver 430 responds to the write pulse signal IWTP and the first write control signal CTR_1234WT reflecting the write latency WL and the additional latency 2tCK in the 'WT1' write command signal. The first global address line G_1234ADD may be driven by the signal WTLA. In this case, even if the write pulse signal IWTP is activated, the second address driver 450 does not drive the second global address line G_5678ADD because the second write control signal CTR_5678WT has a logic 'low'.

As described above, in the semiconductor memory device according to the present invention, the first global address line G_1234ADD and the second global address line G_5678ADD may be driven separately in response to the bank information signal BA <2>. Therefore, the semiconductor memory device according to the present invention can reduce the power consumed more than twice as much as the power consumed in the conventional semiconductor memory device. With the recent development of technology, the number of banks is increasing, and accordingly, the number of global address lines corresponding to each bank or bank group is also increasing. Therefore, the configuration of the present invention can be considered to be suitable for minimizing power consumption. .

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible with various substitutions, modifications, and changes within the scope of the technical idea of the present invention.

In addition, in the above-described embodiment, a case in which one unit having eight banks operates in a semiconductor memory device has been described as an example. Applicable

In the above-described embodiment, a case in which the bank information signal BA <2> is used to distinguish the first and second bank groups 310 and 330 is described as an example. The same applies to the case of using other signals that can distinguish the bank group to be used.

1 is a circuit diagram for explaining an address driver of a 512 mega semiconductor memory device.

FIG. 2 is a circuit diagram for explaining an address driver of a 1 Giga semiconductor memory device. FIG.

3 is a block diagram for explaining a partial configuration of a semiconductor memory device according to the present invention.

4 is a view for explaining the first and second address drivers 350 and 370 of FIG.

5 is a block diagram illustrating the control signal generator 410 of FIG. 4.

FIG. 6 is a circuit diagram for explaining the bank information signal latching section 512 of FIG.

FIG. 7 is a circuit diagram for describing the additive latency reflecting unit 514 of FIG. 5.

FIG. 8 is a circuit diagram illustrating the cas latency reflecting unit 516 of FIG. 5.

FIG. 9 is a waveform diagram for describing an operation waveform of each of the signals shown in FIGS. 4 to 8.

* Explanation of symbols for the main parts of the drawings

310: first bank group 330: second bank group

350: first address driver 370: second address driver

Claims (26)

delete delete delete delete delete delete First and second bank groups each having a plurality of banks activated in response to the bank information; First address driving means for driving a first transmission line corresponding to the first bank group in response to the bank information and the address information; And And second address driving means for driving a second transmission line corresponding to the second bank group in response to the bank information and the address information. The first and second address driving means, respectively, A read address input unit for receiving address information applied in a read operation in response to the bank information; A write address input unit for receiving address information applied during a write operation in response to the bank information; And And an address output unit configured to receive the output signals of the read address input unit and the write address input unit, latch the output signals, and output them to a corresponding transmission line. The method of claim 7, wherein The read and write address input unit, respectively, A transfer unit for transferring corresponding address information applied during the operation to the address output unit; And an activation unit for activating the transfer unit in response to the bank information in the corresponding operation. The method of claim 7, wherein And the address output unit drives the first or second transmission line according to the bank information. First and second bank groups each having a plurality of banks activated in response to the bank information; The first and second read control signals corresponding to the first and second bank groups are generated by reflecting the first latency reflected in the address information in the read operation in the bank information, and reflected in the address information in the write operation. Control signal generation means for generating first and second write control signals corresponding to the first and second bank groups by reflecting the second latency to be in the bank information; First address driving means for driving a first transmission line corresponding to the first bank group in response to the first read control signal, the first write control signal, and the address information in the read operation and the write operation; And Second address driving means for driving a second transmission line corresponding to the second bank group in response to the second read control signal, the second write control signal, and the address information in the read operation and the write operation; A semiconductor memory device having a. The method of claim 10, And the first latency reflected in the address information in the read operation is additive latency. The method of claim 11, And the second latency reflected in the address information in the write operation is a write latency. The method of claim 12, And the write latency includes the additive latency and the cascade latency. The method of claim 13, The control signal generating means, A latency reflecting unit for reflecting the first and second latencies in the bank information; And a control signal output unit configured to output the first and second read control signals and the first and second write control signals in response to an output signal of the latency reflecting unit. The method of claim 14, The latency reflecting unit, A latching unit for latching the bank information in the read operation and the write operation; A first latency reflecting unit for reflecting and outputting the first latency to an output signal of the latching unit; And And a second latency reflecting unit for reflecting and outputting the second latency to an output signal of the latching unit. The method of claim 15, The first latency reflecting unit, A plurality of shifting parts for shifting the output signal of the latching part in response to a clock signal; And a multiplexer for selectively outputting the output signals of the plurality of shifting parts in response to the additive latency. The method of claim 15, The second latency reflecting unit, A plurality of shifting units for shifting the output signal of the first latency reflecting unit in response to a clock signal; And a multiplexer for selectively outputting the output signals of the plurality of shifting parts in response to the cas latency. The method of claim 10, And one of the first and second read control signals is activated in response to the bank information, and one of the first and second read control signals is activated in response to the bank information. . The method of claim 10, A plurality of decoding means for selecting a memory cell corresponding to each of the plurality of banks and corresponding to a signal transmitted through the first or second transmission line among a plurality of memory cells included in each of the plurality of banks A semiconductor memory device comprising: The method of claim 19, And the plurality of decoding means corresponding to the first and second bank groups, respectively, share the first or second transmission line. The method of claim 10, The bank information may distinguish the first bank group from the second bank group. The method of claim 10, And the address information includes a plurality of address signals. The method of claim 14, And the first and second address driving means have a number corresponding to the plurality of address signals. The method of claim 22, The first and second address driving means, respectively, A read address input unit for receiving a corresponding address signal applied during a read operation in response to the bank information; A write address input unit for receiving a corresponding address signal applied during a write operation in response to the bank information; And And an address output unit configured to receive the output signals of the read address input unit and the write address input unit, latch the output signals, and output them to a corresponding transmission line. The method of claim 24, The read and write address input unit, respectively, A transfer unit for transferring the corresponding address signal applied during the operation to the address output unit; And an activation unit for activating the transfer unit in response to the bank information in the corresponding operation. The method of claim 24, And the address output unit drives a corresponding transmission line according to the bank information.

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