KR100948163B1 - Semiconductor package and method for manufacturing thereof - Google Patents

Abstract

A semiconductor package and a method of manufacturing the same are disclosed. Providing a molding frame in which a through hole is formed and a semiconductor chip having an electrode formed on one surface thereof and a protective layer formed on a portion of one surface of the electrode so that the electrode is electrically connected to the outside; Inserting a semiconductor chip into the through-hole facing the surface; filling an insulating material between the molding frame and the semiconductor chip to fix the semiconductor chip to the molding frame; and forming a heat sink on the other surface of the molding frame to cover the other surface of the semiconductor chip. And forming a first via in the protective layer so as to be electrically connected to the electrode, thereby preventing a risk that the electrode of the semiconductor chip may be damaged due to laser drill processing, It is not necessary to form conductive bumps to protect the electrodes, while reducing the number of buildup layers.

Semiconductor, Package, Protective Layer, Buildup Layer

Description

Semiconductor package and method for manufacturing

The present invention relates to a semiconductor package and a method of manufacturing the same.

The semiconductor package is a technology for efficiently packaging devices used in electronic products, and includes chip packaging technology for bonding and electrically connecting the cut semiconductor chips to a substrate and modularizing them. In package technology, the package technology for surface mount is small and has excellent electrical performance. In recent years, high-density packaging technology and peripheral mounting technology have been applied to form a surface mount type such as ball grid array (BGA) and chip scale package (CSP). It is rapidly developing into a smile and light weight trend.

In a conventional embedded package or BGA package, a via hole is formed in the first build up layer, and electrical is formed between the chip pad and the circuit pattern formed on the buildup layer through the via. By forming the conductive portion, it was possible to eliminate the use of solder balls, which may cause reliability and environmental problems.

However, in the conventional embedded package or BGA package process, in processing the via hole using a laser drill, the process risk that the chip pad may be damaged and the difficulty of adjusting the position precision for laser processing There has been a problem.

Accordingly, there is a demand for a semiconductor package and a method of manufacturing the same, which can prevent the risk of chip pad damage caused by laser drilling and reduce the number of buildup layers.

The present invention prevents the risk that the electrodes of the semiconductor chip may be damaged due to laser drilling, thereby eliminating the need to form conductive bumps for protecting the electrodes of the semiconductor chip, and at the same time, reducing the number of buildup layers. It is to provide a package and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a molding frame in which a through hole is formed, and a semiconductor chip having a protective layer formed on a portion of one surface thereof so that an electrode is formed on one surface and the electrode is electrically connected to the outside. Inserting a semiconductor chip into the through-hole so that the electrode faces one surface of the molding frame, and filling an insulating material between the molding frame and the semiconductor chip to fix the semiconductor chip to the molding frame, and molding the cover to the other surface of the semiconductor chip. A method of manufacturing a semiconductor package is provided, the method including forming a heat sink on the other surface of a frame, and forming a first via in a protective layer to be electrically connected to an electrode.

The inserting of the semiconductor chip may include inserting the semiconductor chip into the through hole such that one surface of the protective layer and one surface of the molding frame are on the same plane.

The molding frame may include a base layer and an insulating layer formed on one surface of the base layer, and the inserting of the semiconductor chip may include inserting the semiconductor chip into the through hole so that the electrode faces one surface of the insulating layer. .

The method may further include laminating a fixing film on one surface of the molding frame before inserting the semiconductor chip, and after fixing the semiconductor chip, removing the fixing film.

After forming the first via, forming a buildup layer on one surface of the molding frame to cover one surface of the semiconductor chip, and forming a second via in the buildup layer to be electrically connected to the first via. It may include.

The buildup layer and the second via may be formed in plural, and the second via may be formed in the buildup layer, respectively.

After forming the second via, the method may further include forming a bump on one surface of the build-up layer to be electrically connected to the second via.

The buildup layer is made of a thermoplastic resin, and after forming the bumps, further includes heating and removing the buildup layer, forming the buildup layer, forming the second vias, and forming the bumps. Can be performed again.

In addition, according to another aspect of the present invention, a molding frame in which a through hole is formed, a semiconductor chip having an electrode formed on one surface thereof and inserted into the through hole so that the electrode faces one surface of the molding frame, and the electrode is electrically connected to the outside. A protective layer formed on a portion of one surface of the semiconductor chip, an insulating material interposed between the molding frame and the semiconductor chip to fix the semiconductor chip to the molding frame, and formed on the other surface of the molding frame to cover the other surface of the semiconductor chip. A semiconductor package including a heat sink and a first via formed in a protective layer to be electrically connected to an electrode is provided.

One surface of the protective layer and one surface of the molding frame may be inserted into the through hole to be located on the same plane.

The molding frame includes a base layer and an insulating layer formed on one surface of the base layer, and the semiconductor chip may be inserted such that an electrode faces one surface of the insulating layer.

The semiconductor device may further include a buildup layer formed on one surface of the molding frame to cover one surface of the semiconductor chip, and a second via formed in the buildup layer to be electrically connected to the first via.

The buildup layer and the second via may be formed in plural, and the second via may be formed in the buildup layer, respectively.

A bump may be further formed on one surface of the build-up layer to be electrically connected to the second via.

The build up layer may be made of thermoplastic resin.

Is formed on one surface of the semiconductor chip so that a portion of the electrode is exposed, is formed on one surface of the intervening protective layer interposed between the semiconductor chip and the protective layer, and interposed between the semiconductor chip and the protective layer, between the semiconductor chip and the protective layer It may further include an intervening redistribution layer.

According to the embodiment of the present invention, it is not necessary to form the conductive bumps to protect the electrodes of the semiconductor chip by preventing the risk that the electrodes of the semiconductor chip may be damaged due to laser drilling, and at the same time, the number of buildup layers is increased. Can be reduced.

An embodiment of a semiconductor package and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings. The description will be omitted.

In addition, terms such as first and second used below are merely identification symbols for distinguishing the same or corresponding components, and the same or corresponding components are limited by terms such as the first and second components. no.

1 is a flow chart showing a first embodiment of a semiconductor package manufacturing method according to an aspect of the present invention, Figures 2 to 12 is a cross-sectional view showing each process of the first embodiment of the semiconductor package manufacturing method according to an aspect of the present invention. to be.

1 to 12, a semiconductor package 100, a molding frame 110, a through hole 116, an insulating layer 112, a base layer 114, a fixed film 115, and a semiconductor chip. 120, an electrode 122, a protective layer 130, an insulating material 135, a heat sink 140, the first via 150, a build up layer 160, a second via ( 165, solder resist 170, bump pad 180, and bump 185 are shown.

According to the present exemplary embodiment, the first via 150 is formed in the passivation layer 130 formed on one surface of the semiconductor chip 120, whereby the electrode 122 of the semiconductor chip 120 is formed by a laser drill. The damage problem can be prevented, and at the same time, a method of manufacturing the semiconductor package 100 can be provided that can simplify the process by reducing the number of build-up layers 160.

First, as shown in FIGS. 2 and 3, a through hole is formed, a molding frame including a base layer and an insulating layer, and an electrode is formed on one surface and a protective layer is formed on a portion of one surface of the electrode to be electrically connected to the outside. To provide a chip (S100).

As shown in FIG. 2, a through hole 116 may be formed in the molding frame 110, and may include a base layer 114 and an insulating layer 112 formed therein. Since a predetermined circuit pattern may be formed on one surface of the insulating layer 112 to be electrically connected to the first via 150 formed in the protective layer 130, the electrode 122 of the semiconductor chip 120 may be insulated. It may be inserted to face one side of layer 112.

In the present embodiment, the case where the molding frame 110 is composed of a base layer 114 and the insulating layer 112 as an example, but in addition to this case, the molding frame 110, for example, made of only an insulating material Of course, it can be included in the scope of the present invention.

In this case, the base layer 114 may be made of a material other than an insulating material, and when the base layer 114 is made of a material such as copper (Cu) or silicon (Si) used as the heat sink 140, operating heat of the semiconductor chip 120. It can be removed by more easily passing to the outside.

The molding frame 110 forms an insulating layer 112 such as, for example, polyimide on one surface of the base layer 114, and then perforates the base layer 114 and the insulating layer 112. By forming the through hole 116 can be manufactured.

In addition, after the through hole 116 is first formed in the base layer 114, an insulating layer 112 such as, for example, polyimide is formed and, if necessary, deburring and debrising. It may also be prepared through a post-treatment process such as debris.

As illustrated in FIG. 3, in the semiconductor chip 120, an electrode 122 is formed on one surface thereof, and a protective layer 130 may be formed on a portion of one surface of the semiconductor chip 120 to be electrically connected to the outside. That is, since the protective layer 130 may be formed to expose a portion of the electrode 122 of the semiconductor chip 120, the first via 150 may be formed in the protective layer 130 to be electrically connected to the electrode 122. Can be formed.

In this embodiment, a case in which the protective layer 130 is formed to expose a portion of the electrode 122 on one surface of the semiconductor chip 120 is described as an example. Similarly, the interlayer protective layer (490 of FIG. 29) formed on one surface of the semiconductor chip (420 of FIG. 9) and the electrode (422 of FIG. 29) may be electrically connected to expose a portion of the electrode (422 of FIG. 29). It is formed on one surface of the interlayer protective layer (490 of FIG. 29) so that a portion of the redistribution layer (495 of FIG. 29) and a portion of the redistribution layer (495 of FIG. 29) are formed on one surface of the intervening protective layer (490 of FIG. 29). Of course, the semiconductor chip (420 of FIG. 29) having the protective layer (430 of FIG. 29) formed thereon may be included in the scope of the present invention.

Next, as shown in Figure 4, the fixing film is laminated on one surface of the molding frame (S110). One surface of the protective layer 130 and one surface of the insulating layer 112 may be temporarily stacked on the molding frame 110 to insert and align the semiconductor chip 120 to be positioned on the same plane, where fixed The film 115 may use, for example, a heat resistant film that leaves no residue upon removal.

Next, as shown in FIG. 5, the semiconductor chip is inserted into the through hole so that the electrode faces one surface of the molding frame (S130). That is, the molding frame 110 may include a base layer 114 and an insulating layer 112 formed thereon, and the insulating layer 112 may be electrically connected to the electrode 122 of the semiconductor chip 120. Since the circuit pattern may be formed, the semiconductor chip 120 may be inserted so that the electrode 122 faces the one surface of the insulating layer 112.

In this case, the semiconductor chip 120 is positioned on the same plane in which one surface of the protective layer 130 formed on one surface of the semiconductor chip 120 and one surface of the molding frame 110, that is, one surface of the insulating layer 112. As a result, the insulating layer 112 and the protective layer 130 may be used as the first layer for the build-up, thereby manufacturing the semiconductor package 100 more easily.

Next, as shown in FIG. 6, an insulating material is filled between the molding frame and the semiconductor chip to fix the semiconductor chip to the molding frame (S130). Encapsulating the semiconductor chip 120 in the molding frame 110 to fix the semiconductor chip 120 to the molding frame 110. The through-hole 116 and the inserted semiconductor chip 120 of the molding frame 110 are fixed. It can be performed by filling the insulating material 135 in the space between).

Next, as shown in FIG. 7, the heat sink 140 is formed on the other surface of the molding frame to cover the other surface of the semiconductor chip (S140). The heat sink 140 may emit heat generated during the operation of the semiconductor chip 120 to the outside, and is deposited on the surface of the copper plate, the metal plate, the silicon plate, the metal foil, the copper foil, and the metal layer. Silicon sheet material or the like.

As such, the heat sink 140 covers the other surface of the semiconductor chip 120 and is laminated on the other surface of the molding frame 110, thereby preventing malfunction or failure of the semiconductor chip 120 due to operating heat.

In the present exemplary embodiment, a case in which the heat sink 140 is stacked on the front surface of the other surface of the molding frame 110 is illustrated as an example, but a part of the other surface of the molding frame 110 including the other surface of the semiconductor chip 120 is provided. Of course, the heat sink 140 may also be included in the scope of the present invention.

Next, as shown in Figure 8, to remove the fixed film (S150). The fixing film 115 may be temporarily stacked on the molding frame 110 to align the semiconductor chip 120 so that one surface of the protective layer 130 and one surface of the insulating layer 112 are on the same plane. Therefore, after the semiconductor chip 120 is fixed to the molding frame 110 by the insulating material 135 and the heat sink 140, the fixing film 115 may be removed.

Next, as shown in FIG. 9, the first via is formed in the protective layer to be electrically connected to the electrode (S160). That is, the first via 150 may be formed to electrically connect the semiconductor chip 120 to the outside. Accordingly, as in the related art, a layer for building up is formed on the semiconductor chip 120 and the layer is formed. By forming a via hole by using a laser drill, it is possible to prevent a risk of damaging the electrode 122 of the semiconductor chip 120.

In addition, in order to prevent the risk of damaging the electrode 122 by the laser drill, the process of forming the conductive bumps 185 formed on the electrode 122 can be omitted. 100) can be prepared.

The first via 150 may be formed by, for example, a semi-additive method. First, a seed layer is formed on one surface of the protective layer 130 and one surface of the insulating layer 112 by electroless plating, and a plating resist is formed to expose the electrode 122, and then the plating resist is not formed. As the conductive material is electroplated on the part and the seed layer is removed through micro etching, the first via 150 may be formed. In addition, various methods such as an additive method may be used.

Next, as shown in FIG. 10, a buildup layer is formed on one surface of the molding frame to cover one surface of the semiconductor chip (S170), and a second via is formed on the buildup layer to be electrically connected to the first via (S180).

The build-up layer 160 and the second via 165 may be formed in plural according to the design of the semiconductor package 100, and the second via 165 may be formed in the build-up layer 160, respectively. In the case of this embodiment, the build-up layer 160 is formed of two layers, and two second vias 165 will be described.

First, the buildup layer 160 may be formed on one surface of the molding frame 110 to cover one surface of the semiconductor chip 120 and the first via 150. The build-up layer 160 may be made of an insulating material, and when made of a thermoplastic resin, when a defect occurs, the build-up layer 160 may be removed and reworked. A second embodiment will be described later.

Subsequently, a via hole is formed in the build-up layer 160 to form a second via electrically connected to the first via 150. The second via 165 may be formed by first drilling a via hole corresponding to the position of the first via 150 in the build-up layer 160, and then plating a conductive material in the via hole, thereby forming a build-up layer ( Both surfaces of the 160 may be electrically connected to each other to electrically connect the semiconductor chip 120 to the outside.

As shown in FIG. 10, two build-up layers 160 and two second vias 165 may be formed, and thus the above-described process may be repeatedly performed.

Finally, as shown in FIGS. 11 and 12, bumps are formed on one surface of the build-up layer to be electrically connected to the second via (S190). First, as shown in FIG. 11, the solder resist 170 is formed to expose the second via 165 formed on the uppermost layer, and the bump pad 180 is electrically connected to the second via 165. In this case, the bump pad 180 may be made of gold. For example, the bump pad 180 may be formed using electroplating.

Next, as illustrated in FIG. 12, bumps 185 may be formed on the bump pads 180. The bump 185 may be a conductive material, for example, a solder ball, and may be formed through the bump pad 180, the second via 165, the first via 150, and the electrode 122. The semiconductor package 100 may be electrically connected to an external device.

In the case where the plurality of semiconductor chips 120 are inserted and packaged in the molding frame 110, a process of separating the semiconductor chips 120 by unit may be performed. In this case, a semiconductor package having poor electrical connection or the like may be performed. 100 may remove and reprocess the buildup layer 160, which will be described later in the second embodiment of the method for manufacturing the semiconductor package 100 according to an aspect of the present invention.

Next, a second embodiment of the semiconductor package manufacturing method according to an aspect of the present invention will be described.

13 is a flowchart illustrating a second embodiment of a method of manufacturing a semiconductor package according to an aspect of the present invention, and FIGS. 14 to 27 are cross-sectional views illustrating respective processes of the second embodiment of the method of manufacturing a semiconductor package according to an aspect of the present invention. to be.

13 to 27, the semiconductor package 200, the molding frames 210 and 210 ′, the through holes 216 and 216 ′, the insulating layers 212 and 212 ′, and the base layers 214 and 214 ′. , The fixed film 215, the semiconductor chip 220, the electrode 222, the protective layer 230, the insulating materials 235 and 235 ′, the heat sink 240 and 240 ′, the first via 250 and the build-up layer ( 260 and 260 ', second vias 265 and 265', solder resists 270 and 270 ', bump pads 280 and 280' and bumps 285 and 285 'are shown.

According to the present exemplary embodiment, when a defect occurs during the manufacturing process of the semiconductor package 200, a method of manufacturing the semiconductor package 200 that can remove the build-up layer 260 and reprocess it is provided.

First, as shown in FIGS. 14 and 15, a through-hole is formed, a molding frame formed of a base layer and an insulating layer, and an electrode is formed on one surface and a protective layer is formed on a portion of one surface of the electrode to be electrically connected to the outside. Provide a chip (S200).

Next, as shown in FIG. 16, the fixing film is laminated on one surface of the molding frame (S210), and as shown in FIG. 17, the semiconductor chip is inserted into the through hole so that the electrode faces one surface of the molding frame (S220).

Next, as shown in FIG. 18, an insulating material is filled between the molding frame and the semiconductor chip to fix the semiconductor chip to the molding frame (S230), and as shown in FIG. 19, the heat sink is formed on the other surface of the molding frame to cover the other surface of the semiconductor chip. It forms (S240).

Next, as shown in FIG. 20, the fixing film is removed (S250), and as shown in FIG. 21, a first via is formed in the protective layer to be electrically connected to the electrode (S260).

Next, as shown in FIG. 22, a buildup layer (thermoplastic) is formed on one surface of the molding frame to cover one surface of the semiconductor chip (S270), and a second via is formed on the buildup layer to be electrically connected to the first via. 23 and 24, bumps are formed on one surface of the build-up layer to be electrically connected to the second vias (S285).

Finally, as shown in FIG. 25, the buildup layer is heated and removed (S290), and as shown in FIG. 27, the buildup layer forming, the second via forming, and the bump forming process are performed again (S295).

In the present embodiment, a process of providing a molding frame 210 including an insulating layer 212 and a base layer 214, and a semiconductor chip 220 having an electrode 222 and a protective layer 230 formed thereon, and a fixed film 215. Stacking process, semiconductor chip 220 fixing process by filling insulating material 235, heat sink 240 forming process, first via 250 forming process, buildup layer 260 and second via 265 forming process, solder Since the process of forming the bumps 285 after the formation of the resist 270 and the bump pads 280 is the same as the first embodiment of the method of manufacturing the semiconductor package 200 according to an aspect of the present invention, description thereof will be omitted. Hereinafter, the process of removing the buildup layer 260, the process of forming the buildup layer 260 ′, forming the second via 265 ′, and forming the bump 285 ′ will be described.

As shown in FIG. 25, the buildup layer is heated and removed (S290).

The buildup layer 260 may be made of an insulating material, and may be made of a thermoplastic resin. Accordingly, when electrical connection defects occur during the stacking of the buildup layer 260, the formation of the second via 265, and the formation of the bumps 285, heat is applied to the buildup layer 260. After removal, the new semiconductor package 200 may be reworked.

That is, as the buildup layer 260 made of the thermoplastic resin is heated to the melting point or more, the buildup layer 260 may be removed, and as shown in FIG. 25, the first via 250 remains. The build up layer 260, the second via 265, the solder resist 270, the bump pad 280, and the bump 285 may be removed.

Next, as shown in FIG. 26, the semiconductor chip 220 may be cut and separated from the molding frame 210, inserted into the reworking molding frame 210 ′, and a heat sink 240 ′ for reworking may be formed.

Since the first via 250 may be formed to extend to the insulating layer 212 of the molding frame 210, the first via 250 may be cut to include the semiconductor chip 220 and a part of the molding frame 210 and cut from the molding frame 210. Can be separated.

In addition, the molding frame 210 ′ for reworking may be formed of a base layer 214 ′ and an insulating layer 212 ′, similarly to the molding frame 210, and the size of the through hole 216 ′ may be a molding frame 210. The through hole 216 may be larger than the size.

In addition, similar to the method described above in the first embodiment of the present invention, between the semiconductor chip 220 including a part of the molding frame 210 and the reworking molding frame 210 ′, an insulating material for reworking 235 'may be filled, and a heat sink 240' for reworking may be formed.

Lastly, as shown in FIG. 27, the process of forming the buildup layer, forming the second via, and forming the bump is performed again (S295).

Similar to the method described above in the first embodiment according to one aspect of the present invention, the rebuild build-up layer 260 ', the rework second via 265', the rework solder resist 270 ', the rework bump pads 280 ′, a rework bump 285 ′ may be formed, which may be performed by the same or corresponding method as that of the first embodiment described above, and thus a detailed description thereof will be omitted.

According to the present embodiment, when a defect such as electrical connection occurs during the manufacturing process, by heating and removing the build-up layer 360 made of a thermoplastic resin, a new semiconductor package 200 may be manufactured to reduce manufacturing and material costs. Can be.

Next, a first embodiment of a semiconductor package according to another aspect of the present invention will be described.

28 is a cross-sectional view illustrating a first embodiment of a semiconductor package according to another aspect of the present invention.

Referring to FIG. 28, the semiconductor package 300, the molding frame 310, the through hole 316, the insulating layer 312, the base layer 314, the semiconductor chip 320, the electrode 322, and the protective layer ( 330, insulation 335, heat sink 340, first via 350, build-up layer 360, second via 365, solder resist 370, bump pad 380, bump 385. Is shown.

According to the present embodiment, by using the protective layer 330 and the insulating layer 312 as the first layer for the build-up, it is possible to reduce the build-up layer 360 of the semiconductor package 300, consequently reducing the size A semiconductor package 300 can be presented.

The molding frame 310 may include a base layer 314 and an insulating layer 312 formed on one surface of the base layer 314, and a through hole 316 may be formed. Since a predetermined circuit pattern electrically connected to the first via 350 formed in the protective layer 330 may be formed on one surface of the insulating layer 312, the electrode 322 of the semiconductor chip 320 may be insulated. It may be inserted to face one side of the layer 312.

In the present embodiment, a case where the molding frame 310 is composed of a base layer 314 and the insulating layer 312 has been described as an example, in addition to this, the molding frame 310 is made of, for example, only an insulating material Of course, the case may be included in the scope of the present invention.

In this case, the base layer 314 may be made of a material other than an insulating material, and when the base layer 314 is made of a material such as copper (Cu) or silicon (Si) used as the heat sink 340, the operating heat of the semiconductor chip 320. It can be removed by more easily passing to the outside.

The molding frame 310 forms an insulating layer 312 such as, for example, polyimide on one surface of the base layer 314, and then perforates the base layer 314 and the insulating layer 312. By forming the through hole 316 can be manufactured. In addition, after the through hole 316 is formed in the base layer 314, an insulating layer 312 such as, for example, polyimide is formed, and if necessary, deburring and debrising are performed. It may also be prepared through a post-treatment process such as debris.

The semiconductor chip 320 may have an electrode 322 formed on one surface thereof and be inserted into the through hole 316 so that the electrode 322 faces one surface of the molding frame 310. That is, the molding frame 310 may include a base layer 314 and an insulating layer 312 formed on one surface thereof, and the insulating layer 312 is electrically connected to the electrode 322 of the semiconductor chip 320. Since a predetermined circuit pattern may be formed, the semiconductor chip 320 may be inserted so that the electrode 322 faces one surface of the insulating layer 312.

In the protective layer 330, the protective layer 330 may be formed on a portion of one surface of the semiconductor chip 320 such that the electrode 322 is electrically connected to the outside. That is, since the protective layer 330 may be formed to expose a portion of the electrode 322 of the semiconductor chip 320, the first via 350 may be connected to the protective layer 330 to be electrically connected to the electrode 322. Can be formed.

At this time, the semiconductor chip 320 is positioned on the same plane in which one surface of the protective layer 330 formed on one surface of the semiconductor chip 320 and one surface of the molding frame 310, that is, one surface of the insulating layer 312. As a result, the insulating layer 312 and the protective layer 330 may be used as the first layer for the build-up, thereby realizing the semiconductor package 300 having a simpler structure.

In order to arrange one surface of the protective layer 330 formed on the semiconductor chip 320 and one surface of the insulating layer 312 of the molding frame 310 on the same plane, a fixing film is laminated on one surface of the molding frame 310. Thereafter, the semiconductor chip 320 having the protective layer 330 formed thereon may be inserted into the through hole 316, and the fixing film may use, for example, a heat resistant film that does not leave a residue upon removal.

In the present exemplary embodiment, a case in which the protective layer 330 is formed to expose a portion of the electrode 322 on one surface of the semiconductor chip 320 is described as an example. In addition, the semiconductor chip 320 and The protective layer 330 and the redistribution layer may be interposed between the protective layers 330, which will be described in detail with reference to the second embodiment of the semiconductor package 300 according to another aspect of the present invention. It will be described later.

The insulating material 335 may be interposed between the molding frame 310 and the semiconductor chip 320 to fix the semiconductor chip 320 to the molding frame 310. That is, the insulating material 335 is filled in the space between the through-hole 316 of the molding frame 310 and the inserted semiconductor chip 320 to encapsulate the semiconductor chip 320 in the molding frame 310. .

Accordingly, the semiconductor chip 320 may be fixed to the molding frame 310.

The heat sink 340 may be formed on the other surface of the molding frame 310 to cover the other surface of the semiconductor chip 320. The heat sink 340 may emit heat generated during the operation of the semiconductor chip 320 to the outside, and is deposited on the surface of the copper plate, the metal plate, the silicon plate, the metal foil, the copper foil, and the metal layer. Silicon sheet material or the like.

As such, the heat sink 340 covers the other surface of the semiconductor chip 320 and is laminated on the other surface of the molding frame 310, thereby preventing malfunction or failure of the semiconductor chip 320 due to operating heat.

In the present exemplary embodiment, a case in which the heat sink 340 is stacked on the front surface of the other surface of the molding frame 310 is provided as an example, but a part of the other surface of the molding frame 310 including the other surface of the semiconductor chip 320 is provided. Of course, the heat sink 340 may also be included in the scope of the present invention.

The first via 350 may be formed in the protective layer 330 to be electrically connected to the electrode 322. That is, the first via 350 may be formed to electrically connect the semiconductor chip 320 to the outside. Accordingly, as in the related art, a layer for building up is formed on the semiconductor chip 320 and the layer is formed. By forming a via hole using a laser drill, it is possible to prevent a risk of damaging the electrode 322 of the semiconductor chip 320.

In addition, in order to prevent the risk of damaging the electrode 322 by the laser drill, the process of forming the conductive bumps 385 formed on the electrode 322 can be omitted. 300) can be prepared.

The first via 350 may be formed by, for example, a semi-additive method. First, a seed layer is formed on one surface of the protective layer 330 and one surface of the insulating layer 312 by electroless plating, and a plating resist is formed to expose the electrode 322, and then the plating resist is not formed. As the conductive material is electroplated on the portion and the seed layer is removed through micro etching, the first via 350 may be formed. In addition, various methods such as an additive method may be used.

The build-up layer 360 and the second via 365 may be formed in plural according to the design of the semiconductor package 300, and the second via 365 may be formed in the build-up layer 360, respectively. In the case of this embodiment, the build-up layer 360 is formed of two layers, and two second vias 365 will be described.

The buildup layer 360 may be formed in two layers on one surface of the molding frame 310 to cover one surface of the semiconductor chip 320 and the first via 350, that is, the semiconductor chip 320 and the first layer. The buildup layer 360 may be formed on one surface of the molding frame 310 to cover the via 350. The build-up layer 360 may be made of an insulating material. When the build-up layer 360 is made of a thermoplastic resin, when the defect occurs, the build-up layer 360 may be removed and reworked. In this regard, the method of manufacturing the semiconductor package 300 according to an aspect of the present invention may be performed. It has been described above in the second embodiment.

Two second vias 365 may be formed, and each of the second vias 365 may be formed in the buildup layer 360 to be electrically connected to the first via 350. First, the first vias may be formed in the buildup layer 360. It may be formed by drilling a via hole corresponding to the position of 350 and then plating a conductive material on the via hole.

Accordingly, both surfaces of the build-up layer 360 may be electrically connected to each other to electrically connect the semiconductor chip 320 to the outside.

The bump 385 may be formed on one surface of the build-up layer 360 to be electrically connected to the second via 365. The bump 385 may be, for example, a solder ball as a conductive material, and may be formed through the bump pad 380, the second via 365, the first via 350, and the electrode 322. The semiconductor package 300 and an external device may be electrically connected to each other. In order to form the bumps 385, first, a solder resist 370 and a bump pad 380 may be formed.

First, the solder resist 370 is formed to expose the second vias 365 formed on the uppermost layer, and the bump pads 380 electrically connected to the second vias 365 are formed. Then, the bump pads 380 are formed on the bump pads 380. Bumps 385 may be formed. In this case, the bump pad 380 may be made of gold, and for example, the bump pad 380 may be formed using electroplating.

Next, a second embodiment of a semiconductor package according to another aspect of the present invention will be described.

29 is a cross-sectional view illustrating a second embodiment of a semiconductor package according to another aspect of the present invention.

Referring to FIG. 29, a semiconductor package 400, a molding frame 410, a through hole 416, an insulating layer 412, a base layer 314, a semiconductor chip 420, an electrode 422, and a protective layer ( 430, insulating material 435, heat sink 440, first via 450, build-up layer 460, second via 465, solder resist 470, bump pad 480, bump 485, Interposed protective layer 490 and redistribution layer 495 are shown.

According to the present exemplary embodiment, a degree of freedom in design is provided by interposing the protective layer 490 and the redistribution layer 495 between the protective layer 430 and one surface of the semiconductor chip 420. The elevated semiconductor package 400 is presented.

In the present embodiment, the molding frame 410, the insulating layer 412, the base layer 314, the semiconductor chip 420, the electrode 422, the insulating material 435, the heat sink 440, and the first via 450. The configuration of the build-up layer 460, the second via 465, the solder resist 470, the bump pad 480, and the bump 485 may be performed by the first embodiment of the semiconductor package 400 according to another aspect of the present disclosure. Since the description is the same as or corresponding to the example, a description thereof will be omitted. Hereinafter, the interlayer protective layer 490, the redistribution layer 495, and the difference from the first embodiment of the semiconductor package 400 according to another aspect of the present invention will be omitted. The protective layer 430 will be described.

The interlayer protective layer 490 may be formed on one surface of the semiconductor chip 420 to expose a portion of the electrode 422 of the semiconductor chip 420, and may be interposed between the semiconductor chip 420 and the protective layer 430. have.

The redistribution layer 495 may be formed on one surface of the interlayer protective layer 490 to be electrically connected to the electrode 422 of the semiconductor chip 420, and may be interposed between the semiconductor chip 420 and the protective layer 430. In addition, since the redistribution layer 495 may be electrically connected to the first via 450, the electrode 422 and the first via 450 of the semiconductor chip 420 may be electrically connected through the redistribution layer 495. have.

As the intervening passivation layer 490 and the redistribution layer 495 are formed, the positions of the electrodes 422 of the semiconductor chip 420 may be redistributed, and thus, the positions of the electrodes 422 in the semiconductor package 400 design. Regardless of whether you want to increase your design freedom.

The protective layer 430 may be formed on one surface of the redistribution layer 495 so that a portion of the redistribution layer 495 is exposed, and the first via may be formed in the protective layer 430 to be electrically connected to the redistribution layer 495. Since the 450 may be formed, the electrode 422 of the semiconductor chip 420 may be electrically connected to the outside through the redistribution layer 495, the first via 450, the second via 465, and the bump 485. Can be.

Many embodiments other than the above-described embodiments are within the scope of the claims of the present invention.

1 is a flow chart showing a first embodiment of a method for manufacturing a semiconductor package according to an aspect of the present invention.

2 to 12 are cross-sectional views showing respective processes of the first embodiment of the method for manufacturing a semiconductor package according to one aspect of the present invention.

13 is a flow chart showing a second embodiment of a method of manufacturing a semiconductor package according to one aspect of the present invention.

14 to 27 are cross-sectional views showing respective steps of the second embodiment of the method for manufacturing a semiconductor package according to one aspect of the present invention.

28 is a cross-sectional view showing a first embodiment of a semiconductor package according to another aspect of the present invention.

29 is a sectional view showing a second embodiment of a semiconductor package according to another aspect of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: semiconductor package 110: molding frame

112: insulating layer 114: base layer

116: through hole 115: fixing film

120: semiconductor chip 122: electrode

130: protective layer 135: insulating material

140: heat sink 150: the first via

160: build up layer 165: second via

170: solder resist 180: bump pad

185: bump

Claims (16)

Providing a semiconductor chip having an electrode formed on one surface thereof and a protective layer selectively opening the electrode; Stacking a fixing film on one surface of a molding frame in which a through hole is formed; Inserting the semiconductor chip into the through hole so that the protective layer is supported by the fixing film so that one surface of the protective layer and one surface of the molding frame are on the same plane; Fixing the semiconductor chip to the molding frame by filling an insulating material between the molding frame and the semiconductor chip; Forming a heat sink on the other surface of the molding frame to cover the other surface of the semiconductor chip; Removing the fixing film to expose the protective layer and the electrode; And Forming a first via and a circuit pattern directly connected to the electrode in the protective layer. delete The method of claim 1, The molding frame, A base layer; A semiconductor package manufacturing method comprising an insulating layer formed on one surface of the base layer. delete The method of claim 1, After forming the first via, Forming a buildup layer on one surface of the molding frame to cover one surface of the semiconductor chip; And Forming a second via in the build-up layer to be electrically connected to the first via. The method of claim 5, The build-up layer and the second via are formed in plural, and the second via is formed in the build-up layer, respectively. The method of claim 5, After forming the second via, And forming a bump on one surface of the build-up layer to be electrically connected to the second via. The method of claim 7, wherein The build up layer is made of a thermoplastic resin, After the step of forming the bump, Heating and removing the buildup layer; Forming a buildup layer on one surface of the molding frame to cover one surface of the semiconductor chip; And And forming a second via in the re-formed buildup layer to be electrically connected to the first via. A molding frame in which a through hole is formed; A semiconductor chip including an electrode and a protective layer for selectively opening the electrode, the semiconductor chip being inserted into the through hole so that one surface of the protective layer and the molding frame is disposed on the same plane; An insulating material interposed between the molding frame and the semiconductor chip to fix the semiconductor chip to the molding frame; A heat sink formed on the other surface of the molding frame to cover the other surface of the semiconductor chip; A first via formed in the passivation layer to be directly connected to the electrode; And a circuit pattern formed on a surface of the protective layer and electrically connected to the first via. delete The method of claim 9, The molding frame, A base layer; And an insulating layer formed on one surface of the base layer. The method of claim 9, A buildup layer formed on one surface of the molding frame to cover one surface of the semiconductor chip; And a second via formed in the buildup layer to be electrically connected to the first via. The method of claim 12, The build-up layer and the second via are formed in plural, and the second via is formed in the build-up layer, respectively. The method of claim 12, And a bump formed on one surface of the buildup layer to be electrically connected to the second via. The method of claim 14, The build-up layer is a semiconductor package, characterized in that made of a thermoplastic resin. The method of claim 9, An interim protective layer formed on one surface of the semiconductor chip to expose a portion of the electrode and interposed between the semiconductor chip and the protective layer; And a redistribution layer formed on one surface of the intervening passivation layer to be electrically connected to the electrode and interposed between the semiconductor chip and the passivation layer.

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