KR100945818B1 - Circuit and Method of Controlling Precharge in Semiconductor Memory Apparatus - Google Patents

Abstract

The precharge control circuit of the semiconductor memory device of the present invention includes a read clock driver for driving an internal clock to generate a read burst clock; A write clock driver configured to drive the internal clock to generate a write burst clock in response to a read write mode signal and a data input off signal, and to disable the write burst clock when the data input off signal is enabled; And precharge control means for generating an auto precharge signal using the read burst clock during a read operation and the write burst clock during a write operation.

Semiconductor Memory Device, Precharge, Light

Description

Circuit and Method of Controlling Precharge in Semiconductor Memory Apparatus

The present invention relates to a semiconductor memory device, and more particularly, to a precharge control circuit and method of a semiconductor memory device.

In general, a semiconductor memory device receives a command from an external device and performs active and precharge operations. The semiconductor memory device performs a read operation or a write operation during an active operation. The semiconductor memory device outputs data from a memory cell during a read operation and inputs data into the memory cell during a write operation. When one active operation is completed, signals remain in the bit line and each data I / O line that performed the data input / output operation. It can be done smoothly. Therefore, the semiconductor memory device includes a precharge control circuit to precharge each signal line between active periods.

One precharge control circuit of a semiconductor memory device is provided for each memory bank. It has a configuration for generating a precharge signal. To this end, the precharge control circuit includes a read precharge control means and a write precharge control means. That is, the precharge control circuit generates a burst clock using an internal clock and generates a read auto precharge signal from the burst clock and burst length information during a read operation using a read precharge control means. Meanwhile, a write auto precharge signal is generated from the burst clock, burst length information, and write latency information during a write operation using a write precharge control means. Thereafter, the read auto precharge signal, the write auto precharge signal, and the bank information are combined to generate an auto precharge signal and transmit the auto precharge signal to the corresponding memory bank.

Referring to FIG. 1, a read write mode signal rdwt that distinguishes a read operation from a write operation, a data input off signal dioff indicating a section in which data is not input, and a waveform of the burst clock bclk can be seen. have. Here, the read write mode signal rdwt indicates a read operation mode at a low level and a write operation mode at a high level. The data input off signal dioff is a signal that is enabled at a high level in a period in which data is not input to the memory bank, that is, in an All Bank Idle mode or a refresh mode. The burst clock bclk is a clock signal input to the read precharge control means and the write precharge control means.

In the period in which the read write mode signal rdwt is at a low level, that is, in the read operation mode, the write precharge control means does not need to be activated. In addition, since the data input operation is not substantially performed even in the section in which the data input off signal dioff is enabled, the write precharge control means does not need to be activated. However, as shown in the drawing, the burst clock bclk is implemented in a form of continuously toggling, and as the activated burst clock bclk is input to the write precharge control means, the light precharge is performed. The result is that the charge control means is also activated.

As described above, the conventional precharge control circuit of the semiconductor memory device has a configuration in which the write precharge control means is activated even in a situation where the write operation mode is not implemented, thereby causing power consumption. In addition, since the precharge control circuit is provided as many as the number of memory banks, the power consumption described above adversely affects the power efficiency of the entire semiconductor memory device. In order to reduce the power consumption of the semiconductor memory device, it is necessary to prevent the flow of current generated in the precharge control circuit like this, and for this reason, a new technology configuration for reducing the power consumption is required.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and there is a technical problem to provide a precharge control circuit and method for a semiconductor memory device with reduced power consumption.

According to one or more exemplary embodiments, a precharge control circuit of a semiconductor memory device may include: a read clock driver configured to drive an internal clock to generate a read burst clock; A write clock driver configured to drive the internal clock to generate a write burst clock in response to a read write mode signal and a data input off signal, and to disable the write burst clock when the data input off signal is enabled; And precharge control means for generating an auto precharge signal by using the read burst clock during a read operation and by using the write burst clock during a write operation.

According to another aspect of the present invention, there is provided a method of controlling a precharge circuit of a semiconductor memory device, the method comprising: a) driving an internal clock to generate a read burst clock; b) In the read operation, auto precharge using the burst end signal, which is a signal enabled in the form of a pulse when a predetermined burst length has elapsed during the read burst clock, the bank active signal, and the data input / output operation of the semiconductor memory device. Generating a signal; c) during a write operation, determining whether to provide the internal clock as a toggled light burst clock in response to a data input off signal; And d) generating the auto precharge signal using the write burst clock, the burst end signal, and the bank active signal.

The precharge control circuit and method of the semiconductor memory device of the present invention creates an effect of reducing power consumption by stopping the operation of the circuit configuration for the write precharge operation during the read operation.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2 is a block diagram illustrating a configuration of a precharge control circuit of a semiconductor memory device according to an embodiment of the present invention.

As shown, the precharge control circuit includes a read clock driver 10 which drives an internal clock clk_int to generate a read burst clock rd_bclk; Read precharge control means 20 for generating a read auto precharge signal rdpcg in response to the read burst clock rd_bclk, the burst end signal bstend, the read write mode signal rdwt, and the reset signal rst. ; A write clock driver 30 driving the internal clock clk_int to generate a write burst clock wt_bclk in response to the read write mode signal rdwt and a data input off signal dioff; Write auto in response to the write burst clock bclk_wt, the burst end signal bstend, the reset signal rst, the write latency signal wltc, the write address combination signal wac, and the bank address signal badd. Write precharge control means (40) for generating a precharge signal (wtpcg); And auto precharge by combining the read auto precharge signal rdpcg and the write auto precharge signal wtpcg in response to a bank active signal ba, a command pulse signal cmp, and a precharge delay signal pcgdly. And a precharge signal generating means 50 for generating a signal pcg.

The internal clock clk_int driven by the read clock driver 10 and the write clock driver 30 to generate the read burst clock rd_bclk and the write burst clock wt_bclk, respectively, is external to the semiconductor memory device. As a clock signal input through a buffer from a, it is one of the clock signal used in various fields in the semiconductor memory device. The read clock driver 10 has a configuration that can be easily implemented in the form of a general clock driver.

The burst end signal bstend is a signal for applying a preset burst length to the precharge control circuit during a data input / output operation of a semiconductor memory device. The burst termination signal bstend is enabled in a pulse form when a predetermined burst length has elapsed. to be. The read precharge control means 20 initializes the state of the read auto precharge signal rdpcg when the reset signal rst is enabled in the form of a pulse. Subsequently, when the read write mode signal rdwt indicates a read operation mode, the burst stop signal bstend is delayed by a predetermined time in response to the read burst clock rd_bclk, so that the read auto precharge signal ( rdpcg).

The write clock driver 30 operates the internal clock clk_int to generate the write burst clock wt_bclk, wherein the read write mode signal rdwt indicates a read operation mode or inputs the data. It is not activated when the off signal dioff is enabled. In this case, the data input off signal dioff is a signal that is enabled at a high level in a section in which data is not input to the memory bank, that is, in an all bank idle mode or a refresh mode. That is, the write clock driver 30 is activated only when the data input operation is substantially performed in the write operation mode, and performs the operation to periodically toggle the write burst clock wt_bclk.

The light latency signal wltc is a signal for causing the light precharge control means 40 to perform an operation according to a preset light latency. The write latency signal wltc is a combination of a plurality of signals, and may be implemented such that only one signal is enabled according to the length of the write latency. The write address combination signal wac is a signal generated by combining an address indicating an all bank precharge or auto precharge operation with the read write mode signal rdwt. This signal is enabled in all bank precharge or auto precharge mode before the write operation. On the other hand, the bank address signal badd is a signal indicating whether the corresponding memory bank is activated, and the write precharge control means 40 may be activated only when the bank address signal badd is enabled. .

The write precharge control means 40 resets the burst end signal in response to the write burst clock wt_bclk after the reset signal rst is enabled to initialize the state of the write auto precharge signal wtpcg. Delay (bstend) The write precharge control means 40 may be implemented in the form of a shift register, and shifts the burst end signal bstend for several periods of the write burst clock wt_bclk as the write auto precharge signal wtpcg. Whether to output is determined by the write latency signal wltc.

As such, the write precharge control means 40 performs an operation of shifting the burst end signal bstend by using the write burst clock wt_bclk. In the read operation mode, the light auto precharge signal wtpcg is not substantially generated, but the above-described shifting operation may be continuously performed in the light precharge control means 40. As described above, when the write precharge control means 40 performs the above-described shifting operation in the read operation mode or in the period in which the data input operation does not occur substantially, unnecessary power consumption is caused. However, the write clock driver 30 of the present invention is deactivated in a period where the data input operation does not occur substantially so that the write burst clock wt_bclk is not toggled so that the write precharge control means 40 is activated. Therefore, unnecessary power consumption of the precharge control circuit can be reduced.

The precharge signal generating means 50 performs an OR operation on the read auto precharge signal rdpcg and the write auto precharge signal wtpcg. Thereafter, the signal generated by the OR operation is output as the auto precharge signal pcg under the control of the bank active signal ba, the command pulse signal cmp, and the precharge delay signal pcgdly. In this case, the bank active signal ba is a signal enabled when the memory bank is in an active mode or a refresh mode, and the command pulse signal cmp is a signal indicating a read operation and a write operation of the memory bank. The precharge delay signal pcg is a signal for improving the stability of the precharge operation by delaying the generation of the auto precharge signal pcg until the time when the precharge command is substantially performed after the precharge command is input. .

Here, the lead precharge control means 20, the write precharge control means 40, and the precharge signal generation means 50 may be collectively referred to as precharge control means 60. That is, the precharge control means 60 generates the auto precharge signal using the read burst clock during a read operation and the write burst clock during a write operation.

FIG. 3 is a circuit diagram showing the detailed configuration of the write clock driver shown in FIG.

As illustrated, the write clock driver 30 combines the read write mode signal rdwt and the data input off signal dioff to generate a clock enable signal clken 310. ); And a clock driver 320 driving the internal clock clk_int to generate the write burst clock wt_bclk in response to the clock enable signal clken.

The clock enable unit 310 includes: an inverter (IV) for receiving the data input off signal (dioff); And a NAND gate ND configured to receive the read write mode signal rdwt and the output signal of the inverter IV and output the clock enable signal clken.

The clock driver 320 includes a gate (NR) for receiving the internal clock (clk_int) and the clock enable signal (clken) and outputting the write burst clock (wt_bclk).

In the write clock driver 30 configured as described above, the clock enable signal clken is implemented as a low enable signal.

The clock enable unit 310 disables the clock enable signal clken to a high level when the read write mode signal rdwt indicates a read operation mode as a low level. The clock enable signal clken is also disabled when the data input off signal dioff is enabled at a high level. In this case, the clock driver 320 disables the write burst clock wt_bclk regardless of the input of the internal clock clk_int.

On the other hand, the clock enable unit 310 indicates the write operation mode as the read write mode signal rdwt is high level, and the clock enable when the data input off signal dioff is disabled to the low level. Enable the signal (clken). In this case, the write burst clock wt_bclk output from the clock driver 320 has a form in which the internal clock clk_int is inverted and delayed.

4 is a timing diagram for explaining the operation of the precharge control circuit of the semiconductor memory device of the present invention.

The waveforms of the read write mode signal rdwt, the data input off signal dioff, and the write burst clock wt_bclk are shown in the drawing.

As shown, the write burst clock wt_bclk is toggled during a write operation, that is, when the read write mode signal rdwt is at a high level. However, in this case, when the data input off signal dioff is enabled, the write burst clock wt_bclk is disabled to a low level.

During the read operation, that is, when the read write mode signal rdwt is at the low level, the write burst clock wt_bclk is disabled regardless of the state of the data input off signal dioff.

As such, the write burst clock wt_bclk is activated only when an operation of actually inputting data occurs. Comparing the waveform of the write burst clock wt_bclk with FIG. 1 showing the prior art, the power consumption reduction effect according to the present invention can be more easily understood.

As described above, the precharge control circuit of the semiconductor memory device of the present invention causes the write burst clock to be disabled in a section in which the data input operation does not occur substantially, thereby causing the write precharge control means to be deactivated and unnecessary. Reduce power consumption Since the write clock driver and the write precharge control means are provided as many as the number of memory banks, by disabling the write burst clock according to the interval, the semiconductor memory device can generate a significant power consumption reduction effect.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a timing diagram for explaining the operation of a precharge control circuit of a conventional semiconductor memory device;

2 is a block diagram illustrating a configuration of a precharge control circuit of a semiconductor memory device according to an embodiment of the present invention;

3 is a circuit diagram showing a detailed configuration of the write clock driver shown in FIG. 2;

4 is a timing diagram for explaining the operation of the precharge control circuit of the semiconductor memory device of the present invention.

<Description of the symbols for the main parts of the drawings>

10: lead clock driver 20: lead precharge control means

30: light clock driver 40: light precharge control means

50: precharge signal generating means

Claims (9)

A read clock driver for driving an internal clock to generate a read burst clock; A write clock driver configured to drive the internal clock to generate a write burst clock in response to a read write mode signal and a data input off signal, and to disable the write burst clock when the data input off signal is enabled; And And a precharge control means for generating an auto precharge signal using the read burst clock during a read operation and using the write burst clock during a write operation. The method of claim 1, The write clock driver is configured to toggle the write burst clock when the read write mode signal indicates a write operation mode and the data input off signal is disabled. Circuit. The method of claim 1, The precharge control means, Read precharge control means for generating a read auto precharge signal in response to the read burst clock, the burst end signal, and the read write mode signal; Write precharge control means for generating a write auto precharge signal in response to the write burst clock, the burst end signal, write latency signal, and write address combination signal; And Precharge signal generation means for generating an auto precharge signal by combining the read auto precharge signal and the write auto precharge signal in response to a bank active signal, a command pulse signal, and a precharge delay signal; A precharge control circuit of a semiconductor memory device comprising a. The method of claim 3, wherein The read precharge control means is configured to delay the burst end signal for a predetermined time and output the read auto precharge signal in response to the read burst clock when the read write mode signal indicates a read operation mode. A precharge control circuit of a semiconductor memory device. The method of claim 3, wherein And the write precharge control means is configured to shift the burst end signal in response to the write burst clock for a time indicated by the write latency signal to output the write auto precharge signal. Precharge control circuit. The method of claim 3, wherein The precharge signal generating means performs an OR operation on the read auto precharge signal and the write auto precharge signal, and then performs the OR operation under the control of the bank active signal, the command pulse signal and the precharge delay signal. And output the signal generated by the auto precharge signal as the auto precharge signal. a) driving an internal clock to generate a read burst clock; b) In the read operation, auto precharge using the burst end signal, which is a signal enabled in the form of a pulse when a predetermined burst length has elapsed during the read burst clock, the bank active signal, and the data input / output operation of the semiconductor memory device. Generating a signal; c) during a write operation, determining whether to provide the internal clock as a toggled light burst clock in response to a data input off signal; And d) generating the auto precharge signal using the write burst clock, the burst end signal, and the bank active signal. The method of claim 7, wherein And c) deactivating the write burst clock when the data input off signal is enabled during a write operation. The method of claim 8, C), c-1) generating a clock enable signal in response to whether the write operation is performed and the data input off signal; And c-2) driving the internal clock to generate the write burst clock in response to the clock enable signal; Precharge control method of a semiconductor memory device comprising a.

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