KR100943079B1 - Apparatus for ethernet interfacing - Google Patents

Abstract

An interface device between an Ethernet network communication device connected via an optical cable and an Ethernet switch or router is disclosed. In an interface device of an Ethernet network communication device and a network relay device, the interface device of the present invention receives a single communication channel signal from the network relay device and performs routing or forwarding to process a single communication channel signal having a restored Ethernet frame. A network processing unit for routing or forwarding the data to the network relay apparatus; The Ethernet frame of the single communication channel signal received from the network processing unit is divided into a plurality of fragment frames, and each of the divided fragment frames is assigned to any one of the plurality of communication channels, and the line decoded fragment frames of the plurality of communication channel signals A media access processor for generating the restored Ethernet frame and transferring a single communication channel signal having the restored Ethernet frame to the network processor; And a physical layer processor configured to perform photoelectric conversion and line decoding of the signal received from the network processor, and line coding and all-optical conversion of the plurality of communication channel signals.

Ethernet interface, media access control

Description

Ethernet interface device {Apparatus for ethernet interfacing}

The present invention relates to an Ethernet interface technology, and more particularly to a technology for interfacing an Ethernet network communication device connected through an optical cable and a network relay device such as an Ethernet switch or a router.

The present invention is derived from the research conducted as part of the IT growth engine technology development project of the Ministry of Information and Communication and the Ministry of Information and Telecommunications Research and Development (Task Management Number: 2005-S-102-03, Task name: Carrier-class Ethernet technology development).

Various local area network (LAN) communication technologies, which were applied only in a limited area of a local area network, are being converted to Ethernet communication technology, which is cost-competitive for performance. Ethernet communication is widely used in the enterprise such as campus, enterprise, etc., as well as home appliances and home networking.

The Internet dedicated line service market for enterprises and small businesses is shifting from the existing communication methods such as ATM / SDH (Asynchronous Transfer Mode / Synchronous Digital Hierarchy) to low-cost carrier-class Ethernet communication. The Internet service market for subscribers, which began with xDSL (x Digital Subscriber Line) communication technology, has also recently shifted to Ethernet-based broadband access network technologies such as Ethernet Passive Optical Network (EPON) and Apartment LAN.

A business is underway to transform the 10 Gigabit Ethernet network communication environment into a 40 Gigabit Ethernet network communication environment.

The existing 10 Gigabit dedicated fiber cable has been replaced by a ribbon fiber cable capable of supporting multiple channels through a single fiber cable, and an Ethernet transmission system for 40 Gigabit is being installed. Accordingly, an Ethernet network interface device for interfacing Ethernet network communication equipment connected through an optical cable to an Ethernet switch fabric or the like should also be replaced for 40 gigabit.

The present invention has been derived in consideration of a method for minimizing the existing Ethernet technology resources (software and hardware, etc.) to change the communication environment at a low cost. Accordingly, it has been noted that by making minor changes to the existing 10 Gigabit Ethernet network equipment, the Ethernet network communication equipment and the Ethernet switch fabric can be interfaced.

Meanwhile, an Ethernet-based physical interface (eg, 10 / 100Mbps Ethernet and 1 / 10Gbps Ethernet) is used as one interface, and there is an 802.1ad link aggregation technology. The 802.1ad link aggregation technology is performed by the operation of the link aggregation control protocol existing in the link aggregation sublayer, which is a higher layer of the media access control layer.

However, according to the software interface aggregation method based on the protocol, the interface is aggregated logically only through a higher protocol (for example, TCP / IP) rather than directly dealing with the physical interface. You can't always provide twice the bandwidth. In addition, since link aggregation is processed based on a protocol, there is a problem in that a packet processing delay for protocol processing (eg, request / response) occurs.

The technical problem to be achieved by the present invention is to provide an Ethernet interface device that can interface a network relay device such as Ethernet network communication equipment and Ethernet switch fabric by modifying only a part of the Ethernet interface device in order to switch the communication environment at a low cost will be.

Another technical problem to be solved by the present invention is to interface with an Ethernet network, by using a method of directly dealing with a physical interface by excluding an interface processing method by a higher layer based on a protocol, and efficiently using communication resources and delaying packet processing. It is to provide an Ethernet interface device that can prevent.

According to an aspect of the present invention, in an interface device between an Ethernet network communication device and a network relay device, a single communication channel signal is received from the network relay device for routing or forwarding, and a single communication channel having a restored Ethernet frame. A network processor for routing or forwarding signals to the network relay apparatus; The Ethernet frame of the single communication channel signal received from the network processing unit is divided into a plurality of fragment frames, and each of the divided fragment frames is assigned to any one of the plurality of communication channels, and the line decoded fragment frames of the plurality of communication channel signals A media access processor for generating the restored Ethernet frame and transferring a single communication channel signal having the restored Ethernet frame to the network processor; And a physical layer processor configured to perform photoelectric conversion and line decoding of the signal received from the network processor, and line coding and all-optical conversion of the plurality of communication channel signals.

As described above, according to a characteristic aspect of the present invention, the present invention provides an interface between an existing Ethernet physical layer equipment and a newly established Ethernet network equipment so that the existing Ethernet network resources can be used as it is. do.

In addition, the existing Ethernet physical layer equipment and the like can be used as it is without developing a physical layer equipment for a large amount of Ethernet communication newly installed.

In addition, the present invention can effectively use communication resources and prevent packet processing delays by using a method of directly handling a physical interface and excluding an interface processing method by a higher layer based on a protocol in interfacing an Ethernet network. .

In addition, the present invention divides an Ethernet frame of a single communication channel into n fragment frames, and allocates each divided fragment frame to any one of the n communication channels. In addition, n communication channel signals implemented from each fragment frame are transmitted to a small amount of Ethernet physical layer processing equipment through a communication cable. Therefore, the logical interface aggregation method and the protocol processing method are eliminated, and by using the physical interface aggregation method, communication resources can be efficiently used and packet processing delay for protocol processing can be prevented.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First of all, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings. In describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

1 is a view showing an Ethernet interface device according to an embodiment of the present invention, Figure 2 is a view showing a frame configuration of a single channel signal and a fragment frame configuration of a four-channel signal in accordance with an embodiment of the present invention; 3 is a diagram illustrating an interface between a media access processor and a physical layer processor according to an exemplary embodiment of the present invention. Hereinafter, with reference to the accompanying drawings will be described.

Reference numeral 100 denotes a configuration diagram of a 40 Gigabit Ethernet interface device, which is composed of a physical layer processor 110, a medium connection processor 120, and a network processor 130.

Reference numeral 111 denotes a quad 10 Gigabit Ethernet transponder (QSFP) provided in the physical layer processing unit 110, and reference numeral 112 denotes a quad 10 gigabit Ethernet transceiver provided in the physical layer processing unit 110 ( Quad 10GbE Transceiver). Reference numeral 121 denotes a frame division and recovery unit 120 provided in the media access processing unit 120.

The physical layer processor 110 performs a physical layer communication with a corresponding physical layer processor provided in the Ethernet network communication device 150. Therefore, the basic implementation technology itself of the physical layer processing unit 110 corresponds to those known to those skilled in the art. As is well known, physical layer processing of Ethernet communication can be largely divided into opto-electric conversion operations, line coding and line decoding operations. Line coding and line decoding is to convert the error or error-resistant signal and restore the converted signal back to the original signal in order to minimize the error or error of the signal transmitted through the optical cable.

As described above, the physical layer processor 110 includes a quad 10 Gigabit Ethernet transponder 111 and a quad 10 Gigabit Ethernet transceiver 112 to provide 40 Gbps bandwidth. The 4-channel 10 Gigabit Ethernet signal received through the ribbon optical fiber cable 140 is transmitted to the medium access processing unit 120 via a path provided by the physical layer processing unit 110 operating independently per channel. For example, the quad 10 Gigabit Ethernet transponder 111 and the quad 10 Gigabit Ethernet transceiver 112 may be implemented as a four-channel 10 Gigabit Serial Electrical Interface (XFI). In addition, for example, the medium access processing unit 120 and the physical layer processing unit 110 may be implemented as a four-channel 10 Gigabit Attachment Unit Interface (XAUI). XFI and XAUI are standard specification interfaces in the field of Ethernet communication and are known to those skilled in the art.

Quad 10 Gigabit Ethernet transponder 111 is a 4 channel optical fiber of 10.3125Gbps transmission level received from Ethernet network communication equipment 150 via ribbon optical fiber cable (optical cable capable of supporting multi channel through one cable) 140. Opto-electrical conversion for each signal. The quad 10 Gigabit Ethernet transponder 111 delivers the photo-electrically converted signal to the quad 10 Gigabit Ethernet transceiver 112 through XFI, which is composed of a 1 bit differential signal of 10.3125 Gbps per channel.

In addition, the quad 10 Gigabit Ethernet transponder 111 performs an electro-optical conversion operation on the 4-channel signal transmitted from the quad 10 Gigabit Ethernet transceiver 112 through the XAUI consisting of a 4-bit differential signal of 3.125 Gbps per channel. This is transmitted to the Ethernet network communication equipment 150 through the ribbon optical fiber cable 140.

Quad 10 Gigabit Ethernet Transceiver 112 provides bit clock and data recovery, 1:16 demultiplexing, for 10.3125 Gbps 1-bit differential signals on each of the four channels received via XFI from Quad 10 Gigabit Ethernet Transponder 111. Descrambling, 66B / 64B decoding, 8B / 10B coding, and 10: 1 multiplexing are performed sequentially. The quad 10 Gigabit Ethernet transceiver 112 transmits the line decoded 4-channel signal to the medium access processor 120 as described above through the 4-channel XAUI composed of 4-bit differential signals of 3.125 Gbps per channel. In addition, the quad 10 Gigabit Ethernet transceiver 112 performs line coding on the 4-channel signal transmitted from the media access processor 120 through the 4-channel XAUI, and transmits the 4-channel XAUI to the quad 10 Gigabit Ethernet transponder 111 through the 4-channel XFI. To pass.

The medium access processing unit 120 maps one communication channel of a large transmission amount and n communication channels of a small transmission amount in order to interface a signal format having a different transmission amount. For example, a signal format of one channel of 40 Gbps is mapped to a signal format of four channels of 10 Gbps. In this case, for example, a signal of one channel of 40 Gbps class is a signal recognized in an upper layer, and a signal format of four channels of 10 Gbps class is implemented as a signal recognized in a lower layer.

Therefore, by changing the media connection processing unit in hardware, it is possible to interface with signals having different formats.

From the standpoint of the network processor 130 corresponding to the upper layer, the signal is transmitted and received on a single communication channel, while the single channel signal from the network processor 130 is divided and mapped into n channel signals. The n channel signals from the physical layer processor 110 are mapped to a single channel signal.

The medium access processing unit 120 performs a 1:10 reverse on a 4-bit (also referred to as 4 lane) differential signal of 3.125 Gbps received from the quad 10 Gigabit Ethernet transceiver 112 of the physical layer processing unit 110 through the 4-channel XAUI. Fragmentation frames 220, 230, 240, and 250 are generated from each channel signal by performing multiplexing, bit lane alignment, and 10B / 8B decoding, and buffered therein are received buffers (see 331 (not shown in FIG. 1)). (See Figure 3). The frame recovery and division unit 121 of the medium access processing unit 120 refers to the 40 Gigabit Ethernet frame 210 by referring to the sequence number 14b of the header portion of the fragment frame of each channel buffered in the reception buffer 331. It restores and transmits it to the network processing unit 130 through SPI-5 (System Packet Interface Level-5) composed of 16-bit differential signals of 2.488Gbps ~ 3.125Gbps.

In addition, the medium access processing unit 120 is a preamble, a start of frame delimiter, MAC data frame (MAC Data Frame) of the packet transmitted from the network processing unit 130 through the SPI-5 Gigabit Ethernet frame format 210 is configured. In addition, the frame restoration and dividing unit 121 of the medium access processing unit 120 has a variable length (minimum 8 bytes to maximum 128 bytes) corresponding to 4 channels of 10 Gigabit Ethernet of the physical layer processing unit 110 for a 40 Gigabit Ethernet frame. The fragments are divided into fragment frames 220, 230, 240, and 250 having fragment headers 260 having four different values, respectively, and are buffered in the transmission buffer 332 (not shown in FIG. 1).

The media access processor 120 allocates a fragment frame to one of four communication channels, generates four communication channel signals, and transmits the four communication channel signals to the physical layer processor 110 through the four-channel XAUI. In this case, for example, the fragment frame 220 transmitted through the 10 Gigabit Ethernet channel 1 is a 10 Gigabit Ethernet Media Independent Interface (XGMII) of the 156.25 MHz clock, 4-bit control signal, 32-bit data signal through the transmission buffer 332 Mapped to signal group.

In addition, the media access processing unit 120 generates and transmits a four-channel signal from the channel-specific fragment frames 220, 230, 240, and 250 of the transmission buffer 332. Is passed to channel 1 block 333 of the quad 10 Gigabit Ethernet transceiver 112 via XAUI of 3.125 Gbps, 4-bit (also known as 4-lane) differential signals, via 8B / 10B encoding, 10: 1 multiplexing. (See Figure 3).

At this time, the fragment header unit 260 is 10 Gigabit Ethernet standard IEEE 802.3 2005 Standard Edition, Clause 46 Reconciliation Sublayer (RS) and 10 Gigabit Ethernet Media Independent Interface (GMII), Table 46-5. Since it can be delivered using Sequence_Order_Sets, the existing 10 Gigabit Ethernet physical layer means can be used as it is.

The network processor 130 performs a layer operation higher than that of the media access layer. The network processor 130 is connected to a network relay device such as a switch 140 or a router (not shown) of a 40 Gigabit Ethernet network to transmit and receive packet data. Basically, the network processor 130 performs packet processing for forwarding or routing (Modification and Editing for Forwarding / Routing).

Also, for example, the network processor 130 may perform packet classification, ingress admissioin control, forwarding, or routing on 40 Gigabit Ethernet packets received from the media access processor 120 through SPI-5. Packet Processing for Quality of Service / Class of Service, Multicast Processing, IP Fragmentation and Reassembly (Modification and Editing for Forwarding / Routing) After performing Fragment and Reassembly, statistical information management, and the like, the packet is transmitted to the switch fabric 140 provided in the 40 Gigabit Ethernet network through the Fabric Interface (FI).

In addition, for example, the network processing unit 130 may classify the packet into the 40 Gigabit Ethernet packet received from the switch fabric 140 provided in the 40 Gigabit Ethernet network through the Fabric Interface (FI). Ingress Admissioin Control, Modulation and Editing for Forwarding / Routing, Traffic Management for Quality of Service / Class of Service, Multicast ) Processing, IP fragmentation and reassembly, statistical information management, and the like, and then the data is transmitted to the media access processor 120 through SPI-5.

2 is a diagram illustrating a frame configuration of a single channel signal and a fragment frame configuration of a four channel signal according to an embodiment of the present invention.

Reference numeral 210 denotes a structure of a 40 gigabit Ethernet frame, reference numeral 220 denotes a structure of a fragment frame for a 10 gigabit Ethernet channel 1 signal, and reference numeral 230 denotes a structure diagram of a fragment frame for a 10 gigabit Ethernet channel 2 signal. 240 is a structural diagram of a fragment frame for a 10 Gigabit Ethernet channel 3 signal, reference numeral 250 is a structural diagram of a conch frame for a 10 Gigabit Ethernet channel 4 signal.

In the figure, the first MAC data frame is divided into the first four fragment frames (reference 1). The second MAC data frame is divided into the second four fragment frames (reference 2).

Reference numeral 260 denotes a header portion of the fragment frame. The fragment frame includes a header portion 260 and a main body portion. The header portion 260 includes an 8-bit Void bit 261, a 14-bit sequence number 262, and a 1-bit Start of Packet bit 263. 1 bit End of Packet bit 264 and 8 bit Cyclic Redundancy Check bit 265.

Sequence number 262 represents the sequence information of the fragment frame for restoring to an Ethernet frame of a single communication channel signal. When the 40 Gigabit Ethernet frame 210 is divided into fragment frames 220, 230, 240, and 250, a sequentially increasing value (0-2 ^14-1 ) is assigned to the sequence number 262 of each fragment frame. do. Conversely, when the fragment frames 220, 230, 240, 250 are restored to the 40 gigabit Ethernet frame 210, they can be assembled in sequence 262 of sequence numbers.

The Start of Packet bit 263 is used when the fragment frame (any one of fragment frame 1 to fragment frame 8 in the example of FIG. 2) refers to the start frame of the 40 Gigabit Ethernet frame, and the End of Packet bit 264 is The fragment frame (any one of the fragment frames 1 to 8 in the example of FIG. 2) is used when referring to the last frame of the 40 gigabit Ethernet frame.

For example, if (S, E) = (1,0), the fragment frame is the start of a 40 Gigabit Ethernet frame, and if (S, E) = (0, 1), the fragment frame is 40 Gigabit Ethernet End of frame If (S, E) = (0, 0), the fragment frame is the content in the middle of some of the 40 Gigabit Ethernet frames. Cyclic Redundancy Check bit 265 is used to detect bit errors in fragment frames.

According to a preferred embodiment of the present invention, in order to interface signal formats with different transmission amounts, one communication channel of a large transmission amount and n communication channels of a small transmission amount are mapped. For example, a signal format of one channel of 40 Gbps is mapped to a signal format of four channels of 10 Gbps. In this case, for example, a signal of one channel of 40 Gbps class is a signal recognized in an upper layer, and a signal format of four channels of 10 Gbps class is implemented as a signal recognized in a lower layer.

On the other hand, in the detailed description of the present invention has been described with respect to specific embodiments, various modifications are of course possible without departing from the scope of the invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents thereof.

1 is a view showing an Ethernet interface device according to an embodiment of the present invention.

2 illustrates a frame configuration of a single channel signal and a fragment frame configuration of a four channel signal according to an embodiment of the present invention.

3 is a diagram illustrating an interface between a media access processor and a physical layer processor according to an exemplary embodiment of the present invention.

<Description of main parts of drawing>

100: Ethernet interface device

130: network processing unit 120: media access processing unit

110: physical layer processing unit

Claims (4)

In the interface device between the Ethernet network communication equipment and the network relay device, A network processor configured to receive a single communication channel signal from the network relay device and perform routing or forwarding, and to route or forward a single communication channel signal having a restored Ethernet frame to the network relay device; The Ethernet frame of the single communication channel signal received from the network processing unit is divided into a plurality of fragment frames, and each of the divided fragment frames is assigned to any one of the plurality of communication channels, and the line decoded fragment frames of the plurality of communication channel signals A media access processor for generating the restored Ethernet frame and transferring a single communication channel signal having the restored Ethernet frame to the network processor; And And a physical layer processor configured to perform photoelectric conversion and line decoding of the signal received from the network processor, and line coding and all-optical conversion of the plurality of communication channel signals. The method of claim 1, wherein the physical layer processing unit, The line coding is performed on the plurality of communication channel signals transmitted from the medium access processing unit, and the line decoding is performed on the plurality of communication channel signals transmitted from the Ethernet network communication device and the photoelectric conversion is transmitted to the medium access processing unit. An Ethernet transceiver; And Electro-optical conversion of a plurality of communication channel signals transmitted from the Ethernet transceiver to the Ethernet network communication equipment through a ribbon fiber optic cable, and a plurality of communication channel signals received from the Ethernet network communication equipment through a ribbon fiber optic cable. And an Ethernet transponder for converting the optical-electricity to the Ethernet transceiver. The method of claim 1, The engraving frame is It comprises a header part and a main body part; The header unit, And the sequence information of the fragment frame for restoring the Ethernet frame of the single communication channel signal. The method according to any one of claims 1 to 3, The network relay device is an Ethernet interface device, characterized in that the Ethernet switch or router.

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