KR100942969B1 - Analog Delay Locked Loop and Operating Method of same, Circuit and Method for Clock Data Recovery, Phase Locked Loop and Operating Method of same - Google Patents

Abstract

The present invention relates to an analog delay locked loop and a method of operating the same, a clock data recovery circuit and a clock data recovery method, a phase locked loop, and an operation method thereof for reducing a fixed time at a low frequency. A flag signal generator configured to generate a flag signal enabled according to a time remaining before the delay lock loop is fixed; And a clock alignment unit that adjusts a delay amount of the internal clock to align an internal clock with an external clock, and adjusts a change width of the delay amount in response to the flag signal in the process of adjusting the delay amount.

Delay-Locked Loop, Analog, Clock Data Recovery, Phase Locked Loop

Description

Analog delay locked loop and its operation method, clock data recovery circuit and clock data recovery method, phase locked loop and its operation method {Analog Delay Locked Loop and Operating Method of same, Circuit and Method for Clock Data Recovery, Phase Locked Loop and Operating Method Method of same}

The present invention relates to an analog delay locked loop (Analog DLL), a clock data recovery circuit (CDR circuit) and a phase locked loop (PLL). The present invention relates to an analog delay locked loop, a clock data recovery circuit, and a phase locked loop, which can reduce a fixed time even at a low frequency clock.

First, the delay locked loop shows that synchronous semiconductor devices such as DRAMs that operate in synchronization with an external clock generate an internal clock using a clock buffer and a clock driver. Delay, and the operation performance of the semiconductor device is thereby deteriorated. That is, the data access time of the semiconductor device is increased by a predetermined delay time due to the clock buffer inside the chip.

Therefore, a circuit for generating an internal clock synchronized with an external clock inside the chip is provided, wherein the circuit used is a delay locked loop. Typically, the delay lock loop is classified into an analog delay lock loop and a digital delay lock loop according to a method of synchronizing an internal clock to an external clock.

Analog delay locked loops have better jitter characteristics than digital delay locked loops, and they are often used in semiconductor devices using high frequency clocks such as high speed DRAM.

1 is a block diagram of a conventional analog delay locked loop.

A conventional analog delay lock loop is output from a delay model unit 140 and a delay model unit 140 for modeling a delay amount delayed when an external clock (not shown) is buffered with an internal clock CLK. Phase comparison unit 100 for comparing the phase of the clock and the internal clock CLK, a charge pump unit for outputting a charging current (discharging current) in response to the output of the phase comparison unit 100 ( 110, the loop filter unit 120 for outputting the control voltage Vcontrol in response to the charging current and the discharge current, and the delay model unit by adjusting the delay value of the internal clock CLK in response to the control voltage Vcontrol. It is configured to include a voltage control delay line unit 130 to output to 140.

In operation, the phase comparator 100 compares the phase of the fed back clock CLK_feed and the internal clock CLK and outputs an up / down signal. The charge pump unit 110 outputs a charging current or a discharge current in response to an up / down signal, and the loop filter unit 120 outputs a control voltage Vcontrol that changes according to the charging current discharge current. Finally, the voltage control delay line unit 130 adjusts the delay value of the internal clock CLK according to the value of the control voltage Vcontrol. That is, the delay value is adjusted so that the internal clock CLK is synchronized with the external clock.

Now, the clock data recovery circuit will be described. As communication systems between chips become faster and larger in capacity, direct and high speed systems are required. Due to hardware complexity, power, and price, the transmitter transmits only the data information except the clock to synchronize with the receiver. At this time, the receiving end needs a clock that can accurately recover the distorted data due to the limited channel bandwidth. The necessity of such a clock becomes larger when transferring a large amount of data, and a structure that generates a stable clock synchronized with the received data has a great effect on the performance of the system. Accordingly, a clock data recovery circuit (CDR) for extracting a synchronized stable clock from data having a high data rate is used.

2 is a configuration diagram of a conventional clock data recovery circuit.

The conventional clock data recovery circuit includes a voltage control delay line unit 220, a phase comparator 230, a charge pump unit 240, a loop filter unit 250, and a data restoration unit 260. In general, the clock supplied from the phase locked loop 210 is used.

A phase locked loop (PLL) 210 outputs a stable clock having a constant frequency to the voltage control delay line unit 220.

The voltage controlled delay line (VCDL) 220 receives a clock output from the phase locked loop 210 and adjusts a delay value of the clock according to the input voltage Vcontrol. The voltage control delay line unit 220 is inputted in the form of a voltage (Vcontrol) through the charge pump unit 240, the loop filter unit 250, the data generated from the phase comparison unit 230 and the timing of the clock. The voltage control delay line unit 220 adjusts the timing of the data and the clock by delaying the clock based on the information.

The phase comparator 230 receives a clock and data DATA outputted from the voltage control delay line unit 220, compares the phase of the data DATA and the clock, and updates the information up / down (UP / DN). Output to the charge pump unit 240 as a signal.

The charge pump 240 receives the up / down (UOP / DN) signal output from the phase comparator 230 and receives a charging current or a discharging current from the loop filter unit. 250).

The loop filter unit 250 outputs the current received from the charge pump unit 240 to the voltage control delay line unit 220 as a voltage Vcontrol having a gradual change, and thus the voltage control delay line unit 220. Determine the delay value of).

The data restoring unit 260 restores and outputs data DATA using a clock whose delay value is output from the voltage control delay line unit 220. Here, recovering data means to latch (or catch) and output data using a clock aligned with the data.

In summary, the clock data recovery circuit CDR adjusts the rising edge of the clock output from the phase locked loop 210 to be aligned with the center of the data pulse. The data is recovered and output using a clock aligned with the data.

FIG. 3 is a diagram illustrating a clock aligned with data through a clock data recovery circuit, and as shown in FIG. 3, data is restored using a clock aligned with the data.

4 is a block diagram of a conventional phase locked loop.

The conventional phase locked loop includes a phase / frequency comparison unit 410, a charge pump unit 420, a loop filter unit 430, and a voltage controlled oscillator 440 as shown in the drawing.

The phase / frequency comparison unit 410 compares the phase / frequency of the input clock REF_CLK and the output clock CLK. The charge pump unit 420 outputs a charging current or a discharging current according to the comparison result of the phase / frequency comparison unit 410, and the loop filter unit 430 is connected to the charging current and the discharge current. And discharges a control voltage (Vcontrol) whose voltage is changed. The voltage controlled oscillator (VCO) 440 outputs a clock CLK having a frequency determined by the control voltage Vcontrol.

That is, the phase locked loop compares the input clock REF_CLK and the output clock CLK to generate a stable output clock CLK having a constant frequency.

As shown in Figs. 1,2 and 4, the clock data recovery circuit, the analog delay locked loop, and the phase locked loop have similar configurations. However, the clock data recovery circuit synchronizes the clock and data (adjust the delay value), the analog delay lock loop synchronizes the internal and external clocks (adjust the delay value), and the phase lock loop adjusts the frequency of the output clock. The basic principles are similar.

Analog delay locked loops generally have good jitter characteristics, so they are often used in high speed memories despite their complexity. Analog delay locked loops designed for high speed (high frequency) can have different characteristics at low frequencies. For example, jitter or locking time.

At low frequencies, one period of the clock is longer, so the delay value until it is fixed must be larger. That is, the analog delay locked loop and the clock data recovery circuit have a problem in that a locking time is increased during low frequency operation. This problem becomes larger as analog delay locked loops, clock data recovery circuits, and phase locked loops designed to target high frequencies.

The present invention has been proposed to solve the above problems of the prior art, and its object is to reduce the locking time of the analog delay locked loop, clock data recovery circuit, and phase locked loop. In particular, an object of the present invention is to provide an analog delay locked loop, a clock data recovery circuit, and a phase locked loop in which a fixed time does not increase even in a low frequency operation.

Analog delay lock loop according to the present invention for achieving the above object, the flag signal generation unit for generating a flag signal that is enabled according to the time remaining before the delay lock loop fixed; And a clock alignment unit that adjusts a delay amount of the internal clock to align an internal clock with an external clock, and adjusts a change width of the delay amount in response to the flag signal in the process of adjusting the delay amount.

In detail, a delay model unit for modeling a delay time between the internal clock and the external clock; A phase comparator comparing the output of the delay model and a phase of an internal clock; A charge pump unit configured to output a charge current or a discharge current in response to the output of the phase comparison unit; A loop filter unit outputting a control voltage in response to the charging current and the discharge current; And a voltage control delay line unit configured to adjust a delay value of the internal clock in response to the control voltage and output the delayed value to the delay model unit. The charge pump unit may adjust the amount of current of the charging current and the discharge current in response to the flag signal. Alternatively, the loop filter unit may be charged or discharged in response to the charging current or the discharge current, and includes two or more capacitors for outputting the control voltage, and at least one of the two or more capacitors responds to the flag signal. It may be characterized in that the on / off.

In accordance with another aspect of the present invention, there is provided a method of operating a delay locked loop, the method including generating a flag signal enabled according to a time remaining before the delay locked loop is fixed; Comparing the phase of the internal clock with the feedback clock; Outputting a control voltage according to the comparison result, and controlling a change width of the control voltage in response to the flag signal in the process of adjusting the control voltage; Adjusting a delay value of the internal clock in response to the control voltage; And delaying the internal clock of which the delay value is adjusted by a predetermined time to feed back the feedback clock.

The outputting of the control voltage may include: outputting a charging current or a discharging current according to the comparison result, and the current outputting step may be determined according to the flag signal; And a voltage output step of outputting a control voltage which is charged and discharged by the charging current or the discharge current and whose potential is determined. Alternatively, the outputting of the control voltage may include outputting a charging current or a discharge current according to the comparison result; And a control voltage which is charged and discharged according to the charging current or the discharge current and whose potential is determined, and the degree of change in the potential of the control voltage according to the charging discharge is determined according to the flag signal. It may be characterized by including the step.

A clock data recovery circuit according to the present invention includes a flag signal generation unit for generating a flag signal enabled according to a time remaining before the clock data recovery circuit is fixed; A clock data alignment unit which adjusts a delay amount of the clock to align a clock and data, and adjusts a change width of the delay amount in response to the flag signal in adjusting the delay amount; And a data restoration unit for restoring the data by using a clock whose delay value is adjusted through the clock data alignment unit.

In detail, the clock data sorting unit may include: a phase comparing unit comparing the phase of the data and the clock fed back from the voltage control delay line unit; A charge pump unit configured to output a charge current or a discharge current in response to the output of the phase comparison unit; A loop filter unit outputting a control voltage in response to the charging current and the discharge current; And the voltage control delay line adjusting the delay value of the clock in response to the control voltage and transferring the delayed value of the clock to the data recovery unit and the phase comparator. The charge pump unit may adjust the amount of current of the charging current and the discharge current in response to the flag signal. Alternatively, the loop filter unit may be charged or discharged in response to the charging current or the discharge current, and includes two or more capacitors for outputting the control voltage, and at least one of the two or more capacitors responds to the flag signal. It may be characterized in that the on / off.

The clock data recovery method according to the present invention comprises the steps of: generating a flag signal enabled according to the time remaining until the clock data recovery circuit is fixed; Comparing the phase of the data and the fed back clock; Outputting a control voltage according to the comparison result, and controlling a change width of the control voltage in response to the flag signal in the process of adjusting the control voltage; Adjusting a delay value of the clock in response to the control voltage, and feeding back a clock whose delay value is adjusted as the feedback clock; And restoring the data by using the clock whose delay value is adjusted.

The outputting of the control voltage may include: outputting a charging current or a discharging current according to the comparison result, and the current outputting step may be determined according to the flag signal; And a voltage output step of outputting a control voltage which is charged and discharged by the charging current or the discharge current and whose potential is determined. Alternatively, the outputting of the control voltage may include outputting a charging current or a discharge current according to the comparison result; And outputting a control voltage which is charged and discharged according to the charging current or the discharge current and whose potential is determined, and a degree of change in the potential of the control voltage according to the charging discharge is determined according to the flag signal. It may be characterized in that it comprises a.

The phase lock loop according to the present invention includes a flag signal generation unit for generating a flag signal enabled according to a time remaining before the phase lock loop is fixed; And adjusting the frequency of the output clock by comparing the phase / frequency of an input clock and a fed back output clock to output a stable clock, and adjusting a change width of the frequency in response to the flag signal. It includes a frequency control unit.

In detail, the frequency control unit phase / frequency comparison unit for comparing the phase / frequency of the input clock and the output clock; A charge pump unit outputting a charge current or a discharge current in response to the output of the phase / frequency comparison unit; A loop filter unit outputting a control voltage in response to the charging current and the discharge current; And a voltage controlled oscillator for outputting the output clock having a frequency determined by the control voltage. The charge pump unit may adjust the amount of current of the charging current and the discharge current in response to the flag signal. Alternatively, the loop filter unit may be charged or discharged in response to the charging current or the discharge current, and includes two or more capacitors for outputting the control voltage, and at least one of the two or more capacitors responds to the flag signal. It may be characterized in that the on / off.

In accordance with another aspect of the present invention, there is provided a method of operating a phase locked loop, the method comprising: generating a flag signal enabled according to a time remaining before the phase locked loop is fixed; Comparing the phase / frequency of the input clock and the fed back output clock; Outputting a control voltage according to the comparison result, and controlling a change width of the control voltage in response to the flag signal in the process of adjusting the control voltage; And outputting the output clock having a frequency determined by the control voltage.

The outputting of the control voltage in detail may include: outputting a charging current or a discharging current according to the comparison result, and a current output step of determining the current amount according to the flag signal; And a voltage output step of outputting a control voltage charged and discharged by the charging current or the discharge current and whose potential is determined. Alternatively, the outputting of the control voltage may include outputting a charging current or a discharge current according to the comparison result; And outputting a control voltage which is charged and discharged according to the charging current or the discharge current and whose potential is determined, and a degree of change in the potential of the control voltage according to the charging discharge is determined according to the flag signal. It may include.

That is, the analog delay locked loop, the clock data recovery circuit, and the phase locked loop according to the present invention adjust their resolution according to the remaining time before their locking.

The analog delay locked loop, the clock data recovery circuit, and the phase locked loop according to the present invention adjust their resolution according to the remaining time before their locking.

That is, the control voltage is roughly changed when much time remains before the fixing, and the control voltage is finely changed when the time is left before the fixing. Therefore, there is an advantage that the correct operation while reducing the locking time (locking time).

Particularly, in the related art, when an analog delay lock loop is designed to target a high frequency, a fixed time is greatly increased during low frequency operation, but the present invention has an advantage of enabling fast fixation even during low frequency operation.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

5 is a block diagram of an analog delay locked loop according to the present invention.

The analog delay lock loop according to the present invention includes a flag signal generator 510 for generating a flag signal that is enabled according to the time remaining before the delay lock loop is locked, and an internal clock CLK. The clock alignment unit 520 adjusts the delay amount of the internal clock CLK to align the clock, and adjusts the delay variation in response to the flag signal in the process of adjusting the delay amount.

That is, a flag signal generation unit 510 which is not included in the conventional analog delay lock loop is provided to generate a flag signal having information on whether there is much time left until the lock of the delay lock loop or little. The clock alignment unit 520 corresponding to the delay locked loop adjusts the width of the delay amount change in response to the flag signal. This does not mean that the final delay amount of the clock is changed in response to the flag signal, but that the amount of delay that is changed at one time when the delay amount is changed is changed in accordance with the flag signal. That is, the resolution of the clock alignment unit 520 changes according to the flag signal.

FIG. 6 is a first detailed embodiment of the analog delay locked loop of FIG. 5.

The flag signal generator 610 may include a voltage follower 611 for receiving a control voltage Vcontrol, a control voltage Vcontrol received through the voltage follower 611, and a preset reference voltage Vref. It may be configured to include a comparator 612 to compare the and output as a flag signal (flag). The flag signal generator 610 compares the preset reference voltage Vref with the control voltage Vcontrol to determine whether there is much or less time left before the delay lock loop is locked. The higher the value of the control voltage Vcontrol, the greater the delay value of the voltage control delay line unit 650, which means that less time is required to lock than when the value of the control voltage Vcontrol is low. Means that. Since the flag signal flag in the drawing is enabled when the control voltage Vcontrol is higher than the reference voltage Vref, the enable of the flag signal means that the time before fixing remains relatively short.

The MODE signal input to the flag signal generator 610 is a signal indicating whether the analog delay lock loop is operating at a high frequency or a low frequency, and the flag signal generator 610 is enabled or disabled using this signal. It can be configured to be disabled. In the case of a system having a high speed mode and a low speed mode, a signal for distinguishing a high speed mode and a low speed mode is used internally. Therefore, this signal may be used as the MODE signal in the drawing.

The flag signal generator 610 may be used in both the high speed mode and the low speed mode, but in the low speed mode (the clock is low frequency), the flag signal generator 610 is used because the locking time increases. While the need to reduce the fixed time is more, on the other hand, since the fixed time does not take long in the high speed mode (the clock is high frequency), the need to use the flag signal generator 610 is relatively reduced. Therefore, the flag signal generator 610 of the present invention can be configured to be enabled only in a low speed mode (low frequency) using the MODE signal as shown in the figure.

The lower the frequency, the greater the amount of delay required for locking, so that the level of the control voltage Vcontrol required for locking becomes higher than at high frequencies. Therefore, when the flag signal generator 610 is used only in the low speed mode by using the MODE signal as shown in the drawing, the reference voltage Vref can be set relatively higher, so that the locking time in the low speed mode is further increased. It also has the advantage of being able to reduce it.

The clock alignment unit 520 may include a delay model unit 660 for modeling a delay time between the internal clock CLK and the external clock; A phase comparator 620 for comparing the output of the delay model unit 660 and the phase of the internal clock CLK; A charge pump unit 630 for outputting a charging current or a discharge current in response to the output of the phase comparing unit 620; A loop filter unit 640 for outputting a control voltage Vcontrol in response to a charging current and a discharge current; And a voltage control delay line unit 650 for adjusting the delay value of the internal clock in response to the control voltage Vcontrol and outputting the delayed value to the delay model unit 660. Since the charge pump unit 630 and the loop filter unit 640 generate a control voltage Vcontrol according to the comparison result of the phase comparator 620, the charge pump unit 630 and the loop filter unit 640 are called control voltage generators. That is, the clock alignment unit is composed of components similar to the conventional analog delay locked loop.

However, in the first detailed embodiment, the charge pump unit 620 receives a flag signal and adjusts the amount of charge current discharge current according to the flag signal. Whether to output the charging current or the discharge current is determined by the up / down (UP / DN) signal, which is the output of the phase comparator 610, as in the prior art, but the current amount of the charge current and the discharge current is a flag signal. Is adjusted in response to When the time until the fixed time is left large, that is, when the flag signal is disabled, the amount of current of the charge current and the discharge current is adjusted to be large, and when the time until the fixed time is short, that is, the flag signal When is enabled, the amount of current of charge current and discharge current is adjusted to be small.

In summary, since the amount of current of the charge current discharge current increases when the flag signal is disabled, the clock alignment unit 520 rapidly changes the delay value, and when the flag signal flag is enabled, the charge current discharge current of the charge current discharge current increases. Since the amount of current decreases, the clock alignment unit 520 slowly changes the delay value. That is, the resolution of the clock alignment unit 520 changes depending on whether the flag signal is enabled.

FIG. 7 is a diagram illustrating an embodiment of the charge pump unit 630 of FIG. 6.

As shown in the figure, the charge pump unit 630 is a two or more connected in parallel to receive the bias voltage (gate voltage of M2, M3, M4, M5) to its gate to supply a current into the charge pump unit 630 Pull-up transistors (M2, M3, M4, M5, four transistors because they are two mirrors) and some of the paralleled pull-up transistors (M2, M3, two mirrors). One transistor is controlled by the flag signal) and one end is connected or disconnected by the flag signal to adjust the amount of current of the charge current and the discharge current according to the flag signal.

In operation, the current of the current source ICH is mirrored by the transistors M2 and M4, and the currents of the mirrored transistors M2 and M4 are again mirrored to the transistors M3 and M5. In addition, the currents of the mirrored transistors M3 and M5 are output as a charge current or a discharge current by an up / down signal.

One end of one drain-source of the transistors M2 and M3 is disconnected or connected by a flag signal. When the flag signal is disabled, more currents are mirrored than when the transistors M2 and M3 are connected and disconnected, and as a result, the amount of charge current and discharge current increases. However, when the flag signal is enabled and the transistors M2 and M3 are disconnected, the amount of mirrored current is reduced and eventually the amount of charge current and discharge current is also reduced. That is, the current amount of the charge current and the discharge current varies depending on whether the flag signal is enabled.

Since the illustrated embodiment shows a case in which the ICH is mirrored twice, two transistors M3 and M5 of four transistors M2, M3, M4, and M5 are controlled by the flag signal. In the case of mirroring, only one of the two transistors needs to be configured to be controlled by the flag signal.

8 is a configuration diagram of another embodiment of the charge pump unit 630 of FIG. 6.

As shown in the figure, the charge pump unit 630 may include a first and second pull-up transistors M6 and M7 connected in parallel to receive a first bias voltage through its gate and supply current into the charge pump unit 630. It includes two or more pull-down transistors (M8, M9) connected in parallel to receive a two-bias voltage to its gate to leak the current of the charge pump section to the ground terminal, and some of the two or more pull-up transistors (M6, M7) (M6) One end is connected or disconnected in response to the flag signal, and some of the two or more pull-down transistors M8 and M9 are connected to or disconnected from one end in response to the flag signal, thereby charging and discharging currents. The amount of current can be adjusted.

In operation, when the flag signal is disabled, all the transistors M6, 7, 8, and 9 operate, so that the amount of current of the charge current discharge current increases. However, when the flag signal is enabled, since one end of the transistors M6 and M8 is cut off, the amount of current of the charge current and the discharge current becomes smaller than when the flag signal is disabled.

That is, the current amounts of the charge current and the discharge current are adjusted by the flag signal as in the embodiment of FIG. 8 differs from the embodiment of FIG. 7 in that the charging current discharge current is generated directly between the power supply voltage VDD and the ground voltage VSS without using a current mirror.

FIG. 9 is a second detailed embodiment of the analog delay locked loop of FIG. 5.

Unlike the first detailed embodiment of FIG. 6, the second detailed embodiment of FIG. 9 uses the loop filter unit 940 instead of the charge pump unit 930 instead of the flag signal generated by the flag signal generation unit 910. Enter

That is, in the first detailed embodiment, the resolution of the analog delay locked loop is changed by changing the amount of charge current and discharge current output from the charge pump 630 by the flag signal. In this case, the capacity of the loop filter unit 940 is changed by a flag signal to change the resolution of the analog delay locked loop.

Since the basic configuration other than the loop filter unit 940 is the same as that of the first detailed embodiment, detailed description of parts other than the loop filter 940 will be omitted.

FIG. 10 is a diagram illustrating an embodiment of the loop filter unit 940 of FIG. 9.

As shown in the figure, the loop filter unit 940 is charged or discharged in response to a charging current or a discharge current, and includes two or more capacitors C1 and C2 for outputting a control voltage Vcontrol. A part C1 of the capacitors C1 and C2 is turned on / off in response to a flag signal.

When the flag signal is disabled, the capacitor C1 is turned off. Therefore, the capacitance of the entire loop filter unit 940 is C1. When the flag signal is enabled, the capacitor C1 is turned on. Therefore, the capacitance of the entire loop filter unit 940 becomes C1 + C2. Therefore, when the flag signal is enabled, the control voltage Vcontrol changes slowly, and when the flag signal flag is disabled, the control voltage Vcontrol changes quickly. In other words, the resolution of the delay locked loop changes depending on whether the flag signal is enabled.

11 is a view showing a change in the control voltage (Vcontrol) in the analog delay lock loop according to the present invention.

As shown in the figure, when the control voltage Vcontrol is lower than the reference voltage Vref, that is, when the flag signal flag is disabled, the control voltage Vcontrol increases rapidly. However, when the control signal Vcontrol is higher than the reference voltage Vref and the flag signal is enabled, the control voltage Vcontrol gradually increases. That is, the control voltage Vcontrol is changed steeply when much time is left until the lock, and when the time until lock time is low, the control voltage Vcontrol is gently changed.

Therefore, it is advantageous to obtain excellent jitter characteristics because the control voltage Vontrol is changed in detail when the lock time is close to the lock time.

12 is a block diagram of a clock data recovery circuit according to the present invention.

The clock data recovery circuit according to the present invention includes a flag signal generation unit 1210 for generating a flag signal that is enabled according to the time remaining before the clock data recovery circuit is locked; Adjust the delay amount of the clock CLK to align the clock CLK and the data DATA, and adjust the clock data to adjust the variation of the delay amount in response to the flag signal in the process of adjusting the delay amount. Part 1220; And a data restorer 1230 which restores the data using a clock whose delay value is adjusted through the clock data sorter 1220.

That is, a flag signal generation unit 1210, which is not present in the conventional analog clock data recovery circuit, is provided to generate a flag signal having information on whether there is much time left or a little time left until the clock data recovery circuit is locked. The width of the delay amount change of the clock data alignment unit is adjusted through the flag signal. This does not mean that the final delay amount of the clock CLK is changed in response to the flag signal, but that the amount of delay that is changed at one time when the delay amount is changed is changed according to the flag signal. That is, the resolution of the clock data alignment unit 1220 changes according to the flag signal.

FIG. 13 is a first detailed embodiment of the clock data recovery circuit of FIG. 12.

The flag signal generator 1310 may be configured in the same manner as the flag signal generator 610 of the analog delay locked loop. The clock data sorter 1220 may include a phase comparator 1320 for comparing a phase of a clock and data DATA fed back from the voltage control delay line unit 1350; A charge pump unit 1330 for outputting a charging current or a discharge current in response to the output of the phase comparing unit 1320; A loop filter unit 1340 for outputting a control voltage Vcontrol in response to a charging current and a discharge current; And a voltage control delay line unit 1350 which adjusts the delay value of the clock CLK in response to the control voltage Vcontrol and transmits the delay value to the data recovery unit 1360 and the phase comparator 1320. In addition, the data restorer 1360 restores the data DATA by using a clock whose delay value is output from the voltage control delay line unit 1350. Since the charge pump unit 1330 and the loop filter unit 1340 generate a control voltage Vcontrol according to the comparison result of the phase comparator 1320, the charge pump unit 1330 and the loop filter unit 1340 are referred to as a control voltage generator.

The basic principle of speeding up the fixed time of the clock data recovery circuit in the first detailed embodiment of FIG. 13 is the same as in the first detailed embodiment (FIG. 6) of the analog delay locked loop. Accordingly, the charge pump unit 1330 is controlled by the flag signal to adjust the amount of charge current and discharge current. The charge pump unit may be configured in the same manner as the charge pump unit illustrated in FIGS. 7 and 8, and the operation thereof is also the same, and thus the detailed description thereof will be omitted.

FIG. 14 is a second detailed embodiment of the clock data recovery circuit of FIG. 12.

In the second detailed embodiment of FIG. 14, the basic principle of accelerating the fixed time of the clock data recovery circuit is the same as that of the second detailed embodiment of the analog delay locked loop (FIG. 9). Accordingly, the loop filter unit 1440 changes its capacity (capacitance) under the control of the flag signal. The loop filter unit 1440 may be configured in the same manner as the loop filter unit illustrated in FIG. 10, and the operation thereof is also the same, and thus detailed description thereof will be omitted.

15 is a configuration diagram of a phase locked loop according to the present invention.

The phase lock loop according to the present invention includes a flag signal generation unit 1510 for generating a flag signal that is enabled according to a time remaining before the phase lock loop is fixed; And adjusts the frequency of the output clock CLK by comparing the phase / frequency of the input clock CLK_REF and the fed back output clock CLK to output a stable clock, and flags the change width of the frequency in the process of adjusting the frequency. And a frequency adjusting unit 1520 that adjusts in response to a signal.

That is, a flag signal generation unit 1510, which is not included in the conventional phase lock loop, is provided to generate a flag signal having information on whether there is much time left until the lock of the phase lock loop or a little remains. Adjust the width of the frequency change amount of the frequency control unit 1520 through the (). This does not mean that the frequency of the final output clock CLK is changed in response to the flag signal, but that the amount of change of the frequency that is changed at one time when the frequency changes is changed in accordance with the flag signal. That is, the resolution of the frequency adjuster 1520 changes according to the flag signal.

FIG. 16 is a first detailed embodiment of the phase locked loop of FIG. 15.

The flag signal generator 1610 may be configured in the same manner as the flag signal generator 610 of the analog delay locked loop. However, the voltage controlled oscillator 1650 may have a higher frequency as the control voltage Vcontrol increases depending on the design, and may also increase the frequency as the control voltage Vcontrol decreases. There may be a case where the input signals of the + and-terminals of the comparator 1612 need to be interchanged.

The frequency controller 1520 may include a phase / frequency comparison unit 1620 for comparing the phase / frequency of the input clock CLK_REF and the output clock CLK; A charge pump unit 1630 for outputting a charging current or a discharge current in response to the output of the phase / frequency comparison unit 1620; A loop filter unit 1640 for outputting a control voltage Vcontrol in response to a charging current and a discharge current; And a voltage controlled oscillator unit 1650 for outputting an output clock CLK having a frequency determined by the control voltage Vcontrol. Since the charge pump unit 1630 and the loop filter unit 1640 generate a control voltage Vcontrol according to the comparison result of the phase / frequency comparison unit 1620, the charge pump unit 1630 and the loop filter unit 1640 are called control voltage generators.

The basic principle of accelerating the fixed time of the phase locked loop in the first detailed embodiment of FIG. 16 is the same as in the first detailed embodiment (FIG. 6) of the analog delay locked loop. Accordingly, the charge pump 1630 controls the amount of charge current and discharge current under the control of a flag signal. The charge pump unit may be configured in the same manner as the charge pump unit illustrated in FIGS. 7 and 8, and the operation thereof is also the same, and thus the detailed description thereof will be omitted.

FIG. 17 is a second detailed embodiment of the phase locked loop of FIG. 15.

In the second detailed embodiment of FIG. 17, the basic principle of accelerating the fixed time of the phase locked loop is the same as that of the second detailed embodiment of the analog delay locked loop (FIG. 9). Accordingly, the loop filter unit 1740 changes its capacity (capacitance) under the control of the flag signal. The loop filter unit 1740 may be configured in the same manner as the loop filter unit illustrated in FIG. 10, and the operation thereof is also the same, and thus detailed description thereof will be omitted.

As described above, the analog delay locked loop, the clock data recovery circuit, and the phase locked loop according to the present invention roughly change the control voltage when the time remaining until the fixation is large and remain until the fixation. If the time is small, the control voltage is changed in detail. Therefore, there is an advantage that the fixed operation can be guaranteed fast and accurate operation.

Referring to Figures 5, 6, and 9 again looks at with respect to the operation method of the analog delay locked loop according to the present invention. In accordance with another aspect of the present invention, there is provided a method of operating an analog delay locked loop, the method comprising: generating a flag signal enabled according to a time remaining before the delay locked loop is fixed; Comparing the phase of the internal clock CLK with the feedback clock; The control voltage Vcontrol is controlled and output according to the comparison result, and in the process of adjusting the control voltage Vcontrol, the control voltage Vcontrol is controlled in response to a flag signal. Outputting (Vcontrol); Adjusting a delay value of the internal clock CLK in response to the control voltage Vcontrol; And delaying the internal clock of which the delay value is adjusted by a predetermined time (feedback by the delay model unit) to feed back as a feedback clock.

According to the method as described in the first detailed embodiment of FIG. 6, the outputting of the control voltage outputs a charging current or a discharging current according to a phase comparison result between the internal clock CLK and the feedback clock. A current output step, characterized in that the amount of current is determined according to a flag signal; And a voltage output step of outputting a control voltage Vcontrol, which is charged and discharged by the charging current or the discharge current and whose potential is determined.

In addition, when the method according to the method described in the second detailed embodiment of FIG. 7 outputs the control voltage, the charging current or the discharging current is output according to the phase comparison result of the internal clock CLK and the feedback clock. Doing; And outputs a control voltage Vcontrol that is charged and discharged according to the charging current or the discharge current and whose potential is determined, and a degree of change in the potential of the control voltage Vcontrol according to the charging discharge is determined according to a flag signal. It consists of a voltage output step.

12, 13, and 14 again, a clock data recovery method according to the present invention will be described. The clock data recovery method according to the present invention comprises the steps of: generating a flag signal (flag) is enabled according to the time remaining before the clock data recovery circuit is fixed; Comparing phases of the data DATA and the fed back clock; The control voltage Vontrol is adjusted and output according to the comparison result, and in the process of adjusting the control voltage Vcontrol, the control voltage Vcontrol is controlled in response to a flag signal. Outputting (Vcontrol); Adjusting a delay value of the clock CLK in response to the control voltage Vcontrol, and feeding back a clock whose delay value is adjusted as a feedback clock; And restoring data DATA using a clock whose delay value is adjusted.

According to the method as described in the first detailed embodiment of FIG. 13, the outputting of the control voltage outputs a charging current or a discharging current according to a phase comparison result of the data DATA and the fed back clock. A current output step, characterized in that the amount of current is determined according to a flag signal; And a voltage output step of outputting a control voltage Vcontrol, which is charged and discharged by the charging current or the discharge current and whose potential is determined.

In the case of the method as described in the second detailed embodiment of FIG. 14, the outputting of the control voltage may include outputting a charging current or a discharging current according to a phase comparison result of the data DATA and the fed back clock. step; And outputs a control voltage Vcontrol that is charged and discharged according to the charging current or the discharge current and whose potential is determined, and a degree of change in the potential of the control voltage Vcontrol according to the charging discharge is determined according to a flag signal. It consists of a voltage output step.

Referring to FIGS. 15, 16, and 17 again, a method of operating the phase locked loop according to the present invention will be described. In accordance with another aspect of the present invention, there is provided a method of operating a phase locked loop, the method comprising: generating a flag signal enabled according to a time remaining before the phase locked loop is fixed; Comparing the phase / frequency of the input clock CLK_REF and the fed back output clock CLK; The control voltage Vcontrol is controlled and output according to the comparison result, and in the process of adjusting the control voltage Vcontrol, the control voltage Vcontrol is controlled in response to a flag signal. Outputting (Vcontrol); And outputting an output clock CLK having a frequency determined by the control voltage Vcontrol.

According to the method as described in the first detailed embodiment of FIG. 16, the outputting of the control voltage may include charging current or discharging according to a phase / frequency comparison result of the input clock CLK_REF and the output clock CLK. Outputting a current, the current amount of which is determined according to a flag signal; And a voltage output step of outputting a control voltage Vcontrol, which is charged and discharged by the charging current or the discharge current and whose potential is determined.

According to the method as described in the second detailed embodiment of FIG. 17, the outputting of the control voltage may include charging current or discharging according to a phase / frequency comparison result of the input clock CLK_REF and the output clock CLK. Outputting a current; And outputs a control voltage Vcontrol that is charged and discharged according to the charging current or the discharge current and whose potential is determined, and a degree of change in the potential of the control voltage Vcontrol according to the charging discharge is determined according to a flag signal. It consists of a voltage output step.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be appreciated by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a block diagram of a conventional analog delay lock loop.

2 is a block diagram of a conventional clock data recovery circuit.

3 shows a clock aligned to data via a clock data recovery circuit;

4 is a block diagram of a conventional phase locked loop.

5 is a block diagram of an analog delay locked loop according to the present invention.

FIG. 6 is a first detailed embodiment of the analog delay locked loop of FIG.

7 is a configuration diagram of an embodiment of the charge pump unit 630 of FIG. 6.

8 is a configuration diagram of another embodiment of the charge pump unit 630 of FIG. 6.

FIG. 9 is a second detailed embodiment of the analog delay locked loop of FIG. 5; FIG.

FIG. 10 is a diagram illustrating an embodiment of the loop filter unit 910 of FIG. 9.

11 is a view showing a change in the control voltage (Vcontrol) in the analog delay lock loop according to the present invention.

12 is a block diagram of a clock data recovery circuit according to the present invention.

FIG. 13 is a first detailed embodiment of the clock data recovery circuit of FIG. 12;

FIG. 14 is a second detailed embodiment of the clock data recovery circuit of FIG.

15 is a block diagram of a phase locked loop according to the present invention.

FIG. 16 is a first detailed embodiment of the phase locked loop of FIG.

FIG. 17 is a second detailed embodiment of the phase locked loop of FIG.

* Explanation of symbols for the main parts of the drawings

510, 1210, and 1510: flag signal generation unit 520: clock alignment unit

1220: clock data alignment unit 1230: data recovery unit

1520: frequency control unit

Claims (38)

A flag signal generator for generating a flag signal by comparing the control voltage with a preset reference voltage; A delay model unit for modeling a delay time between an internal clock and an external clock; A phase comparator comparing the output of the delay model and a phase of an internal clock; A control voltage generator configured to increase or decrease the level of the control voltage according to a comparison result of the phase comparator, wherein a width of the increase or decrease of the control voltage is adjusted according to the flag signal; And A voltage control delay line unit configured to adjust a delay value of the internal clock in response to the control voltage and output the delayed value to the delay model unit Analog delay lock loop comprising a. The method of claim 1, The control voltage generator, A charge pump unit configured to output a charge current or a discharge current in response to the output of the phase comparison unit; And A loop filter unit outputting the control voltage in response to the charging current and the discharge current Analog delay lock loop comprising a. 3. The method of claim 2, The charge pump unit, And an amount of current of the charging current and the discharge current is adjusted in response to the flag signal. The method of claim 3, wherein The charge pump unit, It includes two or more pull-up transistors connected in parallel to receive a bias voltage at its gate to supply a current into the charge pump unit, Some of the two or more pull-up transistors, one end is connected or disconnected in response to the flag signal. The method of claim 3, wherein The charge pump unit, Two or more pull-up transistors connected in parallel to receive a first bias voltage at their gates to supply current into the charge pump unit, and to receive a second bias voltage at its gate to leak current from the charge pump unit to the ground terminal; Two or more pull-down transistors connected in parallel, Some of the two or more pull-up transistors have one end connected or disconnected in response to the flag signal, and at least some of the two or more pull-down transistors have one end connected or disconnected in response to the flag signal. Fixed loop. 3. The method of claim 2, The loop filter unit, And charged or discharged in response to the charging current or the discharge current, and including two or more capacitors for outputting the control voltage. At least one of the two or more capacitors is on / off in response to the flag signal. delete The method of claim 1, The flag signal generator, A voltage follower for receiving the control voltage; And A comparator comparing the control voltage received through the voltage follower with the reference voltage and outputting the flag signal as the flag signal; Analog delay lock loop comprising a. The method of claim 1, The flag signal generator, The delay lock loop is enabled when operating at a low frequency, the analog delay lock loop, characterized in that disabled when the high frequency operation. Generating a flag signal by comparing the control voltage with a preset reference voltage; Comparing the phase of the internal clock with the feedback clock; Outputting a control voltage according to the comparison result, and controlling a change width of the control voltage in response to the flag signal in adjusting the control voltage; Adjusting a delay value of the internal clock in response to the control voltage; And Delaying the internal clock whose delay value is adjusted by a predetermined time and feeding back as the feedback clock; Operation method of an analog delay locked loop comprising a. The method of claim 10, Outputting the control voltage, Outputting a charging current or a discharging current according to the comparison result, wherein the current amount is determined according to the flag signal; And A voltage output step of outputting a control voltage which is charged and discharged by the charging current or the discharge current and whose potential is determined; Method of operation of an analog delay locked loop comprising a. The method of claim 10, Outputting the control voltage, Outputting a charging current or a discharge current according to the comparison result; And Outputting a control voltage which is charged and discharged according to the charging current or the discharge current and whose potential is determined, and the degree of change in the potential of the control voltage according to the charging discharge is determined according to the flag signal. Method of operation of an analog delay locked loop comprising a. delete A flag signal generation unit for generating a flag signal by comparing the control voltage and the reference voltage; A phase comparison unit for comparing a phase of a clock and data fed back from the voltage control delay line unit; A control voltage generator configured to increase or decrease the level of the control voltage according to a comparison result of the phase comparator, wherein a width of the increase or decrease of the control voltage is adjusted according to the flag signal; And The voltage control delay line unit adjusting a delay value of an input clock in response to the control voltage and outputting the delayed value to the feedback clock; A data restorer for restoring the data by using the feedback clock; Clock data recovery circuit comprising a. The method of claim 14, The control voltage generator, A charge pump unit configured to output a charge current or a discharge current in response to the output of the phase comparison unit; And A loop filter unit outputting the control voltage in response to the charging current and the discharge current Clock data recovery circuit comprising a. The method of claim 15, The charge pump unit, And a current amount of the charge current and the discharge current in response to the flag signal. The method of claim 16, The charge pump unit, It includes two or more pull-up transistors connected in parallel to receive a bias voltage at its gate to supply a current into the charge pump unit, And at least one end of the at least two pull-up transistors is connected or disconnected in response to the flag signal. The method of claim 16, The charge pump unit, Two or more pull-up transistors connected in parallel to receive a first bias voltage at their gates to supply current into the charge pump unit, and to receive a second bias voltage at its gate to leak current from the charge pump unit to the ground terminal; Two or more pull-down transistors connected in parallel, Some of the two or more pull-up transistors are responsive to the flag signal and one end thereof is connected or disconnected, and some of the two or more pull-down transistors have one end thereof connected or disconnected in response to the flag signal. Circuit. The method of claim 15, The loop filter unit, And charged or discharged in response to the charging current or the discharge current, and including two or more capacitors for outputting the control voltage. Some of the at least two capacitors are turned on / off in response to the flag signal. delete The method of claim 14, The flag signal generator, A voltage follower for receiving the control voltage; And A comparator comparing the control voltage received through the voltage follower with a preset reference voltage and outputting the flag signal; Clock data recovery circuit comprising a. The method of claim 14, The flag signal generator, And the clock data recovery circuit is enabled when the clock data recovery circuit operates at a low frequency and is disabled during the high frequency operation. Generating a flag signal by comparing the control voltage with a preset reference voltage; Comparing the phase of the data and the fed back clock; Outputting a control voltage according to the comparison result, and controlling a change width of the control voltage in response to the flag signal in the process of adjusting the control voltage; Adjusting a delay value of an input clock in response to the control voltage, and feeding back a clock whose delay value is adjusted as the feedback clock; And Restoring the data using the clock with the delay adjusted; Clock data recovery method comprising a. The method of claim 23, wherein Outputting the control voltage, Outputting a charging current or a discharging current according to the comparison result, wherein the current amount is determined according to the flag signal; And A voltage output step of outputting a control voltage which is charged and discharged by the charging current or the discharge current and whose potential is determined; Clock data recovery method comprising the. The method of claim 23, wherein Outputting the control voltage, Outputting a charging current or a discharge current according to the comparison result; And Outputting a control voltage which is charged and discharged according to the charging current or the discharge current and whose potential is determined, and the degree of change in the potential of the control voltage according to the charging discharge is determined according to the flag signal. Clock data recovery method comprising the. delete A flag signal generator for generating a flag signal by comparing the control voltage with a preset reference voltage; A phase / frequency comparison unit comparing phase / frequency of an input clock and an output clock; A control voltage generator configured to increase or decrease the level of the control voltage based on a comparison result at the output of the phase / frequency comparison unit, wherein the width of the increase or decrease is adjusted according to the flag signal; And A voltage controlled oscillator unit for outputting the output clock having a frequency determined by the control voltage Phase locked loop comprising a. 28. The method of claim 27, The control voltage generator, A charge pump unit outputting a charge current or a discharge current in response to the output of the phase / frequency comparison unit; And A loop filter unit outputting the control voltage in response to the charging current and the discharge current Phase locked loop, characterized in that it comprises a. The method of claim 28, The charge pump unit, And a current amount of the charge current and the discharge current is adjusted in response to the flag signal. The method of claim 29, The charge pump unit, It includes two or more pull-up transistors connected in parallel to receive a bias voltage at its gate to supply a current into the charge pump unit, Some of the two or more pull-up transistors, one end is connected or disconnected in response to the flag signal. The method of claim 29, The charge pump unit, Two or more pull-up transistors connected in parallel to receive a first bias voltage at their gates to supply current into the charge pump unit, and to receive a second bias voltage at its gate to leak current from the charge pump unit to the ground terminal; Two or more pull-down transistors connected in parallel, Some of the two or more pull-up transistors have one end connected or disconnected in response to the flag signal, and some of the two or more pull-down transistors have one end connected or disconnected in response to the flag signal. . The method of claim 28, The loop filter unit, It is charged or discharged in response to the charging current or the discharge current, and comprises two or more capacitors for outputting the control voltage, Some of the at least two capacitors are on / off in response to the flag signal. delete 28. The method of claim 27, The flag signal generator, A voltage follower for receiving the control voltage; And A comparator comparing the control voltage received through the voltage follower with the reference voltage and outputting the flag signal as the flag signal; Phase locked loop, characterized in that it comprises a. Generating a flag signal by comparing the control voltage with a preset reference voltage; Comparing the phase / frequency of the input clock and the fed back output clock; Outputting a control voltage according to the comparison result, and controlling a change width of the control voltage in response to the flag signal in adjusting the control voltage; And Outputting the output clock having a frequency determined by the control voltage Method of operation of a phase locked loop comprising a. The method of claim 35, wherein Outputting the control voltage, Outputting a charging current or a discharging current according to the comparison result, wherein the current amount is determined according to the flag signal; And A voltage output step of outputting a control voltage which is charged and discharged by the charging current or the discharge current and whose potential is determined; Method of operation of a phase locked loop comprising a. The method of claim 35, wherein Outputting the control voltage, Outputting a charging current or a discharge current according to the comparison result; And Outputting a control voltage which is charged and discharged according to the charging current or the discharge current and whose potential is determined, and the degree of change in the potential of the control voltage according to the charging discharge is determined according to the flag signal. Method of operation of a phase locked loop comprising a. delete

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