KR100941514B1 - Multi bit phase change memory device and method of fabricating the same - Google Patents

Abstract

It provides a multi-bit phase transition memory device. The device has first and second electrodes facing each other. A data store is disposed between the first electrode and the second electrode. The data store has one or more intermediate electrodes and a plurality of phase change patterns. For example, the data store may have first and second phase change patterns. The first phase change pattern may be in contact with the first electrode. The second phase change pattern may be in contact with the second electrode. The intermediate electrode may be interposed between the first phase transition pattern and the second phase transition pattern. The first electrode and the data reservoir may be disposed in a contact hole penetrating the interlayer insulating layer.

Description

Multi bit phase change memory device and method of fabricating the same

1 is a partial cross-sectional view schematically illustrating a conventional phase change memory device.

FIG. 2 is an equivalent circuit diagram illustrating a portion of a cell array region of a phase change memory device according to first and second embodiments of the present invention.

3 is a plan view illustrating a portion of a cell array region of a phase change memory device according to first and second embodiments of the present invention.

4 is a cross-sectional view taken along the line II ′ of FIG. 3 to explain the phase change memory device according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view taken along the line II ′ of FIG. 3 to explain the phase change memory device according to the second embodiment of the present invention.

6 is an equivalent circuit diagram illustrating a portion of a cell array region of a phase change memory device according to a third embodiment of the present invention.

7 is a cross-sectional view illustrating a phase change memory device according to a third embodiment of the present invention.

8 is an equivalent circuit diagram illustrating a portion of a cell array region of a phase change memory device according to a fourth embodiment of the present invention.

9 is a cross-sectional view illustrating a phase change memory device according to a fourth embodiment of the present invention.

10 to 15 are cross-sectional views taken along the line II ′ of FIG. 3 to explain a method of manufacturing a phase change memory device according to the first embodiment of the present invention.

16 to 18 are cross-sectional views taken along the line II ′ of FIG. 3 to explain another method of manufacturing the phase change memory device according to the first embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a multi-bit phase change memory device and a method of manufacturing the same.

Semiconductor memory devices may be classified into volatile memory devices and nonvolatile memory devices. The nonvolatile memory devices have a characteristic that data stored therein is not destroyed even if their power is cut off. Accordingly, the nonvolatile memory device is widely adopted in a mobile communication system, a mobile memory device, an auxiliary memory device of a digital device, and the like.

There have been many efforts to develop a new memory device having a non-volatile memory characteristic and an efficient structure for improving the integration. A representative example of this is a phase change memory device. The unit cell of the phase change memory device may include a switching device and a data storage serially connected to the switching device. The data store includes a lower electrode electrically connected to the switching element and a phase change material layer in contact with the lower electrode. The phase change material film is a material film that is electrically switched between an amorphous state and a crystalline state or between various resistive states under the crystalline state, depending on the amount of current provided.

1 is a partial cross-sectional view schematically illustrating a conventional phase change memory device.

Referring to FIG. 1, a phase change memory device is formed on a lower insulating film 12 disposed in a predetermined region on a semiconductor substrate 11, a lower electrode 14 disposed in the lower insulating film 12, and an upper insulating film 12. The upper insulating film 13 to cover, the bit line 18 disposed on the upper insulating film 13, the phase transition pattern 16 disposed in the upper insulating film 13 and in contact with the lower electrode 14, and the phase transition. An upper electrode 17 is electrically connected between the pattern 16 and the bit line 18. In addition, the lower electrode 14 is electrically connected to a switching element such as a diode or a transistor.

When a program current flows through the lower electrode 14, joule heat is generated at an interface between the phase change pattern 16 and the lower electrode 14. This joule heat converts a portion of the phase transition pattern 16 (hereinafter referred to as a 'transition region') into an amorphous state or a crystalline state. The resistivity of the transition region 20 having the amorphous state is higher than the resistivity of the transition region 20 having the crystalline state. Accordingly, by sensing the current flowing through the transition region 20 in the read mode, it is possible to determine whether the information stored in the phase transition pattern 16 of the phase change memory device is logic '1' or logic '0'.

Herein, the larger the transition region 20 is, the larger the proportion of the program current is. In this case, the switching element should be designed to have sufficient current driving capability to supply the program current. However, in order to improve the current driving capability, the area occupied by the switching element is increased. In other words, the smaller the transition region 20 is, the better the integration degree of the phase change memory device is.

On the other hand, when two or more bits of information are stored in one cell, since the degree of integration of the phase change memory device can be remarkably improved, research on this has been widely conducted. Since the phase change material film may have various resistance values according to the relative ratio between crystalline and amorphous therein, the phase change material film may theoretically store more than two bits of multi-bit information per cell.

A multi-bit phase change memory device has been disclosed by Ovshinsky in US Patent Publication No. 2004-0178404 entitled "Multiple bit chalcogenide storage device."

According to Obsinski, the phase change memory cell has three electrodes that respectively contact the top, bottom and side surfaces of the phase change material film. The crystal state of the upper region of the phase change material film is changed using electrodes contacting the top and side surfaces of the phase change material film, and the crystal state of the lower region of the phase change material film is used using electrodes contacting the bottom and side surfaces of the phase change material film. Can be changed to store two bits of information per cell. However, the structure and manufacturing process of the phase change memory cell may be complicated, and the configuration of the peripheral circuit for supplying the program current may be complicated.

SUMMARY OF THE INVENTION The present invention has been made in an effort to improve the above-described problems of the related art, and to provide a multi-bit phase change memory device having a small transition region.

Another object of the present invention is to provide a method of manufacturing a multi-bit phase change memory device having a small transition region.

In order to achieve the above technical problem, the present invention provides a multi-bit phase transition memory device. The device has a first electrode provided on the substrate. A second electrode spaced apart from the first electrode is disposed. A data store is disposed between the first electrode and the second electrode. The data store has one or more intermediate electrodes and a plurality of phase change patterns.

In some embodiments of the present disclosure, the data store may have first and second phase change patterns. The first phase change pattern may be in contact with the first electrode. The second phase change pattern may be in contact with the second electrode. The intermediate electrode may be interposed between the first phase transition pattern and the second phase transition pattern.

In another embodiment, another phase change pattern may be disposed between the first phase change pattern and the intermediate electrode. Another intermediate electrode may be interposed between the first phase transition pattern and the other phase transition pattern.

In another embodiment, an interlayer insulating film may be provided on the substrate. The data store may be disposed in a contact hole penetrating the interlayer insulating layer. The first electrode may also be disposed in the contact hole. In addition, a spacer may be interposed between the interlayer insulating layer and the data storage in the contact hole.

In another embodiment, the first electrode is a Ti film, TiSi film, TiN film, TiON film, TiW film, TiAlN film, TiAlON film, TiSiN film, TiBN film, W film, WN film, WON film, WSiN film , WBN film, WCN film, Si film, Ta film, TaSi film, TaN film, TaON film, TaAlN film, TaSiN film, TaCN film, Mo film, MoN film, MoSiN film, MoAlN film, NbN film, ZrSiN film, ZrAlN The film may include one selected from the group consisting of a film, a conductive carbon group film, and a Cu film.

In another embodiment, the intermediate electrode may be a Ti film, a TiSi film, a TiN film, a TiON film, a TiW film, a TiAlN film, a TiAlON film, a TiSiN film, a TiBN film, a W film, a WN film, a WON film, a WSiN film, WBN film, WCN film, Si film, Ta film, TaSi film, TaN film, TaON film, TaAlN film, TaSiN film, TaCN film, Mo film, MoN film, MoSiN film, MoAlN film, NbN film, ZrSiN film, ZrAlN film , A conductive carbon group film, and a Cu film.

In another embodiment, the phase change patterns may be two or more compounds selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, P, O, and C. . The phase change patterns may be different material layers.

In another embodiment, a word line electrically connected to the first electrode may be provided. A bit line may be provided that is electrically connected to the second electrode. A switching element electrically connected to the first electrode may be provided.

The present invention also provides a method of manufacturing a multi-bit phase change memory device. The method includes forming an interlayer insulating film having contact holes on the substrate. A first electrode partially filling the contact hole is formed. A first phase change pattern is formed on the first electrode in the contact hole. An intermediate electrode is formed on the first phase change pattern. A second phase change pattern is formed on the intermediate electrode. A second electrode in contact with the second phase change pattern is formed on the interlayer insulating film.

In some embodiments, a spacer may be formed on sidewalls of the contact hole. The spacer may be formed before and / or after forming the first electrode.

In another embodiment, a first conductive layer may be formed to fill the contact hole. The first electrode may be formed by etching back the first conductive layer. The upper surface of the first electrode may be formed to protrude upward from the center of the contact hole toward the edge. The first electrode is a Ti film, a TiSi film, a TiN film, a TiON film, a TiW film, a TiAlN film, a TiAlON film, a TiSiN film, a TiBN film, a W film, a WN film, a WON film, a WSiN film, a WBN film, a WCN film, Si film, Ta film, TaSi film, TaN film, TaON film, TaAlN film, TaSiN film, TaCN film, Mo film, MoN film, MoSiN film, MoAlN film, NbN film, ZrSiN film, ZrAlN film, conductive carbon group carbon group) film, and one selected from the group consisting of a Cu film.

In another embodiment, a first phase change material layer may be formed on the first electrode to fill the contact hole. The first phase change pattern may be etched back to form the first phase change pattern. The first phase transition pattern may be formed of two or more compounds selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, P, O, and C.

In another embodiment, an intermediate conductive layer filling the contact hole may be formed on the first phase change pattern. The intermediate electrode may be formed by etching back the intermediate conductive layer. The upper surface of the intermediate electrode may be formed to protrude upward from the center of the contact hole toward the edge. The intermediate electrode may be a Ti film, a TiSi film, a TiN film, a TiON film, a TiW film, a TiAlN film, a TiAlON film, a TiSiN film, a TiBN film, a W film, a WN film, a WON film, a WSiN film, a WBN film, a WCN film, or a Si. Film, Ta film, TaSi film, TaN film, TaON film, TaAlN film, TaSiN film, TaCN film, Mo film, MoN film, MoSiN film, MoAlN film, NbN film, ZrSiN film, ZrAlN film, conductive carbon group group) film, and one selected from the group consisting of a Cu film.

In another embodiment, a second phase change material layer may be formed on the intermediate electrode to completely fill the contact hole and cover the interlayer insulating layer. The second phase change material layer may be planarized to form the second phase change pattern until the interlayer insulating layer is exposed. The second phase transition pattern may be formed of two or more compounds selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, P, O, and C. The second phase change pattern may be formed of a material layer different from the first phase change pattern.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed contents are thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Portions denoted by like reference numerals denote like elements throughout the specification.

FIG. 2 is an equivalent circuit diagram illustrating a portion of a cell array region of a phase change memory device according to the first and second embodiments of the present invention, and FIG. 3 illustrates a phase change memory device according to the first and second embodiments of the present invention. A plan view of a portion of the cell array region. That is, FIG. 3 is a plan view illustrating a portion of the cell array region of FIG. 2. 4 is a cross-sectional view taken along the line II ′ of FIG. 3 to explain the phase change memory device according to the first embodiment of the present invention, and FIG. 5 illustrates the phase change memory device according to the second embodiment of the present invention. It is sectional drawing taken along the cutting line II 'of FIG.

2 and 3, the phase change memory devices according to the first and second embodiments of the present invention are word lines WL disposed parallel to each other in a column direction, and bit lines disposed parallel to each other in a row direction. s (BL), and a plurality of data storage in; the (data storages R _P) may be provided.

The bit lines BL may be disposed to intersect the word lines WL. The data stores R _P may be disposed at intersections of the bit lines BL and the word lines WL, respectively. First electrodes 71 may be interposed between the data stores R _P and the word lines WL. Second electrodes 95 may be interposed between the data stores R _P and the bit lines BL.

3 and 4, the phase change memory device according to the first embodiment of the present invention may include word lines 55 and WL and bit lines 97 and BL provided on the substrate 51. The word lines 55 and WL and the bit lines 97 and BL may be disposed to cross each other. The substrate 51 may be a semiconductor substrate such as a silicon wafer.

A lower insulating layer 53 may be provided on the substrate 51. The lower insulating film 53 may be a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. Word lines 55 and WL may be disposed in the lower insulating layer 53. The upper surface of the lower insulating layer 53 and the upper surfaces of the word lines 55 and WL may be exposed on the same plane. The word lines 55 and WL may be conductive patterns such as polysilicon patterns, metal interconnections, or epitaxial semiconductor patterns.

An interlayer insulating layer 57 may be provided on the word lines 55 and WL and the lower insulating layer 53. The interlayer insulating film 57 may be an insulating film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. The interlayer insulating layer 57 may have a planarized upper surface.

A contact hole 61 penetrating the interlayer insulating layer 57 may be disposed on the word lines 55 and WL. Spacers 63 may be disposed on sidewalls of the contact holes 61. The spacer 63 may be an insulating film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. As a result, the inner diameter of the contact hole 61 may be reduced. In addition, the spacer 63 may partially cover the sidewall of the contact hole 61. However, the spacer 63 may be omitted.

The first electrode 71 may be disposed in the contact hole 61. The first electrode 71 may be in contact with the word lines 55 and WL. The first electrode 71 includes a Ti film, a TiSi film, a TiN film, a TiON film, a TiW film, a TiAlN film, a TiAlON film, a TiSiN film, a TiBN film, a W film, a WN film, a WON film, a WSiN film, a WBN film, WCN film, Si film, Ta film, TaSi film, TaN film, TaON film, TaAlN film, TaSiN film, TaCN film, Mo film, MoN film, MoSiN film, MoAlN film, NbN film, ZrSiN film, ZrAlN film, conductive carbon And a combination film selected from the group consisting of a conductive carbon group film, and a Cu film.

The second electrode 95 may be disposed on the interlayer insulating layer 57. The second electrode 95 includes a Ti film, a TiSi film, a TiN film, a TiON film, a TiW film, a TiAlN film, a TiAlON film, a TiSiN film, a TiBN film, a W film, a WN film, a WON film, a WSiN film, a WBN film, WCN film, Si film, Ta film, TaSi film, TaN film, TaON film, TaAlN film, TaSiN film, TaCN film, Mo film, MoN film, MoSiN film, MoAlN film, NbN film, ZrSiN film, ZrAlN film, conductive carbon And a combination film selected from the group consisting of a conductive carbon group film, and a Cu film.

A data storage R _P may be disposed between the first electrode 71 and the second electrode 95. That is, the data storage R _P may be provided in the contact hole 61. The spacer 63 may be interposed between the data storage R _P and the interlayer insulating layer 57.

The data store R _P may include a first phase transition pattern 73 and a second phase transition pattern 77. An intermediate electrode 75 may be interposed between the first phase transition pattern 73 and the second phase transition pattern 77. One end of the intermediate electrode 75 may contact the first phase change pattern 73. The other end of the intermediate electrode 75 may contact the second phase change pattern 77. The first phase change pattern 73 may be in contact with the first electrode 71. The second phase change pattern 77 may be in contact with the second electrode 95.

For example, the first electrode 71, the first phase transition pattern 73, the intermediate electrode 75, and the second phase transition pattern 77 may be sequentially stacked in the contact hole 61. . In this case, the first electrode 71, the first phase transition pattern 73, the intermediate electrode 75, the second phase transition pattern 77, and the second electrode 95 are electrically connected in series. Can be.

The first phase transition pattern 73 may be two or more compounds selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, P, O, and C. have. The second phase transition pattern 77 may be two or more compounds selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, P, O, and C. have. The first phase change pattern 73 and the second phase change pattern 77 may be the same material film or different material films.

The intermediate electrode 75 includes a Ti film, a TiSi film, a TiN film, a TiON film, a TiW film, a TiAlN film, a TiAlON film, a TiSiN film, a TiBN film, a W film, a WN film, a WON film, a WSiN film, a WBN film, and a WCN. Film, Si film, Ta film, TaSi film, TaN film, TaON film, TaAlN film, TaSiN film, TaCN film, Mo film, MoN film, MoSiN film, MoAlN film, NbN film, ZrSiN film, ZrAlN film, conductive carbon group (conductive carbon group) film, and one or a combination film selected from the group consisting of a Cu film. The intermediate electrode 75 may be the same material film as the first electrode 71 or a different material film.

The interlayer insulating layer 57 may be covered with an upper insulating layer 93. An upper surface of the second electrode 95 may be exposed on the upper insulating layer 93. The upper insulating film 93 may be an insulating film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. The bit lines 97 and BL may be disposed on the upper insulating layer 93. The bit lines 97 and BL may be in contact with the second electrode 95. The bit lines 97 and BL may be conductive material layers. The second electrode 95 may be omitted. In this case, the bit lines 97 and BL may be in contact with the second phase change pattern 77.

Referring to FIGS. 2 to 4 again, the operation of the phase change memory device according to the first embodiment of the present invention will be described.

Referring back to FIGS. 2 to 4, the program operation of the phase change memory device according to the first embodiment of the present invention is performed through the data storage R _P through the first electrode 71 and the second electrode 95. This can be done by applying a program current to the.

In detail, when the first phase transition pattern 73 and the second phase transition pattern 77 are both in an amorphous state, the data storage R _P may exhibit a first synthetic resistance. The first composite resistor may be interpreted as a value corresponding to a series connection of the reset resistor of the first phase transition pattern 73 and the reset resistor of the second phase transition pattern 77.

When a first program current is applied to the data store R _P , a first transition region 73T may be generated in the first phase transition pattern 73. The first transition region 73T may be formed adjacent to the first electrode 71. The first transition region 73T may be in a crystalline state. In this case, the data store R _P has a second compound resistance lower than the first compound resistance. The second composite resistor may be interpreted as a value corresponding to a series connection of a program resistor of the first phase transition pattern 73 and a reset resistor of the second phase transition pattern 77.

Subsequently, when a second program current higher than the first program current is applied to the data storage R _P , a second transition region 77T may be generated in the second phase transition pattern 77. The second transition region 77T may be formed adjacent to the intermediate electrode 75. The second transition region 77T may be in a crystalline state. In this case, the data store R _P has a third composite resistance lower than the second composite resistance. The third composite resistor may be interpreted as a value corresponding to the series connection of the program resistance of the first phase transition pattern 73 and the program resistance of the second phase transition pattern 77.

Subsequently, when a third program current higher than the second program current is applied to the data storage R _P , the first phase transition pattern 73 may be reduced to the amorphous state. In this case, the data store R _P exhibits a fourth composite resistance. The fourth compound resistance may be lower than the first compound resistance and higher than the second compound resistance. The fourth composite resistor may be interpreted as a value corresponding to the series connection of the reset resistor of the first phase transition pattern 73 and the program resistor of the second phase transition pattern 77.

Furthermore, when the fourth program current higher than the third program current is applied to the data storage R _P , the second phase transition pattern 77 may be reduced to the amorphous state. In this case, the data store R _P may be reduced to the first synthetic resistance.

As described above, the data storage R _P may be converted into the first to fourth composite resistors by the first to fourth program currents. Accordingly, the data store R _P can be programmed in four states. In this case, the data store R _P may store 2-bit data.

3 and 5, the phase change memory device according to the second exemplary embodiment of the present invention may include word lines 55 and WL and bit lines 97 and BL provided on the substrate 51. A lower insulating layer 53 may be provided on the substrate 51. An interlayer insulating layer 57 may be provided on the word lines 55 and WL and the lower insulating layer 53. A contact hole 61 penetrating the interlayer insulating layer 57 may be disposed on the word lines 55 and WL. Spacers 63 may be disposed on inner walls of the contact holes 61. The first electrode 71 may be disposed in the contact hole 61. The second electrode 95 may be disposed on the interlayer insulating layer 57. Hereinafter, only differences from the phase change memory device according to the first embodiment of the present invention described with reference to FIG. 4 will be described briefly.

A data storage R _P may be disposed between the first electrode 71 and the second electrode 95. That is, the data storage R _P may be provided in the contact hole 61. The spacer 63 may be interposed between the data storage R _P and the interlayer insulating layer 57.

The data store R _P may include a first phase transition pattern 73 and a second phase transition pattern 77. The first phase change pattern 73 may be in contact with the first electrode 71. The second phase change pattern 77 may be in contact with the second electrode 95. A plurality of intermediate electrodes 75, 81, and 85 and a plurality of intermediate phase transition patterns 83 and 87 may be provided between the first phase transition pattern 73 and the second phase transition pattern 77. In addition, other intermediate electrodes (not shown) and other phase transition patterns (not shown) may be provided between the first phase transition pattern 73 and the second phase transition pattern 77.

For example, the intermediate electrodes 75, 81, and 85 may include a first intermediate electrode 75, a second intermediate electrode 81, and a third intermediate electrode 85. The intermediate phase transition patterns 83 and 87 may include a first intermediate phase transition pattern 83 and a second intermediate phase transition pattern 87.

One end of the first intermediate electrode 75 may contact the second phase change pattern 77. The first intermediate phase transition pattern 83 may be disposed on the first phase transition pattern 73. The second intermediate electrode 81 may be interposed between the first phase transition pattern 73 and the first intermediate phase transition pattern 83. The third intermediate electrode 85 may be disposed on the first intermediate phase transition pattern 83. The second intermediate phase transition pattern 87 may be interposed between the third intermediate electrode 85 and the first intermediate electrode 75.

For example, the first electrode 71, the first phase transition pattern 73, the second intermediate electrode 81, the first intermediate phase transition pattern 83, which are sequentially stacked in the contact hole 61, The third intermediate electrode 85, the second intermediate phase transition pattern 87, the first intermediate electrode 75, and the second phase transition pattern 77 may be provided. In this case, the first electrode 71, the first phase transition pattern 73, the second intermediate electrode 81, the first intermediate phase transition pattern 83, the third intermediate electrode 85, and the The second intermediate phase transition pattern 87, the first intermediate electrode 75, the second phase transition pattern 77, and the second electrode 95 may be electrically connected in series.

The first phase transition pattern 73 may be two or more compounds selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, P, O, and C. have. The second phase transition pattern 77 may be two or more compounds selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, P, O, and C. have.

The first intermediate phase transition pattern 83 may be two or more compounds selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, P, O, and C. Can be. The second intermediate phase transition pattern 87 may be two or more compounds selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, P, O, and C. Can be. The first phase transition pattern 73, the second phase transition pattern 77, the first intermediate phase transition pattern 83, and the second intermediate phase transition pattern 87 may be the same material layer or different material layers.

The intermediate electrodes 75, 81, and 85 are formed of a Ti film, a TiSi film, a TiN film, a TiON film, a TiW film, a TiAlN film, a TiAlON film, a TiSiN film, a TiBN film, a W film, a WN film, a WON film, and a WSiN film. , WBN film, WCN film, Si film, Ta film, TaSi film, TaN film, TaON film, TaAlN film, TaSiN film, TaCN film, Mo film, MoN film, MoSiN film, MoAlN film, NbN film, ZrSiN film, ZrAlN It may be one or a combination thereof selected from the group consisting of a film, a conductive carbon group film, and a Cu film. The intermediate electrodes 75, 81, and 85 may be formed of the same material film as the first electrode 71 or a different material film.

The interlayer insulating layer 57 may be covered with an upper insulating layer 93. An upper surface of the second electrode 95 may be exposed on the upper insulating layer 93. The bit lines 97 and BL may be disposed on the upper insulating layer 93. The bit lines 97 and BL may be in contact with the second electrode 95. The bit lines 97 and BL may be conductive material layers. The second electrode 95 may be omitted. In this case, the bit lines 97 and BL may be in contact with the second phase change pattern 77.

The program operation of the phase change memory device according to the second embodiment of the present invention may be performed by applying a program current to the data storage R _P through the first electrode 71 and the second electrode 95. . The first transition region 73T may be generated in the first phase transition pattern 73 by the program current, and the second transition region 77T may be generated in the second phase transition pattern 77. A third transition region 83T may be generated in the first intermediate phase transition pattern 83, and a fourth transition region (not shown) may be generated in the second intermediate phase transition pattern 87. In this case, the data store R _P may store 4-bit data.

As described above, the data store R _P may include other intermediate electrodes (not shown) and other phase change patterns (not shown). In this case, the data store R _P may store multi-bit data.

6 is an equivalent circuit diagram illustrating a portion of a cell array region of a phase change memory device according to a third embodiment of the present invention, and FIG. 7 is a cross-sectional view illustrating a phase change memory device according to a third embodiment of the present invention.

Referring to FIG. 6, a phase change memory device according to a third embodiment of the present invention may include a plurality of bit lines BL arranged in parallel with each other in a column direction, word lines WL disposed in parallel with each other in a row direction. in the data store; it may be provided with a (data storages R _P), and a plurality of diodes (D).

The bit lines BL may be disposed to intersect the word lines WL. Each of the data stores R _P may be disposed at intersections of the bit lines BL and the word lines WL. Each of the diodes D may be connected in series to a corresponding one of the data stores R _P. One ends of the data stores R _P may be connected to a corresponding one of the bit lines BL. Each of the diodes D may be connected to a corresponding one of the word lines WL. The diodes D may serve as switching elements. However, the diodes D may be omitted. Alternatively, the switching element may be a MOS transistor.

Referring to FIG. 7, the phase change memory device according to the third exemplary embodiment may include word lines 155 and WL and bit lines 97 and BL provided on the substrate 51. The substrate 51 may be a semiconductor substrate such as a silicon wafer. The word lines 155 and WL may be defined by the device isolation layer 152 disposed on the substrate 51. The device isolation layer 152 may be an insulating film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof.

The word lines 155 and WL may be impurity ion implantation regions. Alternatively, the word lines 155 and WL may be conductive wires stacked on the substrate 51. The conductive wiring may be a metal wiring or an epitaxial semiconductor pattern.

A lower insulating layer 153 may be provided on the word lines 155 and WL and the device isolation layer 152. The lower insulating layer 153 may be a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. Diodes D may be disposed in the lower insulating layer 153. The diode D may include a first semiconductor pattern 165 and a second semiconductor pattern 166.

The first semiconductor pattern 165 may be an n-type or p-type semiconductor film. The second semiconductor pattern 166 may be a conductive semiconductor layer different from the first semiconductor pattern 165. For example, when the first semiconductor pattern 165 is an n-type semiconductor film, the second semiconductor pattern 166 may be a p-type semiconductor film.

The first semiconductor pattern 165 and the second semiconductor pattern 166 may be sequentially stacked on a predetermined region of the word line 155. In this case, the first semiconductor pattern 165 may be in contact with the word line 155. The diode electrode 169 may be disposed on the second semiconductor pattern 166. The diode electrode 169 may be a conductive film such as a metal film or a metal silicide film. However, the diode electrode 169 may be omitted.

An interlayer insulating layer 57 may be provided on the diodes D and the lower insulating layer 153. The interlayer insulating layer 57 may be a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. A contact hole 61 penetrating the interlayer insulating layer 57 may be disposed on the diode electrode 169.

Subsequently, as described with reference to FIG. 4, a spacer 63, a first electrode 71, a second electrode 95, and a data storage R _P may be disposed. The first electrode 71 may be in contact with the diode electrode 169.

The data store R _P may include a first phase transition pattern 73 and a second phase transition pattern 77. An intermediate electrode 75 may be interposed between the first phase transition pattern 73 and the second phase transition pattern 77. The interlayer insulating layer 57 may be covered with an upper insulating layer 93. The bit lines 97 and BL may be disposed on the upper insulating layer 93. The bit lines 97 and BL may be in contact with the second electrode 95. The second electrode 95 may be omitted. In this case, the bit lines 97 and BL may be in contact with the second phase change pattern 77.

The program operation of the phase change memory device according to the third embodiment of the present invention may be performed by applying a program current to the data storage R _P through the word lines 155 and WL and the bit lines 97 and BL. Can be. The first transition region 73T may be generated in the first phase transition pattern 73 by the program current, and the second transition region 77T may be generated in the second phase transition pattern 77. In this case, the data store R _P may store 2-bit data.

FIG. 8 is an equivalent circuit diagram illustrating a portion of a cell array region of a phase change memory device according to a fourth embodiment of the present invention, and FIG. 9 is a cross-sectional view illustrating a phase change memory device according to a fourth embodiment of the present invention.

Referring to FIG. 8, a phase change memory device according to a fourth embodiment of the present invention may include a plurality of bit lines BL arranged in parallel with each other in a column direction, word lines WL disposed in parallel with each other in a row direction. Data storages R _P and a plurality of MOS transistors Ta.

The bit lines BL may be disposed to intersect the word lines WL. Each of the data stores R _P may be disposed at intersections of the bit lines BL and the word lines WL. Each of the MOS transistors Ta may be connected in series to a corresponding one of the data stores R _P. One ends of the data stores R _P may be connected to a corresponding one of the bit lines BL. Each of the MOS transistors Ta may be connected to a corresponding one of the word lines WL. The MOS transistors Ta may serve as switching elements. However, the MOS transistors Ta may be omitted. Alternatively, the switching element may be a diode.

In another embodiment, a bit line (not shown) may be connected to one of the source / drain regions of the MOS transistor Ta. One end of the data store R _P may be connected to the other of the source / drain regions. In this case, the other end of the data storage R _P may be connected to a plate electrode (not shown).

Referring to FIG. 9, the phase change memory device according to the fourth embodiment of the present invention may include word lines 237 and WL and bit lines 97 and BL provided on the substrate 51. The substrate 51 may be a semiconductor substrate such as a silicon wafer.

An isolation layer 252 may be disposed on the substrate 51 to define an active region. The device isolation layer 252 may be an insulating layer, such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof. The gate electrode 237 may be disposed on the active region. The gate electrode 237 may serve as the word line WL. The gate electrode 237 may be a conductive film such as a polysilicon film, a metal film, a metal silicide film, or a combination thereof. Source / drain regions 233 may be disposed in the active regions on both sides of the gate electrode 237.

The gate electrode 237, the substrate 51, and the source / drain regions 233 may form a MOS transistor (Ta in FIG. 8).

The MOS transistor and the device isolation layer 252 may be covered with a lower insulating layer 253. The lower insulating layer 253 may be a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof.

The source line 245 and the drain pad 247 may be disposed in the lower insulating layer 253. The source line 245 may be electrically connected to one of the source / drain regions 233 through a source plug 244 passing through the lower insulating layer 253. The drain pad 247 may be electrically connected to another one of the source / drain regions 233 through the drain plug 241 passing through the lower insulating layer 253. The source line 245, the drain pad 247, the source plug 244, and the drain plug 241 may be conductive layers.

An interlayer insulating layer 57 may be provided on the lower insulating layer 253. The interlayer insulating film 57 may be an insulating film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. A contact hole 61 penetrating the interlayer insulating layer 57 may be disposed on the drain pad 247.

Subsequently, as described with reference to FIG. 4, a spacer 63, a first electrode 71, a second electrode 95, and a data storage R _P may be disposed. The first electrode 71 may be in contact with the drain pad 247.

The data store R _P may include a first phase transition pattern 73 and a second phase transition pattern 77. An intermediate electrode 75 may be interposed between the first phase transition pattern 73 and the second phase transition pattern 77. The interlayer insulating layer 57 may be covered with an upper insulating layer 93. The bit lines 97 and BL may be disposed on the upper insulating layer 93. The bit lines 97 and BL may be in contact with the second electrode 95. The second electrode 95 may be omitted. In this case, the bit lines 97 and BL may be in contact with the second phase change pattern 77.

In another embodiment, the bit lines 97 and BL may be replaced with plate electrodes (not shown). In this case, the source line 245 may serve as a bit line.

The program operation of the phase change memory device according to the fourth exemplary embodiment of the present invention may be performed by applying a program current to the data storage R _P through the first electrode 71 and the second electrode 95. . The first transition region 73T may be generated in the first phase transition pattern 73 by the program current, and the second transition region 77T may be generated in the second phase transition pattern 77. In this case, the data store R _P may store 2-bit data.

10 to 15 are cross-sectional views taken along the line II ′ of FIG. 3 to explain a method of manufacturing a phase change memory device according to the first embodiment of the present invention.

Referring to FIG. 10, a lower insulating film 53 may be formed on the substrate 51. The substrate 51 may be a semiconductor substrate such as a silicon wafer. The lower insulating film 53 may be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof.

Word lines 55 and WL may be formed in the lower insulating layer 53. The upper surface of the lower insulating layer 53 and the upper surfaces of the word lines 55 and WL may be exposed on the same plane. The word lines 55 and WL may be formed of a conductive pattern such as a polysilicon pattern, a metal wiring, or an epitaxial seam semiconductor pattern.

Referring to FIG. 11, an interlayer insulating layer 57 may be formed on the word lines 55 and WL and the lower insulating layer 53. The interlayer insulating film 57 may be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. The interlayer insulating layer 57 may be formed to have a flattened upper surface.

A contact hole 61 penetrating the interlayer insulating layer 57 may be formed on the word lines 55 and WL. The word lines 55 and WL may be exposed at the bottom of the contact hole 61. The interlayer insulating layer 57 may be exposed on sidewalls of the contact hole 61. Spacers 63 may be formed on sidewalls of the contact holes 61. The spacer 63 may be formed of an insulating film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. As a result, the inner diameter of the contact hole 61 may be reduced. The word lines 55 and WL may be exposed at the bottom of the contact hole 61. In addition, the spacer 63 may be formed to partially cover the sidewall of the contact hole 61. However, the spacer 63 may be omitted.

Referring to FIG. 12, a first electrode 71 may be formed in the contact hole 61. The first electrode 71 may be formed by etching back the first conductive layer after forming the first conductive layer filling the contact hole 61. The first electrode 71 may be in contact with the word lines 55 and WL. The first electrode 71 may be formed in the lower region of the contact hole 61. That is, the first electrode 71 may be formed at a level lower than the upper surface of the interlayer insulating layer 57.

The spacer 63 may be formed after the first electrode 71 is formed. In this case, the spacer 63 may be formed at an upper level than the first electrode 71.

The first electrode 71 includes a Ti film, a TiSi film, a TiN film, a TiON film, a TiW film, a TiAlN film, a TiAlON film, a TiSiN film, a TiBN film, a W film, a WN film, a WON film, a WSiN film, a WBN film, WCN film, Si film, Ta film, TaSi film, TaN film, TaON film, TaAlN film, TaSiN film, TaCN film, Mo film, MoN film, MoSiN film, MoAlN film, NbN film, ZrSiN film, ZrAlN film, conductive carbon It may be formed of one or a combination of these selected from a group consisting of a conductive carbon group film and a Cu film.

A first phase change material layer 72 may be formed on the first electrode 71 to fill the contact hole 61. The first phase change material film 72 is composed of two or more compounds selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, P, O, and C. Can be formed.

Referring to FIG. 13, a first phase change pattern 73 may be formed on the first electrode 71 by etching back the first phase change material layer 72. The first phase change pattern 73 may be formed in an intermediate region of the contact hole 61. That is, the first phase change pattern 73 may be formed at a level lower than the upper surface of the interlayer insulating layer 57. The first phase change pattern 73 may be in contact with the first electrode 71.

An intermediate electrode 75 may be formed on the first phase change pattern 73. The intermediate electrode 75 may be formed by forming an intermediate conductive layer filling the contact hole 61 on the first phase transition pattern 73 and then etching back the intermediate conductive layer. The intermediate electrode 75 may contact the first phase change pattern 73. The intermediate electrode 75 may be formed in an intermediate region of the contact hole 61. That is, the intermediate electrode 75 may be formed at a level lower than the upper surface of the interlayer insulating layer 57.

The intermediate electrode 75 includes a Ti film, a TiSi film, a TiN film, a TiON film, a TiW film, a TiAlN film, a TiAlON film, a TiSiN film, a TiBN film, a W film, a WN film, a WON film, a WSiN film, a WBN film, and a WCN. Film, Si film, Ta film, TaSi film, TaN film, TaON film, TaAlN film, TaSiN film, TaCN film, Mo film, MoN film, MoSiN film, MoAlN film, NbN film, ZrSiN film, ZrAlN film, conductive carbon group (conductive carbon group) film, and one or a combination thereof selected from the group consisting of a Cu film. The intermediate electrode 75 may be formed of the same material film as the first electrode 71 or may be formed of another material film.

Referring to FIG. 14, a second phase change pattern 77 may be formed on the intermediate electrode 75.

In detail, a second phase change material layer may be formed on the intermediate electrode 75 to fill the contact hole 61. The second phase change material layer may be planarized to form the second phase change pattern 77. In order to planarize the second phase change material film, a chemical mechanical polishing (CMP) process using the interlayer insulating film 57 as a stop film may be applied. In this case, the upper surfaces of the interlayer insulating film 57 and the second phase change pattern 77 may be exposed on the same plane. Alternatively, an etch back process may be applied to planarization of the second phase change material layer.

The second phase transition pattern 77 is formed of two or more compounds selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, P, O, and C. can do. The second phase transition pattern 77 may be formed of the same material layer as the first phase transition pattern 73 or may be formed of different material layers.

The first phase change pattern 73, the intermediate electrode 75 and the second phase change pattern 77 is data storage; can form a (storage data R _P).

Referring to FIG. 15, a second electrode 95 and an upper insulating layer 93 may be formed on the interlayer insulating layer 57. The second electrode 95 may be formed to contact the second phase change pattern 77 on the interlayer insulating layer 57. The upper insulating layer 93 may be formed to cover the interlayer insulating layer 57.

The second electrode 95 includes a Ti film, a TiSi film, a TiN film, a TiON film, a TiW film, a TiAlN film, a TiAlON film, a TiSiN film, a TiBN film, a W film, a WN film, a WON film, a WSiN film, a WBN film, WCN film, Si film, Ta film, TaSi film, TaN film, TaON film, TaAlN film, TaSiN film, TaCN film, Mo film, MoN film, MoSiN film, MoAlN film, NbN film, ZrSiN film, ZrAlN film, conductive carbon It may be formed of one or a combination of these selected from a group consisting of a conductive carbon group film and a Cu film. The second electrode 95 may be formed of the same material film as the first electrode 71 or may be formed of another material film. The upper insulating layer 93 may be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof.

The bit lines 97 and BL may be formed on the upper insulating layer 93. The bit lines 97 and BL may be in contact with the second electrode 95. The bit lines 97 and BL may be formed of a conductive material film. The second electrode 95 may be omitted. In this case, the bit lines 97 and BL may be in contact with the second phase change pattern 77.

16 to 18 are cross-sectional views taken along the line II ′ of FIG. 3 to explain another method of manufacturing the phase change memory device according to the first embodiment of the present invention.

Referring to FIG. 16, the lower insulating film 53, the word lines 55 and WL, the interlayer insulating film 57, and the contact hole 61 are formed on the substrate 51 in the same manner as described with reference to FIGS. 10 and 11. ) And the spacer 63 can be formed. In the following, only the differences will be briefly described.

The first electrode 71 ′ may be formed in the contact hole 61. The first electrode 71 ′ may be formed by forming a first conductive layer filling the contact hole 61 and then etching back the first conductive layer. The etch back of the first conductive layer may be performed using an isotropic etching process. In this case, the etching rate of the first conductive layer may be relatively slow from the center of the contact hole 61 toward the edge. As a result, the upper surface of the first electrode 71 ′ may be formed in a concave shape. That is, the upper surface of the first electrode 71 ′ may protrude upward from the center of the contact hole 61 toward the edge.

The first electrode 71 ′ may be in contact with the word lines 55 and WL. The first electrode 71 ′ may be formed in a lower region of the contact hole 61. That is, the first electrode 71 ′ may be formed at a level lower than an upper surface of the interlayer insulating layer 57.

The spacer 63 may be formed after forming the first electrode 71 ′. In this case, the spacer 63 may be formed at an upper level than the first electrode 71 ′.

The first electrode 71 'is formed of a Ti film, a TiSi film, a TiN film, a TiON film, a TiW film, a TiAlN film, a TiAlON film, a TiSiN film, a TiBN film, a W film, a WN film, a WON film, a WSiN film, and a WBN film. , WCN film, Si film, Ta film, TaSi film, TaN film, TaON film, TaAlN film, TaSiN film, TaCN film, Mo film, MoN film, MoSiN film, MoAlN film, NbN film, ZrSiN film, ZrAlN film, conductive It may be formed of one or a combination thereof selected from the group consisting of a carbon group film and a Cu film.

A first phase change material layer 72 may be formed on the first electrode 71 ′ to fill the contact hole 61. The first phase change material film 72 is composed of two or more compounds selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, P, O, and C. Can be formed.

Referring to FIG. 17, a first phase change pattern 73 ′ may be formed on the first electrode 71 ′ by etching back the first phase change material layer 72. The first phase change pattern 73 ′ may be formed in an intermediate region of the contact hole 61. That is, the first phase change pattern 73 ′ may be formed at a level lower than an upper surface of the interlayer insulating layer 57. The first phase change pattern 73 ′ may be in contact with the first electrode 71 ′.

An intermediate electrode 75 ′ may be formed on the first phase change pattern 73 ′. The intermediate electrode 75 ′ may be formed by forming an intermediate conductive layer filling the contact hole 61 on the first phase transfer pattern 73 ′ and then etching back the intermediate conductive layer. The upper surface of the intermediate electrode 75 'may be formed in a concave shape. That is, the upper surface of the intermediate electrode 75 ′ may protrude upward from the center of the contact hole 61 toward the edge.

The intermediate electrode 75 ′ may be in contact with the first phase change pattern 73 ′. The intermediate electrode 75 ′ may be formed in an intermediate region of the contact hole 61. That is, the intermediate electrode 75 ′ may be formed at a level lower than the upper surface of the interlayer insulating layer 57.

The intermediate electrode 75 'includes a Ti film, a TiSi film, a TiN film, a TiON film, a TiW film, a TiAlN film, a TiAlON film, a TiSiN film, a TiBN film, a W film, a WN film, a WON film, a WSiN film, a WBN film, WCN film, Si film, Ta film, TaSi film, TaN film, TaON film, TaAlN film, TaSiN film, TaCN film, Mo film, MoN film, MoSiN film, MoAlN film, NbN film, ZrSiN film, ZrAlN film, conductive carbon It may be formed of one or a combination of these selected from a group consisting of a conductive carbon group film and a Cu film. The intermediate electrode 75 ′ may be formed of the same material film as the first electrode 71 ′ or may be formed of another material film.

Referring to FIG. 18, a second phase change pattern 77 may be formed on the intermediate electrode 75 ′ in the same manner as described with reference to FIGS. 14 and 15. The first phase transition pattern 73 ′, the intermediate electrode 75 ′, and the second phase transition pattern 77 may constitute a data storage R _P.

The second electrode 95 and the upper insulating layer 93 may be formed on the interlayer insulating layer 57. Bit lines 97 and BL may be formed on the upper insulating layer 93. The second electrode 95 may be omitted. In this case, the bit lines 97 and BL may be in contact with the second phase change pattern 77.

As described above, according to the present invention, first and second electrodes facing each other are provided on a substrate. A data store is disposed between the first electrode and the second electrode. The data store has one or more intermediate electrodes and a plurality of phase change patterns. The first electrode and the data reservoir are disposed in a contact hole penetrating the interlayer insulating layer. The data store may store multi-bit data corresponding to the number of phase change patterns. As a result, a multi-bit phase change memory device having small transition regions can be implemented.

Claims (26)

A first electrode formed on the substrate; A second electrode spaced apart from the first electrode; A data store formed between the first electrode and the second electrode and having one or more intermediate electrodes and a plurality of phase change patterns; And An interlayer insulating film formed on the substrate, wherein the first electrode and the data reservoir are disposed in a contact hole penetrating the interlayer insulating layer, and the data reservoir is self-aligned to the first electrode. The upper surface of each of the intermediate electrodes protruding upward from the center of the contact hole toward the edge. The method of claim 1, The data store A first phase transition pattern in contact with the first electrode; A second phase change pattern in contact with the second electrode; And And a phase electrode interposed between the first phase transition pattern and the second phase transition pattern. The method of claim 2, Another phase transition pattern disposed between the first phase transition pattern and the intermediate electrode; And And another intermediate electrode interposed between the first phase change pattern and the other phase change pattern. delete delete The method of claim 1, And a spacer formed between the interlayer insulating layer and the data storage in the contact hole. The method of claim 1, The first electrode is a Ti film, a TiSi film, a TiN film, a TiON film, a TiW film, a TiAlN film, a TiAlON film, a TiSiN film, a TiBN film, a W film, a WN film, a WON film, a WSiN film, a WBN film, a WCN film, Si film, Ta film, TaSi film, TaN film, TaON film, TaAlN film, TaSiN film, TaCN film, Mo film, MoN film, MoSiN film, MoAlN film, NbN film, ZrSiN film, ZrAlN film, conductive carbon group Carbon group) A phase change memory device comprising one selected from the group consisting of a film and a Cu film. The method of claim 1, The intermediate electrode may be a Ti film, a TiSi film, a TiN film, a TiON film, a TiW film, a TiAlN film, a TiAlON film, a TiSiN film, a TiBN film, a W film, a WN film, a WON film, a WSiN film, a WBN film, a WCN film, or a Si. Film, Ta film, TaSi film, TaN film, TaON film, TaAlN film, TaSiN film, TaCN film, Mo film, MoN film, MoSiN film, MoAlN film, NbN film, ZrSiN film, ZrAlN film, conductive carbon group group) a phase change memory device comprising one selected from the group consisting of a film and a Cu film. The method of claim 1, The phase change patterns are at least two compounds selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, P, O, and C. The method of claim 9, The phase change pattern is a phase change memory device, characterized in that the different material film. Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 1, A word line electrically connected to the first electrode; And Claim 12 was abandoned upon payment of a registration fee. The method of claim 1, And a switching device electrically connected to the first electrode. An interlayer insulating film having a contact hole is formed on the substrate, Forming a first electrode partially filling the contact hole, Forming a first phase change pattern on the first electrode in the contact hole, Forming an intermediate electrode on the first phase change pattern, Forming a second phase change pattern on the intermediate electrode, Forming a second electrode in contact with the second phase change pattern on the interlayer insulating layer, wherein the first phase change pattern is self-aligned to the first electrode, and an upper surface of the intermediate electrode A method of manufacturing a phase change memory device protruding upward from the center of the contact hole toward the edge. Claim 14 was abandoned when the registration fee was paid. The method of claim 13, Before forming the first electrode, And forming spacers on sidewalls of the contact holes. Claim 15 was abandoned upon payment of a registration fee. After forming the first electrode, And forming spacers on sidewalls of the contact holes. Claim 16 was abandoned upon payment of a setup registration fee. The method of claim 13, Forming the first electrode Forming a first conductive layer filling the contact hole, A method of manufacturing a phase change memory device comprising etching back the first conductive layer. Claim 17 was abandoned upon payment of a registration fee. The method of claim 16, The upper surface of the first electrode is a method of manufacturing a phase-transfer memory device, characterized in that formed to protrude upward from the center of the contact hole toward the edge. Claim 18 was abandoned upon payment of a set-up fee. The method of claim 13, The first electrode is a Ti film, a TiSi film, a TiN film, a TiON film, a TiW film, a TiAlN film, a TiAlON film, a TiSiN film, a TiBN film, a W film, a WN film, a WON film, a WSiN film, a WBN film, a WCN film, Si film, Ta film, TaSi film, TaN film, TaON film, TaAlN film, TaSiN film, TaCN film, Mo film, MoN film, MoSiN film, MoAlN film, NbN film, ZrSiN film, ZrAlN film, conductive carbon group Carbon group) A method of manufacturing a phase-transfer memory device, characterized in that formed in one selected from the group consisting of a film and a Cu film. Claim 19 was abandoned upon payment of a registration fee. The method of claim 13, Forming the first phase transition pattern is Forming a first phase change material layer filling the contact hole, A method of manufacturing a phase change memory device comprising etching back the first phase change material layer. Claim 20 was abandoned upon payment of a registration fee. The method of claim 13, The first phase transition pattern is formed of two or more compounds selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, P, O, and C. Method of manufacturing a memory device. Claim 21 was abandoned upon payment of a registration fee. The method of claim 13, Forming the intermediate electrode Forming an intermediate conductive layer filling the contact hole, A method of manufacturing a phase change memory device comprising etching back the intermediate conductive layer. delete Claim 23 was abandoned upon payment of a set-up fee. The method of claim 13, The intermediate electrode may be a Ti film, a TiSi film, a TiN film, a TiON film, a TiW film, a TiAlN film, a TiAlON film, a TiSiN film, a TiBN film, a W film, a WN film, a WON film, a WSiN film, a WBN film, a WCN film, or a Si. Film, Ta film, TaSi film, TaN film, TaON film, TaAlN film, TaSiN film, TaCN film, Mo film, MoN film, MoSiN film, MoAlN film, NbN film, ZrSiN film, ZrAlN film, conductive carbon group group) A method for manufacturing a phase change memory device, characterized in that formed in one selected from the group consisting of a film and a Cu film. Claim 24 was abandoned when the setup registration fee was paid. The method of claim 13, Forming the second phase change pattern Forming a second phase change material film completely filling the contact hole and covering the interlayer insulating film, And planarizing the second phase change material film until the interlayer insulating film is exposed. Claim 25 was abandoned upon payment of a registration fee. The method of claim 13, Claim 26 was abandoned upon payment of a registration fee. The method of claim 25, And the second phase change pattern is formed of a different material layer from the first phase change pattern.

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